Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49399 |
1 |
|
|
T1 |
80 |
|
T2 |
81 |
|
T3 |
9 |
auto[1] |
1722 |
1 |
|
|
T14 |
10 |
|
T15 |
8 |
|
T19 |
14 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50330 |
1 |
|
|
T1 |
64 |
|
T2 |
81 |
|
T3 |
9 |
auto[1] |
791 |
1 |
|
|
T1 |
16 |
|
T48 |
20 |
|
T46 |
22 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49376 |
1 |
|
|
T1 |
80 |
|
T2 |
75 |
|
T3 |
9 |
auto[1] |
1745 |
1 |
|
|
T2 |
6 |
|
T17 |
9 |
|
T49 |
5 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49341 |
1 |
|
|
T1 |
80 |
|
T2 |
72 |
|
T3 |
9 |
auto[1] |
1780 |
1 |
|
|
T2 |
9 |
|
T17 |
6 |
|
T49 |
3 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49356 |
1 |
|
|
T1 |
80 |
|
T2 |
72 |
|
T3 |
9 |
auto[1] |
1765 |
1 |
|
|
T2 |
9 |
|
T17 |
16 |
|
T49 |
6 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
46745 |
1 |
|
|
T1 |
80 |
|
T2 |
81 |
|
T11 |
66 |
no_err_inj |
4376 |
1 |
|
|
T3 |
9 |
|
T4 |
6 |
|
T5 |
40 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49395 |
1 |
|
|
T1 |
80 |
|
T2 |
81 |
|
T3 |
9 |
auto[1] |
1726 |
1 |
|
|
T14 |
9 |
|
T15 |
8 |
|
T19 |
18 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50387 |
1 |
|
|
T1 |
68 |
|
T2 |
81 |
|
T3 |
9 |
auto[1] |
734 |
1 |
|
|
T1 |
12 |
|
T48 |
14 |
|
T46 |
15 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36237 |
1 |
|
|
T1 |
80 |
|
T3 |
9 |
|
T11 |
66 |
auto[1] |
14884 |
1 |
|
|
T2 |
81 |
|
T4 |
6 |
|
T5 |
51 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49352 |
1 |
|
|
T1 |
80 |
|
T2 |
67 |
|
T3 |
9 |
auto[1] |
1769 |
1 |
|
|
T2 |
14 |
|
T17 |
10 |
|
T49 |
4 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49307 |
1 |
|
|
T1 |
80 |
|
T2 |
72 |
|
T3 |
9 |
auto[1] |
1814 |
1 |
|
|
T2 |
9 |
|
T17 |
7 |
|
T49 |
12 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49298 |
1 |
|
|
T1 |
80 |
|
T2 |
70 |
|
T3 |
9 |
auto[1] |
1823 |
1 |
|
|
T2 |
11 |
|
T17 |
10 |
|
T49 |
9 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49432 |
1 |
|
|
T1 |
80 |
|
T2 |
81 |
|
T3 |
9 |
auto[1] |
1689 |
1 |
|
|
T14 |
6 |
|
T15 |
6 |
|
T19 |
15 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49017 |
1 |
|
|
T1 |
80 |
|
T2 |
81 |
|
T3 |
9 |
auto[1] |
2104 |
1 |
|
|
T5 |
11 |
|
T19 |
45 |
|
T69 |
8 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50369 |
1 |
|
|
T1 |
64 |
|
T2 |
81 |
|
T3 |
9 |
auto[1] |
752 |
1 |
|
|
T1 |
16 |
|
T48 |
22 |
|
T46 |
23 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50332 |
1 |
|
|
T1 |
65 |
|
T2 |
81 |
|
T3 |
9 |
auto[1] |
789 |
1 |
|
|
T1 |
15 |
|
T48 |
14 |
|
T46 |
21 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50365 |
1 |
|
|
T1 |
59 |
|
T2 |
81 |
|
T3 |
9 |
auto[1] |
756 |
1 |
|
|
T1 |
21 |
|
T48 |
18 |
|
T46 |
16 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48600 |
1 |
|
|
T1 |
80 |
|
T2 |
81 |
|
T3 |
9 |
auto[1] |
2521 |
1 |
|
|
T18 |
10 |
|
T19 |
47 |
|
T81 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47444 |
1 |
|
|
T1 |
80 |
|
T2 |
81 |
|
T3 |
9 |
auto[1] |
3677 |
1 |
|
|
T59 |
82 |
|
T60 |
69 |
|
T62 |
69 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49315 |
1 |
|
|
T1 |
80 |
|
T2 |
74 |
|
T3 |
9 |
auto[1] |
1806 |
1 |
|
|
T2 |
7 |
|
T17 |
11 |
|
T49 |
6 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49353 |
1 |
|
|
T1 |
80 |
|
T2 |
72 |
|
T3 |
9 |
auto[1] |
1768 |
1 |
|
|
T2 |
9 |
|
T17 |
8 |
|
T49 |
6 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49328 |
1 |
|
|
T1 |
80 |
|
T2 |
74 |
|
T3 |
9 |
auto[1] |
1793 |
1 |
|
|
T2 |
7 |
|
T17 |
8 |
|
T49 |
7 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49498 |
1 |
|
|
T1 |
80 |
|
T2 |
81 |
|
T3 |
9 |
auto[1] |
1623 |
1 |
|
|
T14 |
1 |
|
T15 |
7 |
|
T19 |
19 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
45773 |
1 |
|
|
T1 |
80 |
|
T2 |
81 |
|
T3 |
9 |
auto[1] |
5348 |
1 |
|
|
T12 |
91 |
|
T14 |
5 |
|
T15 |
4 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47321 |
1 |
|
|
T1 |
80 |
|
T2 |
81 |
|
T3 |
9 |
auto[1] |
3800 |
1 |
|
|
T11 |
66 |
|
T16 |
57 |
|
T47 |
83 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51121 |
1 |
|
|
T1 |
80 |
|
T2 |
81 |
|
T3 |
9 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49409 |
1 |
|
|
T1 |
80 |
|
T2 |
81 |
|
T3 |
9 |
auto[1] |
1712 |
1 |
|
|
T14 |
8 |
|
T15 |
6 |
|
T19 |
21 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49374 |
1 |
|
|
T1 |
80 |
|
T2 |
81 |
|
T3 |
9 |
auto[1] |
1747 |
1 |
|
|
T14 |
10 |
|
T15 |
7 |
|
T19 |
15 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49409 |
1 |
|
|
T1 |
80 |
|
T2 |
81 |
|
T3 |
9 |
auto[1] |
1712 |
1 |
|
|
T14 |
5 |
|
T15 |
11 |
|
T19 |
18 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
45488 |
1 |
|
|
T1 |
80 |
|
T2 |
81 |
|
T11 |
66 |
auto[0] |
no_err_inj |
3112 |
1 |
|
|
T3 |
9 |
|
T4 |
6 |
|
T5 |
40 |
auto[1] |
err_inj |
1257 |
1 |
|
|
T18 |
4 |
|
T19 |
24 |
|
T81 |
4 |
auto[1] |
no_err_inj |
1264 |
1 |
|
|
T18 |
6 |
|
T19 |
23 |
|
T81 |
8 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46952 |
1 |
|
|
T1 |
80 |
|
T2 |
72 |
|
T3 |
9 |
auto[0] |
auto[1] |
1648 |
1 |
|
|
T2 |
9 |
|
T17 |
8 |
|
T49 |
6 |
auto[1] |
auto[0] |
2401 |
1 |
|
|
T18 |
9 |
|
T19 |
45 |
|
T81 |
12 |
auto[1] |
auto[1] |
120 |
1 |
|
|
T18 |
1 |
|
T19 |
2 |
|
T90 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46924 |
1 |
|
|
T1 |
80 |
|
T2 |
72 |
|
T3 |
9 |
auto[0] |
auto[1] |
1676 |
1 |
|
|
T2 |
9 |
|
T17 |
7 |
|
T49 |
12 |
auto[1] |
auto[0] |
2383 |
1 |
|
|
T18 |
10 |
|
T19 |
46 |
|
T81 |
12 |
auto[1] |
auto[1] |
138 |
1 |
|
|
T19 |
1 |
|
T22 |
1 |
|
T96 |
5 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46949 |
1 |
|
|
T1 |
80 |
|
T2 |
74 |
|
T3 |
9 |
auto[0] |
auto[1] |
1651 |
1 |
|
|
T2 |
7 |
|
T17 |
8 |
|
T49 |
7 |
auto[1] |
auto[0] |
2379 |
1 |
|
|
T18 |
10 |
|
T19 |
45 |
|
T81 |
12 |
auto[1] |
auto[1] |
142 |
1 |
|
|
T19 |
2 |
|
T22 |
2 |
|
T96 |
11 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46953 |
1 |
|
|
T1 |
80 |
|
T2 |
72 |
|
T3 |
9 |
auto[0] |
auto[1] |
1647 |
1 |
|
|
T2 |
9 |
|
T17 |
6 |
|
T49 |
3 |
auto[1] |
auto[0] |
2388 |
1 |
|
|
T18 |
10 |
|
T19 |
44 |
|
T81 |
12 |
auto[1] |
auto[1] |
133 |
1 |
|
|
T19 |
3 |
|
T96 |
8 |
|
T149 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46967 |
1 |
|
|
T1 |
80 |
|
T2 |
72 |
|
T3 |
9 |
auto[0] |
auto[1] |
1633 |
1 |
|
|
T2 |
9 |
|
T17 |
16 |
|
T49 |
6 |
auto[1] |
auto[0] |
2389 |
1 |
|
|
T18 |
10 |
|
T19 |
43 |
|
T81 |
12 |
auto[1] |
auto[1] |
132 |
1 |
|
|
T19 |
4 |
|
T22 |
2 |
|
T90 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47001 |
1 |
|
|
T1 |
80 |
|
T2 |
75 |
|
T3 |
9 |
auto[0] |
auto[1] |
1599 |
1 |
|
|
T2 |
6 |
|
T17 |
9 |
|
T49 |
5 |
auto[1] |
auto[0] |
2375 |
1 |
|
|
T18 |
8 |
|
T19 |
45 |
|
T81 |
10 |
auto[1] |
auto[1] |
146 |
1 |
|
|
T18 |
2 |
|
T19 |
2 |
|
T81 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35204 |
1 |
|
|
T1 |
80 |
|
T3 |
9 |
|
T11 |
66 |
auto[0] |
auto[1] |
1033 |
1 |
|
|
T14 |
10 |
|
T15 |
8 |
|
T19 |
3 |
auto[1] |
auto[0] |
14195 |
1 |
|
|
T2 |
81 |
|
T4 |
6 |
|
T5 |
51 |
auto[1] |
auto[1] |
689 |
1 |
|
|
T19 |
11 |
|
T22 |
12 |
|
T91 |
7 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35190 |
1 |
|
|
T1 |
80 |
|
T3 |
9 |
|
T11 |
66 |
auto[0] |
auto[1] |
1047 |
1 |
|
|
T14 |
9 |
|
T15 |
8 |
|
T19 |
6 |
auto[1] |
auto[0] |
14205 |
1 |
|
|
T2 |
81 |
|
T4 |
6 |
|
T5 |
51 |
auto[1] |
auto[1] |
679 |
1 |
|
|
T19 |
12 |
|
T22 |
9 |
|
T91 |
9 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35032 |
1 |
|
|
T1 |
80 |
|
T3 |
9 |
|
T11 |
66 |
auto[0] |
auto[1] |
1205 |
1 |
|
|
T19 |
12 |
|
T69 |
8 |
|
T22 |
9 |
auto[1] |
auto[0] |
13985 |
1 |
|
|
T2 |
81 |
|
T4 |
6 |
|
T5 |
40 |
auto[1] |
auto[1] |
899 |
1 |
|
|
T5 |
11 |
|
T19 |
33 |
|
T22 |
42 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35232 |
1 |
|
|
T1 |
80 |
|
T3 |
9 |
|
T11 |
66 |
auto[0] |
auto[1] |
1005 |
1 |
|
|
T14 |
6 |
|
T15 |
6 |
|
T19 |
9 |
auto[1] |
auto[0] |
14200 |
1 |
|
|
T2 |
81 |
|
T4 |
6 |
|
T5 |
51 |
auto[1] |
auto[1] |
684 |
1 |
|
|
T19 |
6 |
|
T22 |
15 |
|
T91 |
10 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31595 |
1 |
|
|
T1 |
80 |
|
T3 |
9 |
|
T11 |
66 |
auto[0] |
auto[1] |
4642 |
1 |
|
|
T12 |
91 |
|
T14 |
5 |
|
T15 |
4 |
auto[1] |
auto[0] |
14178 |
1 |
|
|
T2 |
81 |
|
T4 |
6 |
|
T5 |
51 |
auto[1] |
auto[1] |
706 |
1 |
|
|
T19 |
11 |
|
T22 |
14 |
|
T91 |
11 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35184 |
1 |
|
|
T1 |
80 |
|
T3 |
9 |
|
T11 |
66 |
auto[0] |
auto[1] |
1053 |
1 |
|
|
T17 |
8 |
|
T49 |
6 |
|
T72 |
8 |
auto[1] |
auto[0] |
14169 |
1 |
|
|
T2 |
72 |
|
T4 |
6 |
|
T5 |
51 |
auto[1] |
auto[1] |
715 |
1 |
|
|
T2 |
9 |
|
T18 |
1 |
|
T19 |
16 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35148 |
1 |
|
|
T1 |
80 |
|
T3 |
9 |
|
T11 |
66 |
auto[0] |
auto[1] |
1089 |
1 |
|
|
T17 |
11 |
|
T49 |
6 |
|
T72 |
7 |
auto[1] |
auto[0] |
14167 |
1 |
|
|
T2 |
74 |
|
T4 |
6 |
|
T5 |
51 |
auto[1] |
auto[1] |
717 |
1 |
|
|
T2 |
7 |
|
T19 |
13 |
|
T20 |
4 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35171 |
1 |
|
|
T1 |
80 |
|
T3 |
9 |
|
T11 |
66 |
auto[0] |
auto[1] |
1066 |
1 |
|
|
T17 |
7 |
|
T49 |
12 |
|
T72 |
5 |
auto[1] |
auto[0] |
14136 |
1 |
|
|
T2 |
72 |
|
T4 |
6 |
|
T5 |
51 |
auto[1] |
auto[1] |
748 |
1 |
|
|
T2 |
9 |
|
T19 |
7 |
|
T20 |
11 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35190 |
1 |
|
|
T1 |
80 |
|
T3 |
9 |
|
T11 |
66 |
auto[0] |
auto[1] |
1047 |
1 |
|
|
T17 |
10 |
|
T49 |
4 |
|
T72 |
13 |
auto[1] |
auto[0] |
14162 |
1 |
|
|
T2 |
67 |
|
T4 |
6 |
|
T5 |
51 |
auto[1] |
auto[1] |
722 |
1 |
|
|
T2 |
14 |
|
T19 |
6 |
|
T20 |
14 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35192 |
1 |
|
|
T1 |
80 |
|
T3 |
9 |
|
T11 |
66 |
auto[0] |
auto[1] |
1045 |
1 |
|
|
T17 |
6 |
|
T49 |
3 |
|
T72 |
8 |
auto[1] |
auto[0] |
14149 |
1 |
|
|
T2 |
72 |
|
T4 |
6 |
|
T5 |
51 |
auto[1] |
auto[1] |
735 |
1 |
|
|
T2 |
9 |
|
T19 |
9 |
|
T20 |
11 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35219 |
1 |
|
|
T1 |
80 |
|
T3 |
9 |
|
T11 |
66 |
auto[0] |
auto[1] |
1018 |
1 |
|
|
T17 |
9 |
|
T49 |
5 |
|
T72 |
4 |
auto[1] |
auto[0] |
14157 |
1 |
|
|
T2 |
75 |
|
T4 |
6 |
|
T5 |
51 |
auto[1] |
auto[1] |
727 |
1 |
|
|
T2 |
6 |
|
T18 |
2 |
|
T19 |
11 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35209 |
1 |
|
|
T1 |
80 |
|
T3 |
9 |
|
T11 |
66 |
auto[0] |
auto[1] |
1028 |
1 |
|
|
T14 |
5 |
|
T15 |
11 |
|
T19 |
6 |
auto[1] |
auto[0] |
14200 |
1 |
|
|
T2 |
81 |
|
T4 |
6 |
|
T5 |
51 |
auto[1] |
auto[1] |
684 |
1 |
|
|
T19 |
12 |
|
T22 |
16 |
|
T91 |
10 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35205 |
1 |
|
|
T1 |
80 |
|
T3 |
9 |
|
T11 |
66 |
auto[0] |
auto[1] |
1032 |
1 |
|
|
T14 |
10 |
|
T15 |
7 |
|
T19 |
6 |
auto[1] |
auto[0] |
14169 |
1 |
|
|
T2 |
81 |
|
T4 |
6 |
|
T5 |
51 |
auto[1] |
auto[1] |
715 |
1 |
|
|
T19 |
9 |
|
T22 |
16 |
|
T91 |
10 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34823 |
1 |
|
|
T1 |
80 |
|
T3 |
9 |
|
T11 |
66 |
auto[0] |
auto[1] |
1414 |
1 |
|
|
T19 |
40 |
|
T81 |
12 |
|
T22 |
20 |
auto[1] |
auto[0] |
13777 |
1 |
|
|
T2 |
81 |
|
T4 |
6 |
|
T5 |
51 |
auto[1] |
auto[1] |
1107 |
1 |
|
|
T18 |
10 |
|
T19 |
7 |
|
T90 |
11 |