Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93695500

1

T1

28555

T2

113765

T3

35707

auto[1]

1354116

1

T1

1485

T2

3234

T14

396

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93710494

1

T1

28456

T2

114059

T3

35707

auto[1]

1339122

1

T1

1584

T2

2940

T14

594

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6880506	1			T1	7348		T2	20823		T3	1026
auto[IdleSt]	19948947	1			T1	5391		T2	3463		T3	1403
auto[ClkMuxSt]	33815	1			T1	65		T3	9		T4	6
auto[CntIncrSt]	33593	1			T1	65		T3	9		T4	6
auto[CntProgSt]	1579239	1			T1	114		T3	111		T4	55
auto[TransCheckSt]	26278	1			T1	49		T3	9		T4	6
auto[TokenHashSt]	38064610	1			T1	540		T3	32137		T4	64392
auto[FlashRmaSt]	34319	1			T1	159		T3	9		T4	6
auto[TokenCheck0St]	12065	1			T1	42		T3	9		T4	6
auto[TokenCheck1St]	8854	1			T1	31		T3	9		T4	6
auto[TransProgSt]	397682	1			T1	61		T3	87		T4	133
auto[PostTransSt]	11568602	1			T1	9662		T3	889		T4	1916
auto[ScrapSt]	109050	1			T5	961		T19	611		T50	852
auto[EscalateSt]	6172272	1			T1	4293		T2	22580		T14	1425
auto[InvalidSt]	10177880	1			T1	2220		T2	70124		T17	9440

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1904	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10177880	1			T1	2220		T2	70124		T17	9440
EscalateSt	6172272	1			T1	4293		T2	22580		T14	1425
ScrapSt	109050	1			T5	961		T19	611		T50	852
PostTransSt	11568602	1			T1	9662		T3	889		T4	1916
TransProgSt	397682	1			T1	61		T3	87		T4	133
TokenCheck1St	8854	1			T1	31		T3	9		T4	6
TokenCheck0St	12065	1			T1	42		T3	9		T4	6
FlashRmaSt	34319	1			T1	159		T3	9		T4	6
TokenHashSt	38064610	1			T1	540		T3	32137		T4	64392
TransCheckSt	26278	1			T1	49		T3	9		T4	6
CntProgSt	1579239	1			T1	114		T3	111		T4	55
CntIncrSt	33593	1			T1	65		T3	9		T4	6
ClkMuxSt	33815	1			T1	65		T3	9		T4	6
IdleSt	19948947	1			T1	5391		T2	3463		T3	1403
ResetSt	6880506	1			T1	7348		T2	20823		T3	1026
arcs[ResetSt=>IdleSt]	51474	1			T1	81		T2	71		T3	9
arcs[IdleSt=>ScrapSt]	268	1			T5	1		T19	2		T50	1
arcs[IdleSt=>ClkMuxSt]	33645	1			T1	65		T3	9		T4	6
arcs[ClkMuxSt=>CntIncrSt]	33593	1			T1	65		T3	9		T4	6
arcs[CntIncrSt=>PostTransSt]	1747	1			T14	10		T15	7		T19	15
arcs[CntIncrSt=>CntProgSt]	31789	1			T1	65		T3	9		T4	6
arcs[CntProgSt=>PostTransSt]	4584	1			T1	16		T14	8		T15	8
arcs[CntProgSt=>TransCheckSt]	26278	1			T1	49		T3	9		T4	6
arcs[TransCheckSt=>PostTransSt]	3601	1			T11	41		T14	5		T15	11
arcs[TransCheckSt=>TokenHashSt]	22502	1			T1	49		T3	9		T4	6
arcs[TokenHashSt=>PostTransSt]	9623	1			T1	7		T11	9		T12	91
arcs[TokenHashSt=>FlashRmaSt]	12157	1			T1	42		T3	9		T4	6
arcs[FlashRmaSt=>TokenCheck0St]	12065	1			T1	42		T3	9		T4	6
arcs[TokenCheck0St=>PostTransSt]	3186	1			T1	11		T11	8		T14	7
arcs[TokenCheck0St=>TokenCheck1St]	8854	1			T1	31		T3	9		T4	6
arcs[TokenCheck1St=>PostTransSt]	663	1			T11	8		T14	2		T15	2
arcs[TransProgSt=>PostTransSt]	7376	1			T1	31		T3	9		T4	6
arcs[IdleSt=>EscalateSt]	229	1			T60	8		T62	7		T63	6
arcs[ClkMuxSt=>EscalateSt]	52	1			T59	1		T60	1		T61	1
arcs[CntIncrSt=>EscalateSt]	57	1			T59	4		T60	1		T62	2
arcs[CntProgSt=>EscalateSt]	927	1			T59	13		T60	16		T62	5
arcs[TransCheckSt=>EscalateSt]	175	1			T59	7		T60	2		T62	8
arcs[TokenHashSt=>EscalateSt]	722	1			T59	19		T60	15		T62	16
arcs[FlashRmaSt=>EscalateSt]	92	1			T59	2		T62	2		T63	3
arcs[TokenCheck0St=>EscalateSt]	25	1			T60	1		T62	1		T63	1
arcs[TokenCheck1St=>EscalateSt]	154	1			T59	1		T60	3		T62	2
arcs[TransProgSt=>EscalateSt]	661	1			T59	22		T60	16		T62	11
arcs[PostTransSt=>EscalateSt]	4896	1			T1	16		T14	10		T15	8
arcs[InvalidSt=>EscalateSt]	13240	1			T1	15		T2	63		T17	67

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6880331	1			T1	7348		T2	20823		T3	1026
auto[0]	auto[IdleSt]	19948789	1			T1	5391		T2	3463		T3	1403
auto[0]	auto[ClkMuxSt]	33774	1			T1	65		T3	9		T4	6
auto[0]	auto[CntIncrSt]	33558	1			T1	65		T3	9		T4	6
auto[0]	auto[CntProgSt]	1578629	1			T1	114		T3	111		T4	55
auto[0]	auto[TransCheckSt]	26150	1			T1	49		T3	9		T4	6
auto[0]	auto[TokenHashSt]	38064131	1			T1	540		T3	32137		T4	64392
auto[0]	auto[FlashRmaSt]	34248	1			T1	159		T3	9		T4	6
auto[0]	auto[TokenCheck0St]	12052	1			T1	42		T3	9		T4	6
auto[0]	auto[TokenCheck1St]	8749	1			T1	31		T3	9		T4	6
auto[0]	auto[TransProgSt]	397245	1			T1	61		T3	87		T4	133
auto[0]	auto[PostTransSt]	11566143	1			T1	9654		T3	889		T4	1916
auto[0]	auto[ScrapSt]	109015	1			T5	961		T19	611		T50	852
auto[0]	auto[EscalateSt]	4829574	1			T1	2823		T2	19379		T14	1033
auto[0]	auto[InvalidSt]	10171208	1			T1	2213		T2	70091		T17	9403
auto[1]	auto[ResetSt]	175	1			T59	5		T60	2		T62	4
auto[1]	auto[IdleSt]	158	1			T60	7		T62	6		T63	4
auto[1]	auto[ClkMuxSt]	41	1			T59	1		T61	1		T192	1
auto[1]	auto[CntIncrSt]	35	1			T59	3		T60	1		T62	1
auto[1]	auto[CntProgSt]	610	1			T59	6		T60	10		T62	3
auto[1]	auto[TransCheckSt]	128	1			T59	6		T60	1		T62	6
auto[1]	auto[TokenHashSt]	479	1			T59	14		T60	10		T62	13
auto[1]	auto[FlashRmaSt]	71	1			T59	1		T62	1		T63	1
auto[1]	auto[TokenCheck0St]	13	1			T63	1		T192	1		T193	1
auto[1]	auto[TokenCheck1St]	105	1			T60	3		T62	2		T63	2
auto[1]	auto[TransProgSt]	437	1			T59	14		T60	10		T62	6
auto[1]	auto[PostTransSt]	2459	1			T1	8		T14	4		T15	2
auto[1]	auto[ScrapSt]	35	1			T59	1		T60	1		T62	1
auto[1]	auto[EscalateSt]	1342698	1			T1	1470		T2	3201		T14	392
auto[1]	auto[InvalidSt]	6672	1			T1	7		T2	33		T17	37

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6880354	1			T1	7348		T2	20823		T3	1026
auto[0]	auto[IdleSt]	19948801	1			T1	5391		T2	3463		T3	1403
auto[0]	auto[ClkMuxSt]	33783	1			T1	65		T3	9		T4	6
auto[0]	auto[CntIncrSt]	33551	1			T1	65		T3	9		T4	6
auto[0]	auto[CntProgSt]	1578626	1			T1	114		T3	111		T4	55
auto[0]	auto[TransCheckSt]	26164	1			T1	49		T3	9		T4	6
auto[0]	auto[TokenHashSt]	38064142	1			T1	540		T3	32137		T4	64392
auto[0]	auto[FlashRmaSt]	34255	1			T1	159		T3	9		T4	6
auto[0]	auto[TokenCheck0St]	12048	1			T1	42		T3	9		T4	6
auto[0]	auto[TokenCheck1St]	8752	1			T1	31		T3	9		T4	6
auto[0]	auto[TransProgSt]	397235	1			T1	61		T3	87		T4	133
auto[0]	auto[PostTransSt]	11566065	1			T1	9654		T3	889		T4	1916
auto[0]	auto[ScrapSt]	108998	1			T5	961		T19	611		T50	852
auto[0]	auto[EscalateSt]	4844504	1			T1	2725		T2	19670		T14	837
auto[0]	auto[InvalidSt]	10171312	1			T1	2212		T2	70094		T17	9410
auto[1]	auto[ResetSt]	152	1			T59	2		T60	1		T62	4
auto[1]	auto[IdleSt]	146	1			T60	5		T62	3		T63	4
auto[1]	auto[ClkMuxSt]	32	1			T60	1		T61	1		T192	1
auto[1]	auto[CntIncrSt]	42	1			T59	2		T62	2		T192	2
auto[1]	auto[CntProgSt]	613	1			T59	7		T60	11		T62	3
auto[1]	auto[TransCheckSt]	114	1			T59	5		T60	2		T62	5
auto[1]	auto[TokenHashSt]	468	1			T59	13		T60	6		T62	9
auto[1]	auto[FlashRmaSt]	64	1			T59	2		T62	2		T63	2
auto[1]	auto[TokenCheck0St]	17	1			T60	1		T62	1		T63	1
auto[1]	auto[TokenCheck1St]	102	1			T59	1		T60	1		T62	1
auto[1]	auto[TransProgSt]	447	1			T59	15		T60	12		T62	9
auto[1]	auto[PostTransSt]	2537	1			T1	8		T14	6		T15	6
auto[1]	auto[ScrapSt]	52	1			T59	2		T60	1		T63	1
auto[1]	auto[EscalateSt]	1327768	1			T1	1568		T2	2910		T14	588
auto[1]	auto[InvalidSt]	6568	1			T1	8		T2	30		T17	30