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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 97.99 95.59 93.40 100.00 98.55 98.51 96.47


Total test records in report: 1000
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T812 /workspace/coverage/default/48.lc_ctrl_state_failure.4242653597 Jul 24 07:01:40 PM PDT 24 Jul 24 07:02:00 PM PDT 24 660024727 ps
T813 /workspace/coverage/default/19.lc_ctrl_sec_token_mux.411121036 Jul 24 06:59:45 PM PDT 24 Jul 24 06:59:54 PM PDT 24 1289100019 ps
T814 /workspace/coverage/default/13.lc_ctrl_smoke.774545021 Jul 24 06:59:05 PM PDT 24 Jul 24 06:59:08 PM PDT 24 49431083 ps
T815 /workspace/coverage/default/41.lc_ctrl_stress_all.3709003606 Jul 24 07:01:24 PM PDT 24 Jul 24 07:03:44 PM PDT 24 19607022448 ps
T816 /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1327563464 Jul 24 06:58:24 PM PDT 24 Jul 24 06:58:32 PM PDT 24 446155118 ps
T817 /workspace/coverage/default/17.lc_ctrl_jtag_errors.1598519671 Jul 24 06:59:37 PM PDT 24 Jul 24 07:00:32 PM PDT 24 1894437364 ps
T818 /workspace/coverage/default/21.lc_ctrl_alert_test.4040157393 Jul 24 06:59:57 PM PDT 24 Jul 24 06:59:58 PM PDT 24 35027139 ps
T819 /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3413919926 Jul 24 06:57:03 PM PDT 24 Jul 24 06:57:10 PM PDT 24 1219530802 ps
T820 /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2155618863 Jul 24 06:57:56 PM PDT 24 Jul 24 06:58:04 PM PDT 24 397316946 ps
T821 /workspace/coverage/default/38.lc_ctrl_jtag_access.938661308 Jul 24 07:01:07 PM PDT 24 Jul 24 07:01:13 PM PDT 24 732248099 ps
T822 /workspace/coverage/default/2.lc_ctrl_sec_mubi.2482298656 Jul 24 06:57:34 PM PDT 24 Jul 24 06:57:58 PM PDT 24 2194775498 ps
T157 /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.4208663383 Jul 24 06:57:06 PM PDT 24 Jul 24 07:00:38 PM PDT 24 37992698452 ps
T823 /workspace/coverage/default/26.lc_ctrl_prog_failure.3242538319 Jul 24 07:00:13 PM PDT 24 Jul 24 07:00:16 PM PDT 24 73597297 ps
T824 /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2017452489 Jul 24 07:00:31 PM PDT 24 Jul 24 07:00:40 PM PDT 24 279975405 ps
T825 /workspace/coverage/default/49.lc_ctrl_state_failure.678401782 Jul 24 07:02:00 PM PDT 24 Jul 24 07:02:26 PM PDT 24 742587381 ps
T826 /workspace/coverage/default/26.lc_ctrl_jtag_access.1381434662 Jul 24 07:00:12 PM PDT 24 Jul 24 07:00:19 PM PDT 24 1108011634 ps
T827 /workspace/coverage/default/32.lc_ctrl_state_post_trans.3846850119 Jul 24 07:00:37 PM PDT 24 Jul 24 07:00:47 PM PDT 24 162559667 ps
T828 /workspace/coverage/default/49.lc_ctrl_smoke.3761801177 Jul 24 07:01:48 PM PDT 24 Jul 24 07:01:50 PM PDT 24 52536450 ps
T829 /workspace/coverage/default/0.lc_ctrl_stress_all.4025864377 Jul 24 06:57:07 PM PDT 24 Jul 24 06:57:56 PM PDT 24 4022465170 ps
T78 /workspace/coverage/default/25.lc_ctrl_smoke.530576119 Jul 24 07:00:16 PM PDT 24 Jul 24 07:00:17 PM PDT 24 53756864 ps
T830 /workspace/coverage/default/20.lc_ctrl_state_post_trans.3332484508 Jul 24 06:59:46 PM PDT 24 Jul 24 06:59:55 PM PDT 24 584697036 ps
T831 /workspace/coverage/default/35.lc_ctrl_stress_all.3347732395 Jul 24 07:00:58 PM PDT 24 Jul 24 07:03:29 PM PDT 24 10473894839 ps
T832 /workspace/coverage/default/37.lc_ctrl_alert_test.3606092340 Jul 24 07:01:07 PM PDT 24 Jul 24 07:01:08 PM PDT 24 17288919 ps
T833 /workspace/coverage/default/4.lc_ctrl_sec_mubi.720159287 Jul 24 06:58:03 PM PDT 24 Jul 24 06:58:21 PM PDT 24 2379790669 ps
T834 /workspace/coverage/default/9.lc_ctrl_stress_all.133182021 Jul 24 06:58:41 PM PDT 24 Jul 24 07:05:02 PM PDT 24 21689801239 ps
T835 /workspace/coverage/default/26.lc_ctrl_security_escalation.775746632 Jul 24 07:00:15 PM PDT 24 Jul 24 07:00:23 PM PDT 24 330716947 ps
T836 /workspace/coverage/default/0.lc_ctrl_jtag_priority.2025763609 Jul 24 06:56:59 PM PDT 24 Jul 24 06:57:02 PM PDT 24 601369269 ps
T837 /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1159851773 Jul 24 06:59:22 PM PDT 24 Jul 24 06:59:26 PM PDT 24 258784957 ps
T838 /workspace/coverage/default/32.lc_ctrl_errors.3030897597 Jul 24 07:00:38 PM PDT 24 Jul 24 07:00:53 PM PDT 24 2921317665 ps
T839 /workspace/coverage/default/19.lc_ctrl_jtag_access.1822587146 Jul 24 06:59:44 PM PDT 24 Jul 24 06:59:47 PM PDT 24 1267855660 ps
T840 /workspace/coverage/default/8.lc_ctrl_state_failure.1258953876 Jul 24 06:58:26 PM PDT 24 Jul 24 06:58:45 PM PDT 24 195416284 ps
T841 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1492146942 Jul 24 07:00:37 PM PDT 24 Jul 24 07:00:51 PM PDT 24 434187297 ps
T842 /workspace/coverage/default/15.lc_ctrl_alert_test.4250677319 Jul 24 06:59:20 PM PDT 24 Jul 24 06:59:22 PM PDT 24 38935976 ps
T79 /workspace/coverage/default/46.lc_ctrl_alert_test.3791726316 Jul 24 07:01:41 PM PDT 24 Jul 24 07:01:42 PM PDT 24 21072390 ps
T843 /workspace/coverage/default/5.lc_ctrl_jtag_errors.3837785848 Jul 24 06:58:03 PM PDT 24 Jul 24 06:58:58 PM PDT 24 7035213696 ps
T844 /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.186912418 Jul 24 06:59:31 PM PDT 24 Jul 24 06:59:44 PM PDT 24 556286208 ps
T845 /workspace/coverage/default/3.lc_ctrl_state_post_trans.2159895530 Jul 24 06:57:40 PM PDT 24 Jul 24 06:57:47 PM PDT 24 178979114 ps
T846 /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1582993357 Jul 24 06:58:07 PM PDT 24 Jul 24 06:58:08 PM PDT 24 14768909 ps
T847 /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2075571820 Jul 24 06:57:49 PM PDT 24 Jul 24 06:58:00 PM PDT 24 397946330 ps
T848 /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3287916712 Jul 24 06:58:38 PM PDT 24 Jul 24 06:58:55 PM PDT 24 1106507750 ps
T849 /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.3587492047 Jul 24 06:59:10 PM PDT 24 Jul 24 07:08:22 PM PDT 24 32038605876 ps
T850 /workspace/coverage/default/23.lc_ctrl_errors.3882267935 Jul 24 07:00:16 PM PDT 24 Jul 24 07:00:26 PM PDT 24 266136582 ps
T851 /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3139056337 Jul 24 07:01:27 PM PDT 24 Jul 24 07:01:29 PM PDT 24 54778322 ps
T104 /workspace/coverage/default/27.lc_ctrl_state_failure.2137226861 Jul 24 07:00:16 PM PDT 24 Jul 24 07:00:51 PM PDT 24 391732147 ps
T852 /workspace/coverage/default/46.lc_ctrl_jtag_access.4144161432 Jul 24 07:01:35 PM PDT 24 Jul 24 07:01:36 PM PDT 24 124665084 ps
T853 /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.1678876981 Jul 24 07:01:40 PM PDT 24 Jul 24 07:07:33 PM PDT 24 135993572781 ps
T854 /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.553950341 Jul 24 06:56:51 PM PDT 24 Jul 24 06:56:53 PM PDT 24 23943837 ps
T855 /workspace/coverage/default/47.lc_ctrl_state_post_trans.2073772827 Jul 24 07:01:41 PM PDT 24 Jul 24 07:01:45 PM PDT 24 93196557 ps
T52 /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1654331601 Jul 24 06:58:20 PM PDT 24 Jul 24 06:58:21 PM PDT 24 13625125 ps
T856 /workspace/coverage/default/19.lc_ctrl_alert_test.62789627 Jul 24 06:59:46 PM PDT 24 Jul 24 06:59:47 PM PDT 24 12487934 ps
T857 /workspace/coverage/default/13.lc_ctrl_sec_mubi.2363974254 Jul 24 06:59:05 PM PDT 24 Jul 24 06:59:15 PM PDT 24 1294174636 ps
T858 /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3430045899 Jul 24 06:58:34 PM PDT 24 Jul 24 06:58:59 PM PDT 24 3844226695 ps
T859 /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3215521437 Jul 24 06:59:56 PM PDT 24 Jul 24 06:59:58 PM PDT 24 83491362 ps
T860 /workspace/coverage/default/4.lc_ctrl_prog_failure.2369809654 Jul 24 06:57:51 PM PDT 24 Jul 24 06:57:54 PM PDT 24 278463428 ps
T861 /workspace/coverage/default/15.lc_ctrl_state_failure.3491469724 Jul 24 06:59:20 PM PDT 24 Jul 24 06:59:43 PM PDT 24 198941837 ps
T862 /workspace/coverage/default/17.lc_ctrl_state_post_trans.3322395190 Jul 24 06:59:27 PM PDT 24 Jul 24 06:59:33 PM PDT 24 136967083 ps
T863 /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3687797054 Jul 24 06:57:13 PM PDT 24 Jul 24 06:57:44 PM PDT 24 1668738783 ps
T864 /workspace/coverage/default/44.lc_ctrl_alert_test.3173350708 Jul 24 07:01:28 PM PDT 24 Jul 24 07:01:30 PM PDT 24 85492201 ps
T865 /workspace/coverage/default/3.lc_ctrl_jtag_access.2286026840 Jul 24 06:57:51 PM PDT 24 Jul 24 06:57:59 PM PDT 24 1047264938 ps
T866 /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2003351847 Jul 24 07:01:07 PM PDT 24 Jul 24 07:01:08 PM PDT 24 46550942 ps
T867 /workspace/coverage/default/45.lc_ctrl_alert_test.574003182 Jul 24 07:01:34 PM PDT 24 Jul 24 07:01:36 PM PDT 24 159128817 ps
T868 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3751453697 Jul 24 07:01:34 PM PDT 24 Jul 24 07:01:47 PM PDT 24 338990309 ps
T869 /workspace/coverage/default/41.lc_ctrl_sec_mubi.1211261794 Jul 24 07:01:21 PM PDT 24 Jul 24 07:01:35 PM PDT 24 1374947016 ps
T870 /workspace/coverage/default/18.lc_ctrl_stress_all.3303125717 Jul 24 06:59:43 PM PDT 24 Jul 24 07:02:54 PM PDT 24 23947954954 ps
T871 /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2073963164 Jul 24 07:00:12 PM PDT 24 Jul 24 07:00:13 PM PDT 24 30409868 ps
T105 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.494980551 Jul 24 04:59:21 PM PDT 24 Jul 24 04:59:23 PM PDT 24 212570990 ps
T106 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.4141443566 Jul 24 04:59:19 PM PDT 24 Jul 24 04:59:23 PM PDT 24 439772964 ps
T112 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3309610971 Jul 24 04:59:17 PM PDT 24 Jul 24 04:59:18 PM PDT 24 17263091 ps
T113 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.757952962 Jul 24 04:58:51 PM PDT 24 Jul 24 04:58:53 PM PDT 24 32297844 ps
T110 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.158571896 Jul 24 04:59:08 PM PDT 24 Jul 24 04:59:09 PM PDT 24 22106955 ps
T107 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1120396195 Jul 24 04:59:29 PM PDT 24 Jul 24 04:59:32 PM PDT 24 112045387 ps
T163 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2441135800 Jul 24 04:59:00 PM PDT 24 Jul 24 04:59:01 PM PDT 24 18447792 ps
T175 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2644364151 Jul 24 04:59:05 PM PDT 24 Jul 24 04:59:07 PM PDT 24 33852907 ps
T144 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2321035902 Jul 24 04:59:17 PM PDT 24 Jul 24 04:59:19 PM PDT 24 32987473 ps
T176 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.4176112856 Jul 24 04:59:13 PM PDT 24 Jul 24 04:59:15 PM PDT 24 112218384 ps
T177 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3466268040 Jul 24 04:59:08 PM PDT 24 Jul 24 04:59:10 PM PDT 24 17827930 ps
T108 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2494516616 Jul 24 04:58:56 PM PDT 24 Jul 24 04:58:59 PM PDT 24 101404332 ps
T134 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3084483259 Jul 24 04:59:00 PM PDT 24 Jul 24 04:59:02 PM PDT 24 321711338 ps
T178 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2820137443 Jul 24 04:59:00 PM PDT 24 Jul 24 04:59:02 PM PDT 24 141536254 ps
T135 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3974423250 Jul 24 04:58:57 PM PDT 24 Jul 24 04:58:59 PM PDT 24 87023925 ps
T137 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1403852963 Jul 24 04:58:58 PM PDT 24 Jul 24 04:59:09 PM PDT 24 5381450872 ps
T109 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4072994031 Jul 24 04:59:02 PM PDT 24 Jul 24 04:59:05 PM PDT 24 283464915 ps
T128 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.681133649 Jul 24 04:58:47 PM PDT 24 Jul 24 04:58:51 PM PDT 24 835855397 ps
T111 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4266719307 Jul 24 04:58:48 PM PDT 24 Jul 24 04:58:51 PM PDT 24 143279777 ps
T136 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.4279499706 Jul 24 04:59:00 PM PDT 24 Jul 24 04:59:02 PM PDT 24 201155339 ps
T872 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.100422290 Jul 24 04:58:58 PM PDT 24 Jul 24 04:59:02 PM PDT 24 555183393 ps
T873 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.278008516 Jul 24 04:58:57 PM PDT 24 Jul 24 04:58:59 PM PDT 24 59771609 ps
T874 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1516834510 Jul 24 04:58:59 PM PDT 24 Jul 24 04:59:03 PM PDT 24 530595498 ps
T119 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3619162508 Jul 24 04:59:15 PM PDT 24 Jul 24 04:59:17 PM PDT 24 243727591 ps
T875 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2672567967 Jul 24 04:58:57 PM PDT 24 Jul 24 04:58:59 PM PDT 24 20687413 ps
T876 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3582449614 Jul 24 04:58:54 PM PDT 24 Jul 24 04:58:57 PM PDT 24 482056966 ps
T120 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1677240245 Jul 24 04:59:07 PM PDT 24 Jul 24 04:59:10 PM PDT 24 599477520 ps
T114 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2620163680 Jul 24 04:58:46 PM PDT 24 Jul 24 04:58:50 PM PDT 24 1508212042 ps
T877 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3946394737 Jul 24 04:59:02 PM PDT 24 Jul 24 04:59:05 PM PDT 24 3307719055 ps
T878 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2756739562 Jul 24 04:59:00 PM PDT 24 Jul 24 04:59:03 PM PDT 24 57853187 ps
T879 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2087408985 Jul 24 04:58:56 PM PDT 24 Jul 24 04:58:59 PM PDT 24 244723072 ps
T164 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1782305006 Jul 24 04:58:59 PM PDT 24 Jul 24 04:59:01 PM PDT 24 45676684 ps
T125 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.555447637 Jul 24 04:59:19 PM PDT 24 Jul 24 04:59:22 PM PDT 24 87755725 ps
T145 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3162745495 Jul 24 04:59:06 PM PDT 24 Jul 24 04:59:09 PM PDT 24 91346284 ps
T880 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1442150940 Jul 24 04:58:52 PM PDT 24 Jul 24 04:58:54 PM PDT 24 220413473 ps
T881 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2803726929 Jul 24 04:58:58 PM PDT 24 Jul 24 04:59:00 PM PDT 24 317154536 ps
T882 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1165222212 Jul 24 04:58:59 PM PDT 24 Jul 24 04:59:01 PM PDT 24 63721937 ps
T883 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1151614458 Jul 24 04:59:04 PM PDT 24 Jul 24 04:59:05 PM PDT 24 37320702 ps
T165 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1630793426 Jul 24 04:58:52 PM PDT 24 Jul 24 04:58:53 PM PDT 24 24188244 ps
T884 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1347508811 Jul 24 04:58:57 PM PDT 24 Jul 24 04:59:00 PM PDT 24 55262719 ps
T179 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1712825793 Jul 24 04:58:57 PM PDT 24 Jul 24 04:58:58 PM PDT 24 13965765 ps
T885 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2226965468 Jul 24 04:59:05 PM PDT 24 Jul 24 04:59:07 PM PDT 24 60650891 ps
T886 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3274512838 Jul 24 04:59:04 PM PDT 24 Jul 24 04:59:06 PM PDT 24 854935539 ps
T887 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3700893362 Jul 24 04:58:57 PM PDT 24 Jul 24 04:58:58 PM PDT 24 68960990 ps
T888 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1844735271 Jul 24 04:58:46 PM PDT 24 Jul 24 04:58:59 PM PDT 24 2318191567 ps
T889 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1054019698 Jul 24 04:58:54 PM PDT 24 Jul 24 04:58:56 PM PDT 24 304528908 ps
T890 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2275647799 Jul 24 04:59:03 PM PDT 24 Jul 24 04:59:06 PM PDT 24 530776447 ps
T115 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.7543665 Jul 24 04:58:55 PM PDT 24 Jul 24 04:58:59 PM PDT 24 116796611 ps
T180 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1335883257 Jul 24 04:58:57 PM PDT 24 Jul 24 04:58:59 PM PDT 24 67048151 ps
T891 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.217702936 Jul 24 04:59:23 PM PDT 24 Jul 24 04:59:29 PM PDT 24 695080810 ps
T892 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4278400172 Jul 24 04:59:00 PM PDT 24 Jul 24 04:59:03 PM PDT 24 213743316 ps
T146 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3692350489 Jul 24 04:59:11 PM PDT 24 Jul 24 04:59:12 PM PDT 24 102156119 ps
T893 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1705027386 Jul 24 04:59:00 PM PDT 24 Jul 24 04:59:02 PM PDT 24 105261132 ps
T894 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3960901186 Jul 24 04:58:46 PM PDT 24 Jul 24 04:58:48 PM PDT 24 155664321 ps
T132 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1943438896 Jul 24 04:58:53 PM PDT 24 Jul 24 04:58:57 PM PDT 24 147148801 ps
T895 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3072123472 Jul 24 04:58:59 PM PDT 24 Jul 24 04:59:10 PM PDT 24 4115157442 ps
T896 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3616237782 Jul 24 04:59:01 PM PDT 24 Jul 24 04:59:03 PM PDT 24 18557242 ps
T897 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4011831892 Jul 24 04:58:59 PM PDT 24 Jul 24 04:59:01 PM PDT 24 41381976 ps
T166 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1778995906 Jul 24 04:59:28 PM PDT 24 Jul 24 04:59:29 PM PDT 24 31405502 ps
T898 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1261811208 Jul 24 04:59:05 PM PDT 24 Jul 24 04:59:07 PM PDT 24 94966605 ps
T899 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2351052315 Jul 24 04:59:02 PM PDT 24 Jul 24 04:59:05 PM PDT 24 111084332 ps
T181 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2734487677 Jul 24 04:59:06 PM PDT 24 Jul 24 04:59:08 PM PDT 24 90080224 ps
T900 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2462644264 Jul 24 04:59:32 PM PDT 24 Jul 24 04:59:34 PM PDT 24 35229501 ps
T901 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1606044849 Jul 24 04:59:06 PM PDT 24 Jul 24 04:59:08 PM PDT 24 69218514 ps
T182 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.709980491 Jul 24 04:58:59 PM PDT 24 Jul 24 04:59:01 PM PDT 24 127208346 ps
T902 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3083038079 Jul 24 04:59:02 PM PDT 24 Jul 24 04:59:04 PM PDT 24 24597520 ps
T903 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.4286174138 Jul 24 04:59:29 PM PDT 24 Jul 24 04:59:31 PM PDT 24 32280933 ps
T904 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.100794518 Jul 24 04:59:00 PM PDT 24 Jul 24 04:59:02 PM PDT 24 105255742 ps
T905 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3084959532 Jul 24 04:58:51 PM PDT 24 Jul 24 04:58:59 PM PDT 24 12034293983 ps
T906 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3006093011 Jul 24 04:58:59 PM PDT 24 Jul 24 04:59:01 PM PDT 24 15751133 ps
T907 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.465743927 Jul 24 04:59:28 PM PDT 24 Jul 24 04:59:33 PM PDT 24 122964415 ps
T908 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1235229433 Jul 24 04:59:00 PM PDT 24 Jul 24 04:59:03 PM PDT 24 671547345 ps
T909 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3955730242 Jul 24 04:59:03 PM PDT 24 Jul 24 04:59:05 PM PDT 24 92470661 ps
T910 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.279854848 Jul 24 04:59:00 PM PDT 24 Jul 24 04:59:02 PM PDT 24 34732611 ps
T911 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.486294981 Jul 24 04:59:26 PM PDT 24 Jul 24 04:59:28 PM PDT 24 106955064 ps
T912 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.643995479 Jul 24 04:59:06 PM PDT 24 Jul 24 04:59:08 PM PDT 24 38071369 ps
T913 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3094669443 Jul 24 04:59:29 PM PDT 24 Jul 24 04:59:31 PM PDT 24 79106416 ps
T914 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1731515018 Jul 24 04:59:05 PM PDT 24 Jul 24 04:59:09 PM PDT 24 403436185 ps
T915 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2129821255 Jul 24 04:59:02 PM PDT 24 Jul 24 04:59:08 PM PDT 24 370734267 ps
T916 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1959171588 Jul 24 04:58:58 PM PDT 24 Jul 24 04:58:59 PM PDT 24 19208031 ps
T129 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3348593475 Jul 24 04:59:23 PM PDT 24 Jul 24 04:59:25 PM PDT 24 289468846 ps
T917 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3575215961 Jul 24 04:58:47 PM PDT 24 Jul 24 04:58:49 PM PDT 24 39455568 ps
T918 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1342875357 Jul 24 04:59:06 PM PDT 24 Jul 24 04:59:09 PM PDT 24 51086979 ps
T919 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3083583630 Jul 24 04:58:46 PM PDT 24 Jul 24 04:58:48 PM PDT 24 292702885 ps
T920 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4039023980 Jul 24 04:59:01 PM PDT 24 Jul 24 04:59:02 PM PDT 24 306448982 ps
T921 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2702513245 Jul 24 04:59:03 PM PDT 24 Jul 24 04:59:05 PM PDT 24 666524916 ps
T922 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.141351899 Jul 24 04:59:02 PM PDT 24 Jul 24 04:59:04 PM PDT 24 35150453 ps
T923 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1246119489 Jul 24 04:59:20 PM PDT 24 Jul 24 04:59:21 PM PDT 24 60093719 ps
T924 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2029539424 Jul 24 04:58:53 PM PDT 24 Jul 24 04:58:57 PM PDT 24 3669901878 ps
T925 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.99163481 Jul 24 04:58:55 PM PDT 24 Jul 24 04:59:12 PM PDT 24 2896945609 ps
T926 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1974245554 Jul 24 04:58:56 PM PDT 24 Jul 24 04:58:59 PM PDT 24 138950122 ps
T927 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3078596602 Jul 24 04:59:05 PM PDT 24 Jul 24 04:59:06 PM PDT 24 37234952 ps
T928 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1119123842 Jul 24 04:58:52 PM PDT 24 Jul 24 04:58:54 PM PDT 24 26081301 ps
T929 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2987506304 Jul 24 04:58:52 PM PDT 24 Jul 24 04:58:53 PM PDT 24 45369628 ps
T930 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.181689965 Jul 24 04:59:13 PM PDT 24 Jul 24 04:59:14 PM PDT 24 17729466 ps
T121 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1119125982 Jul 24 04:59:20 PM PDT 24 Jul 24 04:59:22 PM PDT 24 55803873 ps
T931 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1642011570 Jul 24 04:59:28 PM PDT 24 Jul 24 04:59:30 PM PDT 24 43562330 ps
T133 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.55494895 Jul 24 04:59:18 PM PDT 24 Jul 24 04:59:20 PM PDT 24 45666268 ps
T932 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2792729576 Jul 24 04:59:02 PM PDT 24 Jul 24 04:59:05 PM PDT 24 91979133 ps
T122 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1386215731 Jul 24 04:59:26 PM PDT 24 Jul 24 04:59:29 PM PDT 24 443131620 ps
T933 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1934099617 Jul 24 04:58:46 PM PDT 24 Jul 24 04:58:48 PM PDT 24 100801101 ps
T131 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2740389006 Jul 24 04:59:24 PM PDT 24 Jul 24 04:59:27 PM PDT 24 103974881 ps
T934 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3724103408 Jul 24 04:58:51 PM PDT 24 Jul 24 04:58:53 PM PDT 24 62644063 ps
T935 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2577183991 Jul 24 04:58:47 PM PDT 24 Jul 24 04:58:49 PM PDT 24 111429804 ps
T167 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2325839016 Jul 24 04:59:07 PM PDT 24 Jul 24 04:59:08 PM PDT 24 48076258 ps
T936 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1157214384 Jul 24 04:59:09 PM PDT 24 Jul 24 04:59:11 PM PDT 24 27128172 ps
T937 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.679074065 Jul 24 04:59:02 PM PDT 24 Jul 24 04:59:32 PM PDT 24 1527569968 ps
T168 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.694155774 Jul 24 04:58:51 PM PDT 24 Jul 24 04:58:52 PM PDT 24 19823951 ps
T938 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3439812456 Jul 24 04:58:56 PM PDT 24 Jul 24 04:58:57 PM PDT 24 184807450 ps
T939 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3757003759 Jul 24 04:59:05 PM PDT 24 Jul 24 04:59:06 PM PDT 24 54856497 ps
T940 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.83756414 Jul 24 04:58:52 PM PDT 24 Jul 24 04:58:57 PM PDT 24 516978128 ps
T941 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.995113916 Jul 24 04:58:57 PM PDT 24 Jul 24 04:58:58 PM PDT 24 43279108 ps
T169 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1542328684 Jul 24 04:59:08 PM PDT 24 Jul 24 04:59:09 PM PDT 24 11218175 ps
T170 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2321677752 Jul 24 04:59:00 PM PDT 24 Jul 24 04:59:02 PM PDT 24 29886067 ps
T942 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2226261426 Jul 24 04:59:03 PM PDT 24 Jul 24 04:59:05 PM PDT 24 355544443 ps
T943 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2847495334 Jul 24 04:59:04 PM PDT 24 Jul 24 04:59:05 PM PDT 24 20876663 ps
T944 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1992283752 Jul 24 04:59:04 PM PDT 24 Jul 24 04:59:06 PM PDT 24 51424362 ps
T123 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.732055001 Jul 24 04:59:06 PM PDT 24 Jul 24 04:59:10 PM PDT 24 116195719 ps
T945 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.4264539444 Jul 24 04:58:46 PM PDT 24 Jul 24 04:58:48 PM PDT 24 143679324 ps
T946 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2965272242 Jul 24 04:58:47 PM PDT 24 Jul 24 04:58:49 PM PDT 24 103282646 ps
T947 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3777337580 Jul 24 04:59:12 PM PDT 24 Jul 24 04:59:14 PM PDT 24 30834776 ps
T117 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1584577959 Jul 24 04:59:06 PM PDT 24 Jul 24 04:59:09 PM PDT 24 52480561 ps
T948 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3297252581 Jul 24 04:59:15 PM PDT 24 Jul 24 04:59:16 PM PDT 24 22211198 ps
T949 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2674028831 Jul 24 04:59:01 PM PDT 24 Jul 24 04:59:04 PM PDT 24 102273673 ps
T950 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.590551195 Jul 24 04:58:51 PM PDT 24 Jul 24 04:59:06 PM PDT 24 1514470957 ps
T951 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1112832093 Jul 24 04:59:35 PM PDT 24 Jul 24 04:59:38 PM PDT 24 159768813 ps
T952 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.402268559 Jul 24 04:58:55 PM PDT 24 Jul 24 04:59:10 PM PDT 24 658471589 ps
T953 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.4125877583 Jul 24 04:58:53 PM PDT 24 Jul 24 04:58:54 PM PDT 24 34332306 ps
T954 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2400642288 Jul 24 04:59:01 PM PDT 24 Jul 24 04:59:07 PM PDT 24 2506317296 ps
T955 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2715237675 Jul 24 04:59:06 PM PDT 24 Jul 24 04:59:16 PM PDT 24 1641954171 ps
T956 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2877674360 Jul 24 04:59:02 PM PDT 24 Jul 24 04:59:05 PM PDT 24 106160153 ps
T957 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1365247170 Jul 24 04:58:58 PM PDT 24 Jul 24 04:59:00 PM PDT 24 154114135 ps
T958 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.4258123965 Jul 24 04:59:02 PM PDT 24 Jul 24 04:59:04 PM PDT 24 67483755 ps
T959 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.940478193 Jul 24 04:58:57 PM PDT 24 Jul 24 04:58:59 PM PDT 24 49540774 ps
T960 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2778263326 Jul 24 04:58:47 PM PDT 24 Jul 24 04:58:50 PM PDT 24 159300463 ps
T961 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1202380415 Jul 24 04:59:11 PM PDT 24 Jul 24 04:59:13 PM PDT 24 38138954 ps
T962 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3511416558 Jul 24 04:58:45 PM PDT 24 Jul 24 04:58:46 PM PDT 24 64890616 ps
T171 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1811526426 Jul 24 04:59:09 PM PDT 24 Jul 24 04:59:10 PM PDT 24 12064547 ps
T963 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2917056270 Jul 24 04:58:54 PM PDT 24 Jul 24 04:58:55 PM PDT 24 24449838 ps
T172 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3475058165 Jul 24 04:59:10 PM PDT 24 Jul 24 04:59:11 PM PDT 24 18946426 ps
T126 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3706318085 Jul 24 04:59:08 PM PDT 24 Jul 24 04:59:11 PM PDT 24 256437253 ps
T964 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2670822583 Jul 24 04:58:56 PM PDT 24 Jul 24 04:58:57 PM PDT 24 1099155317 ps
T965 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3031579683 Jul 24 04:59:26 PM PDT 24 Jul 24 04:59:28 PM PDT 24 145132167 ps
T966 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1023366745 Jul 24 04:59:26 PM PDT 24 Jul 24 04:59:27 PM PDT 24 37324108 ps
T967 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1817251981 Jul 24 04:59:22 PM PDT 24 Jul 24 04:59:23 PM PDT 24 138999900 ps
T968 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3045105874 Jul 24 04:59:07 PM PDT 24 Jul 24 04:59:08 PM PDT 24 47082410 ps
T969 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2448576018 Jul 24 04:58:55 PM PDT 24 Jul 24 04:58:57 PM PDT 24 480032662 ps
T970 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2354547252 Jul 24 04:59:03 PM PDT 24 Jul 24 04:59:04 PM PDT 24 25235177 ps
T971 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3363311703 Jul 24 04:59:05 PM PDT 24 Jul 24 04:59:08 PM PDT 24 151722955 ps
T972 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.236926884 Jul 24 04:58:58 PM PDT 24 Jul 24 04:59:00 PM PDT 24 169127215 ps
T973 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.4226737592 Jul 24 04:58:59 PM PDT 24 Jul 24 04:59:07 PM PDT 24 1321823605 ps
T173 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.294162485 Jul 24 04:59:05 PM PDT 24 Jul 24 04:59:06 PM PDT 24 16526696 ps
T974 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3613535087 Jul 24 04:59:19 PM PDT 24 Jul 24 04:59:26 PM PDT 24 17148345 ps
T975 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.39797218 Jul 24 04:59:02 PM PDT 24 Jul 24 04:59:03 PM PDT 24 116558908 ps
T124 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3508936801 Jul 24 04:59:01 PM PDT 24 Jul 24 04:59:04 PM PDT 24 1074560029 ps
T976 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.324916828 Jul 24 04:59:00 PM PDT 24 Jul 24 04:59:27 PM PDT 24 5082045135 ps
T977 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3324313913 Jul 24 04:58:56 PM PDT 24 Jul 24 04:58:58 PM PDT 24 79767815 ps
T978 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1937028106 Jul 24 04:59:00 PM PDT 24 Jul 24 04:59:01 PM PDT 24 30890632 ps
T979 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.721596064 Jul 24 04:58:47 PM PDT 24 Jul 24 04:58:49 PM PDT 24 221813469 ps
T980 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4107287805 Jul 24 04:59:02 PM PDT 24 Jul 24 04:59:04 PM PDT 24 38715551 ps
T981 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.349368018 Jul 24 04:58:58 PM PDT 24 Jul 24 04:59:00 PM PDT 24 36995234 ps
T982 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3254316928 Jul 24 04:59:00 PM PDT 24 Jul 24 04:59:09 PM PDT 24 6107280491 ps
T983 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.205927717 Jul 24 04:58:58 PM PDT 24 Jul 24 04:58:59 PM PDT 24 79226371 ps
T984 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.116644762 Jul 24 04:59:03 PM PDT 24 Jul 24 04:59:04 PM PDT 24 84574794 ps
T985 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3611683912 Jul 24 04:58:52 PM PDT 24 Jul 24 04:58:54 PM PDT 24 24872063 ps
T986 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2323670763 Jul 24 04:58:59 PM PDT 24 Jul 24 04:59:01 PM PDT 24 285632489 ps
T987 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2292610581 Jul 24 04:58:59 PM PDT 24 Jul 24 04:59:00 PM PDT 24 14853884 ps
T174 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3330139968 Jul 24 04:59:10 PM PDT 24 Jul 24 04:59:11 PM PDT 24 28631491 ps
T988 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2581929277 Jul 24 04:59:02 PM PDT 24 Jul 24 04:59:04 PM PDT 24 32109273 ps
T989 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4231926450 Jul 24 04:59:25 PM PDT 24 Jul 24 04:59:28 PM PDT 24 35936107 ps
T990 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3913317877 Jul 24 04:59:08 PM PDT 24 Jul 24 04:59:10 PM PDT 24 22926484 ps
T991 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.20675992 Jul 24 04:59:06 PM PDT 24 Jul 24 04:59:08 PM PDT 24 1042075131 ps
T127 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.51995599 Jul 24 04:59:23 PM PDT 24 Jul 24 04:59:26 PM PDT 24 73262413 ps
T992 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.198213133 Jul 24 04:58:58 PM PDT 24 Jul 24 04:58:59 PM PDT 24 20836467 ps
T993 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3204501958 Jul 24 04:58:59 PM PDT 24 Jul 24 04:59:03 PM PDT 24 40232123 ps
T116 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3748469076 Jul 24 04:59:05 PM PDT 24 Jul 24 04:59:08 PM PDT 24 465879438 ps
T994 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1641174079 Jul 24 04:59:07 PM PDT 24 Jul 24 04:59:09 PM PDT 24 26430869 ps
T995 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1585088938 Jul 24 04:59:22 PM PDT 24 Jul 24 04:59:23 PM PDT 24 18015736 ps
T996 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2198480012 Jul 24 04:59:10 PM PDT 24 Jul 24 04:59:11 PM PDT 24 27977020 ps
T118 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.436495416 Jul 24 04:59:01 PM PDT 24 Jul 24 04:59:04 PM PDT 24 63358040 ps
T997 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2822327756 Jul 24 04:59:06 PM PDT 24 Jul 24 04:59:09 PM PDT 24 126733703 ps
T998 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.4029571490 Jul 24 04:59:07 PM PDT 24 Jul 24 04:59:10 PM PDT 24 282020270 ps
T130 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3173080569 Jul 24 04:59:20 PM PDT 24 Jul 24 04:59:22 PM PDT 24 42693578 ps
T999 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3587857515 Jul 24 04:59:18 PM PDT 24 Jul 24 04:59:20 PM PDT 24 175882543 ps
T1000 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1222897617 Jul 24 04:59:22 PM PDT 24 Jul 24 04:59:34 PM PDT 24 665022129 ps

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2154167608
Short name T1
Test name
Test status
Simulation time 5007056096 ps
CPU time 14.47 seconds
Started Jul 24 06:57:15 PM PDT 24
Finished Jul 24 06:57:30 PM PDT 24
Peak memory 226188 kb
Host smart-d9486933-9921-46cf-923a-d2eebcde5ef9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154167608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2154167608
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.694125539
Short name T19
Test name
Test status
Simulation time 13553651119 ps
CPU time 322.35 seconds
Started Jul 24 06:58:12 PM PDT 24
Finished Jul 24 07:03:35 PM PDT 24
Peak memory 404980 kb
Host smart-86b371e8-c9ea-4107-936f-9f19e0a8c51a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=694125539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.694125539
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3556688436
Short name T62
Test name
Test status
Simulation time 324154389 ps
CPU time 8.69 seconds
Started Jul 24 06:59:59 PM PDT 24
Finished Jul 24 07:00:08 PM PDT 24
Peak memory 226176 kb
Host smart-aea90d9f-0e5b-4836-9311-21d4ec6d8bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556688436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3556688436
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.4062289640
Short name T16
Test name
Test status
Simulation time 3420211383 ps
CPU time 7.74 seconds
Started Jul 24 06:56:58 PM PDT 24
Finished Jul 24 06:57:06 PM PDT 24
Peak memory 226056 kb
Host smart-62f729b2-fe24-4291-8d49-1d6f933870b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062289640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.4
062289640
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.357813996
Short name T39
Test name
Test status
Simulation time 47178717 ps
CPU time 0.97 seconds
Started Jul 24 07:00:43 PM PDT 24
Finished Jul 24 07:00:44 PM PDT 24
Peak memory 209244 kb
Host smart-c00220a9-44aa-4231-aeec-06d4ca541582
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357813996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.357813996
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.364964012
Short name T64
Test name
Test status
Simulation time 1032645808 ps
CPU time 44.17 seconds
Started Jul 24 06:58:00 PM PDT 24
Finished Jul 24 06:58:44 PM PDT 24
Peak memory 270168 kb
Host smart-beff4775-1536-433a-b71c-a2891e0f7cfb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364964012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.364964012
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.2927418011
Short name T22
Test name
Test status
Simulation time 50782029105 ps
CPU time 391.05 seconds
Started Jul 24 06:58:52 PM PDT 24
Finished Jul 24 07:05:23 PM PDT 24
Peak memory 306288 kb
Host smart-6675cf7c-7360-41a7-a7cf-8022cd2e0aba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2927418011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.2927418011
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1120396195
Short name T107
Test name
Test status
Simulation time 112045387 ps
CPU time 3 seconds
Started Jul 24 04:59:29 PM PDT 24
Finished Jul 24 04:59:32 PM PDT 24
Peak memory 223280 kb
Host smart-ad98df1f-7992-414b-bbe1-dc7679f3a7ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120396195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1120396195
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3552244853
Short name T60
Test name
Test status
Simulation time 336310318 ps
CPU time 8.11 seconds
Started Jul 24 07:00:37 PM PDT 24
Finished Jul 24 07:00:45 PM PDT 24
Peak memory 218368 kb
Host smart-674b48f6-6b32-45db-b9d5-4f715b228fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552244853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3552244853
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.4134134080
Short name T139
Test name
Test status
Simulation time 18416638096 ps
CPU time 318.34 seconds
Started Jul 24 06:59:51 PM PDT 24
Finished Jul 24 07:05:09 PM PDT 24
Peak memory 235188 kb
Host smart-ceb4e53e-d0d2-430d-93bd-25260df5c4db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4134134080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.4134134080
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1322351570
Short name T10
Test name
Test status
Simulation time 510315659 ps
CPU time 3.62 seconds
Started Jul 24 07:01:28 PM PDT 24
Finished Jul 24 07:01:32 PM PDT 24
Peak memory 217764 kb
Host smart-9dc7f291-2ddf-4d9e-931b-416dbd994fd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322351570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1322351570
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2620163680
Short name T114
Test name
Test status
Simulation time 1508212042 ps
CPU time 3.31 seconds
Started Jul 24 04:58:46 PM PDT 24
Finished Jul 24 04:58:50 PM PDT 24
Peak memory 226384 kb
Host smart-7850546b-a70e-414c-959d-35c8435c2bca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262016
3680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2620163680
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.762966005
Short name T44
Test name
Test status
Simulation time 593292099 ps
CPU time 11.89 seconds
Started Jul 24 06:57:13 PM PDT 24
Finished Jul 24 06:57:25 PM PDT 24
Peak memory 226028 kb
Host smart-15d55d92-5329-4cbf-9828-d335158d2353
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762966005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.762966005
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3207966578
Short name T13
Test name
Test status
Simulation time 86827966 ps
CPU time 1.05 seconds
Started Jul 24 06:59:32 PM PDT 24
Finished Jul 24 06:59:33 PM PDT 24
Peak memory 209112 kb
Host smart-8aa70ec0-09c7-418f-bda5-3a5b69611c9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207966578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3207966578
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.694155774
Short name T168
Test name
Test status
Simulation time 19823951 ps
CPU time 1.08 seconds
Started Jul 24 04:58:51 PM PDT 24
Finished Jul 24 04:58:52 PM PDT 24
Peak memory 218648 kb
Host smart-72f45a4a-c82b-44cb-8d42-fd978684206f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694155774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.694155774
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1537655743
Short name T49
Test name
Test status
Simulation time 225591110 ps
CPU time 22.69 seconds
Started Jul 24 06:57:59 PM PDT 24
Finished Jul 24 06:58:22 PM PDT 24
Peak memory 246572 kb
Host smart-dd9c5331-cfc5-4705-a380-e46eecf085ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537655743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1537655743
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.7543665
Short name T115
Test name
Test status
Simulation time 116796611 ps
CPU time 4.06 seconds
Started Jul 24 04:58:55 PM PDT 24
Finished Jul 24 04:58:59 PM PDT 24
Peak memory 218112 kb
Host smart-bedac418-1978-4257-b249-952e69ca74fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7543665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_err.7543665
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.3152120228
Short name T229
Test name
Test status
Simulation time 9746503819 ps
CPU time 125.72 seconds
Started Jul 24 06:58:12 PM PDT 24
Finished Jul 24 07:00:18 PM PDT 24
Peak memory 282992 kb
Host smart-79f2eb83-88f2-42a7-b796-9708932c08d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152120228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.3152120228
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.465743927
Short name T907
Test name
Test status
Simulation time 122964415 ps
CPU time 4.57 seconds
Started Jul 24 04:59:28 PM PDT 24
Finished Jul 24 04:59:33 PM PDT 24
Peak memory 218212 kb
Host smart-5519ce8b-48fc-4361-85fa-000324116d84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465743927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.465743927
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.732055001
Short name T123
Test name
Test status
Simulation time 116195719 ps
CPU time 4.34 seconds
Started Jul 24 04:59:06 PM PDT 24
Finished Jul 24 04:59:10 PM PDT 24
Peak memory 218132 kb
Host smart-12116778-4f38-4440-8d9d-58a743586a63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732055001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.732055001
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.866176545
Short name T192
Test name
Test status
Simulation time 1107723595 ps
CPU time 7.58 seconds
Started Jul 24 06:58:18 PM PDT 24
Finished Jul 24 06:58:26 PM PDT 24
Peak memory 224828 kb
Host smart-076ef13f-14cd-44d8-8cae-39e78c1a1a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866176545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.866176545
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2313849889
Short name T103
Test name
Test status
Simulation time 13336004776 ps
CPU time 211.18 seconds
Started Jul 24 06:57:41 PM PDT 24
Finished Jul 24 07:01:12 PM PDT 24
Peak memory 300184 kb
Host smart-fe1edabb-8e68-404b-8787-b3ccdf4ec3ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313849889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2313849889
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1529045315
Short name T3
Test name
Test status
Simulation time 743912366 ps
CPU time 13.32 seconds
Started Jul 24 06:57:59 PM PDT 24
Finished Jul 24 06:58:13 PM PDT 24
Peak memory 217776 kb
Host smart-7500f078-dcef-43b0-9259-4b7dac402330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529045315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1529045315
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1119125982
Short name T121
Test name
Test status
Simulation time 55803873 ps
CPU time 2.58 seconds
Started Jul 24 04:59:20 PM PDT 24
Finished Jul 24 04:59:22 PM PDT 24
Peak memory 218200 kb
Host smart-9a09608c-b30e-4d55-b8e2-9bc903ba91f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119125982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1119125982
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1712825793
Short name T179
Test name
Test status
Simulation time 13965765 ps
CPU time 0.99 seconds
Started Jul 24 04:58:57 PM PDT 24
Finished Jul 24 04:58:58 PM PDT 24
Peak memory 209932 kb
Host smart-cedb72b5-d641-44b2-96a2-09b46d4c6a5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712825793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.1712825793
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.681133649
Short name T128
Test name
Test status
Simulation time 835855397 ps
CPU time 3.51 seconds
Started Jul 24 04:58:47 PM PDT 24
Finished Jul 24 04:58:51 PM PDT 24
Peak memory 218080 kb
Host smart-974961eb-7593-438a-831a-c5855db74a90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681133649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.681133649
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3173080569
Short name T130
Test name
Test status
Simulation time 42693578 ps
CPU time 2.19 seconds
Started Jul 24 04:59:20 PM PDT 24
Finished Jul 24 04:59:22 PM PDT 24
Peak memory 218252 kb
Host smart-7c50bd53-af9d-476a-9d14-098855e3c55d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173080569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3173080569
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.541866130
Short name T185
Test name
Test status
Simulation time 34626057 ps
CPU time 0.89 seconds
Started Jul 24 06:56:59 PM PDT 24
Finished Jul 24 06:57:00 PM PDT 24
Peak memory 208848 kb
Host smart-0b9b1485-ba70-44ff-b436-6ec068d9e0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541866130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.541866130
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1429957139
Short name T187
Test name
Test status
Simulation time 13216244 ps
CPU time 0.99 seconds
Started Jul 24 06:57:26 PM PDT 24
Finished Jul 24 06:57:27 PM PDT 24
Peak memory 208888 kb
Host smart-d2c89887-851d-4773-950b-cba6f6535c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429957139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1429957139
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2874967719
Short name T189
Test name
Test status
Simulation time 31588599 ps
CPU time 0.78 seconds
Started Jul 24 06:57:46 PM PDT 24
Finished Jul 24 06:57:47 PM PDT 24
Peak memory 209076 kb
Host smart-3d57815c-3c5b-448a-99f8-d094bb820703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874967719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2874967719
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2637192506
Short name T190
Test name
Test status
Simulation time 10318988 ps
CPU time 0.86 seconds
Started Jul 24 06:58:01 PM PDT 24
Finished Jul 24 06:58:02 PM PDT 24
Peak memory 208700 kb
Host smart-b5edf5af-5eb9-4e2e-b6eb-4b4fcd20d5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637192506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2637192506
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3026434798
Short name T191
Test name
Test status
Simulation time 28944345 ps
CPU time 0.8 seconds
Started Jul 24 06:58:12 PM PDT 24
Finished Jul 24 06:58:13 PM PDT 24
Peak memory 209060 kb
Host smart-8727b8f6-ca49-43ae-9962-78bddf69135d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026434798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3026434798
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1386215731
Short name T122
Test name
Test status
Simulation time 443131620 ps
CPU time 3.14 seconds
Started Jul 24 04:59:26 PM PDT 24
Finished Jul 24 04:59:29 PM PDT 24
Peak memory 223100 kb
Host smart-7095d367-e1aa-4095-83ae-ff2baa787092
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386215731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1386215731
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3706318085
Short name T126
Test name
Test status
Simulation time 256437253 ps
CPU time 2.5 seconds
Started Jul 24 04:59:08 PM PDT 24
Finished Jul 24 04:59:11 PM PDT 24
Peak memory 222168 kb
Host smart-e59abc7b-e4f7-466e-b223-3e2a52f662d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706318085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3706318085
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3748469076
Short name T116
Test name
Test status
Simulation time 465879438 ps
CPU time 2.58 seconds
Started Jul 24 04:59:05 PM PDT 24
Finished Jul 24 04:59:08 PM PDT 24
Peak memory 222864 kb
Host smart-af77b4dd-da9f-42bb-98f8-b2e9e0ff775b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748469076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3748469076
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2052401493
Short name T58
Test name
Test status
Simulation time 11448455308 ps
CPU time 28.07 seconds
Started Jul 24 06:59:32 PM PDT 24
Finished Jul 24 07:00:00 PM PDT 24
Peak memory 218592 kb
Host smart-371d3a0e-5fe4-490e-a73a-de14de1b1393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052401493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2052401493
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2721737219
Short name T5
Test name
Test status
Simulation time 5717759072 ps
CPU time 82.63 seconds
Started Jul 24 07:01:11 PM PDT 24
Finished Jul 24 07:02:34 PM PDT 24
Peak memory 226072 kb
Host smart-c050bab4-c26e-47ca-88b6-52ea967931de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721737219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2721737219
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3083583630
Short name T919
Test name
Test status
Simulation time 292702885 ps
CPU time 1.48 seconds
Started Jul 24 04:58:46 PM PDT 24
Finished Jul 24 04:58:48 PM PDT 24
Peak memory 210028 kb
Host smart-2d7f5ef5-5839-4aa6-a142-7851e28b35bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083583630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3083583630
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.4264539444
Short name T945
Test name
Test status
Simulation time 143679324 ps
CPU time 1.76 seconds
Started Jul 24 04:58:46 PM PDT 24
Finished Jul 24 04:58:48 PM PDT 24
Peak memory 208976 kb
Host smart-4319aac0-e34f-4816-a8e9-ad6358d2ab5f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264539444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.4264539444
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1937028106
Short name T978
Test name
Test status
Simulation time 30890632 ps
CPU time 0.99 seconds
Started Jul 24 04:59:00 PM PDT 24
Finished Jul 24 04:59:01 PM PDT 24
Peak memory 210580 kb
Host smart-8dcf8d76-5f94-4857-8e6f-b50d0bb81a02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937028106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1937028106
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2965272242
Short name T946
Test name
Test status
Simulation time 103282646 ps
CPU time 1.8 seconds
Started Jul 24 04:58:47 PM PDT 24
Finished Jul 24 04:58:49 PM PDT 24
Peak memory 224608 kb
Host smart-2b58dfcd-411d-4ad1-a656-a49ae894fadd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965272242 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2965272242
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3324313913
Short name T977
Test name
Test status
Simulation time 79767815 ps
CPU time 1.31 seconds
Started Jul 24 04:58:56 PM PDT 24
Finished Jul 24 04:58:58 PM PDT 24
Peak memory 209984 kb
Host smart-825ce640-0e4f-40fc-8c18-335c0122ee08
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324313913 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3324313913
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.100422290
Short name T872
Test name
Test status
Simulation time 555183393 ps
CPU time 3.2 seconds
Started Jul 24 04:58:58 PM PDT 24
Finished Jul 24 04:59:02 PM PDT 24
Peak memory 209284 kb
Host smart-093888dc-db78-4a8b-a084-9290a0093d82
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100422290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.100422290
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.590551195
Short name T950
Test name
Test status
Simulation time 1514470957 ps
CPU time 14.58 seconds
Started Jul 24 04:58:51 PM PDT 24
Finished Jul 24 04:59:06 PM PDT 24
Peak memory 209740 kb
Host smart-1de84482-06f4-489c-b6af-efed4c4fbace
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590551195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.590551195
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2778263326
Short name T960
Test name
Test status
Simulation time 159300463 ps
CPU time 2.69 seconds
Started Jul 24 04:58:47 PM PDT 24
Finished Jul 24 04:58:50 PM PDT 24
Peak memory 211812 kb
Host smart-0a0ca754-4ccc-4c46-b4df-1ee0a9975672
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778263326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2778263326
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3960901186
Short name T894
Test name
Test status
Simulation time 155664321 ps
CPU time 1.63 seconds
Started Jul 24 04:58:46 PM PDT 24
Finished Jul 24 04:58:48 PM PDT 24
Peak memory 209984 kb
Host smart-a66cdb17-a5ec-4329-9f41-d7614330a439
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960901186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3960901186
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2577183991
Short name T935
Test name
Test status
Simulation time 111429804 ps
CPU time 1.28 seconds
Started Jul 24 04:58:47 PM PDT 24
Finished Jul 24 04:58:49 PM PDT 24
Peak memory 209872 kb
Host smart-370ad3c4-6cd3-4377-86c1-24bd0620d0b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577183991 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2577183991
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3511416558
Short name T962
Test name
Test status
Simulation time 64890616 ps
CPU time 1.08 seconds
Started Jul 24 04:58:45 PM PDT 24
Finished Jul 24 04:58:46 PM PDT 24
Peak memory 210080 kb
Host smart-015c510f-0fba-4aba-8b06-61ba1d820175
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511416558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3511416558
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1934099617
Short name T933
Test name
Test status
Simulation time 100801101 ps
CPU time 1.77 seconds
Started Jul 24 04:58:46 PM PDT 24
Finished Jul 24 04:58:48 PM PDT 24
Peak memory 219140 kb
Host smart-ee177c3d-29be-4284-888c-6dd551b180d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934099617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1934099617
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.757952962
Short name T113
Test name
Test status
Simulation time 32297844 ps
CPU time 1.65 seconds
Started Jul 24 04:58:51 PM PDT 24
Finished Jul 24 04:58:53 PM PDT 24
Peak memory 209956 kb
Host smart-f51a4534-f21b-403a-a958-3c0e94a0557c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757952962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.757952962
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3575215961
Short name T917
Test name
Test status
Simulation time 39455568 ps
CPU time 1.31 seconds
Started Jul 24 04:58:47 PM PDT 24
Finished Jul 24 04:58:49 PM PDT 24
Peak memory 208548 kb
Host smart-c0c617aa-38a3-42ae-b592-8803384757f2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575215961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3575215961
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2581929277
Short name T988
Test name
Test status
Simulation time 32109273 ps
CPU time 1.67 seconds
Started Jul 24 04:59:02 PM PDT 24
Finished Jul 24 04:59:04 PM PDT 24
Peak memory 218316 kb
Host smart-790635fa-41ce-4e0a-a806-20e31b3cecdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581929277 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2581929277
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2987506304
Short name T929
Test name
Test status
Simulation time 45369628 ps
CPU time 0.82 seconds
Started Jul 24 04:58:52 PM PDT 24
Finished Jul 24 04:58:53 PM PDT 24
Peak memory 209864 kb
Host smart-5a58d3ce-2e9e-48d7-a519-71891f7d3c53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987506304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2987506304
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1165222212
Short name T882
Test name
Test status
Simulation time 63721937 ps
CPU time 1.47 seconds
Started Jul 24 04:58:59 PM PDT 24
Finished Jul 24 04:59:01 PM PDT 24
Peak memory 209840 kb
Host smart-b219737f-c5d0-46aa-9beb-dd6c12b60eef
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165222212 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1165222212
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1844735271
Short name T888
Test name
Test status
Simulation time 2318191567 ps
CPU time 12.44 seconds
Started Jul 24 04:58:46 PM PDT 24
Finished Jul 24 04:58:59 PM PDT 24
Peak memory 209964 kb
Host smart-33b90947-ebb3-488d-9d02-d6be2030205e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844735271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1844735271
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3084959532
Short name T905
Test name
Test status
Simulation time 12034293983 ps
CPU time 7.02 seconds
Started Jul 24 04:58:51 PM PDT 24
Finished Jul 24 04:58:59 PM PDT 24
Peak memory 209928 kb
Host smart-84084f3c-a556-4126-8e8d-6a92c0b122fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084959532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3084959532
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.721596064
Short name T979
Test name
Test status
Simulation time 221813469 ps
CPU time 2.01 seconds
Started Jul 24 04:58:47 PM PDT 24
Finished Jul 24 04:58:49 PM PDT 24
Peak memory 211668 kb
Host smart-6589d8ba-173a-4111-a2bc-f35b22c505a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721596064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.721596064
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.83756414
Short name T940
Test name
Test status
Simulation time 516978128 ps
CPU time 4.4 seconds
Started Jul 24 04:58:52 PM PDT 24
Finished Jul 24 04:58:57 PM PDT 24
Peak memory 219228 kb
Host smart-f9565a61-3f49-465f-95fa-3821f0058fb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837564
14 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.83756414
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2087408985
Short name T879
Test name
Test status
Simulation time 244723072 ps
CPU time 2.1 seconds
Started Jul 24 04:58:56 PM PDT 24
Finished Jul 24 04:58:59 PM PDT 24
Peak memory 209932 kb
Host smart-85501474-a400-4ce2-a4fa-94685a5fed3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087408985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2087408985
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.709980491
Short name T182
Test name
Test status
Simulation time 127208346 ps
CPU time 1.34 seconds
Started Jul 24 04:58:59 PM PDT 24
Finished Jul 24 04:59:01 PM PDT 24
Peak memory 209916 kb
Host smart-33ecfe00-3914-4b6d-9d08-b8d0dedcd4e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709980491 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.709980491
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.995113916
Short name T941
Test name
Test status
Simulation time 43279108 ps
CPU time 0.98 seconds
Started Jul 24 04:58:57 PM PDT 24
Finished Jul 24 04:58:58 PM PDT 24
Peak memory 218064 kb
Host smart-ad98e6a1-0dd0-4139-b9d2-0ccf3c41eee3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995113916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.995113916
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2494516616
Short name T108
Test name
Test status
Simulation time 101404332 ps
CPU time 2.71 seconds
Started Jul 24 04:58:56 PM PDT 24
Finished Jul 24 04:58:59 PM PDT 24
Peak memory 218180 kb
Host smart-5315a4f0-0ca9-42ea-ad6e-e7f029ab6368
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494516616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2494516616
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3724103408
Short name T934
Test name
Test status
Simulation time 62644063 ps
CPU time 2.05 seconds
Started Jul 24 04:58:51 PM PDT 24
Finished Jul 24 04:58:53 PM PDT 24
Peak memory 218132 kb
Host smart-a8442fce-efe1-4e7f-8ee4-dd2354774c19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724103408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3724103408
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.158571896
Short name T110
Test name
Test status
Simulation time 22106955 ps
CPU time 1.36 seconds
Started Jul 24 04:59:08 PM PDT 24
Finished Jul 24 04:59:09 PM PDT 24
Peak memory 219648 kb
Host smart-62e5797a-d4b0-4ea5-a699-6886258e7975
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158571896 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.158571896
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2325839016
Short name T167
Test name
Test status
Simulation time 48076258 ps
CPU time 1.04 seconds
Started Jul 24 04:59:07 PM PDT 24
Finished Jul 24 04:59:08 PM PDT 24
Peak memory 209900 kb
Host smart-7c56fcb4-fade-4539-afb5-7c169afdd5d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325839016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2325839016
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1246119489
Short name T923
Test name
Test status
Simulation time 60093719 ps
CPU time 1.18 seconds
Started Jul 24 04:59:20 PM PDT 24
Finished Jul 24 04:59:21 PM PDT 24
Peak memory 210076 kb
Host smart-a15c3c05-3d5e-4fee-96b9-60aca567bdca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246119489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.1246119489
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.4029571490
Short name T998
Test name
Test status
Simulation time 282020270 ps
CPU time 2.99 seconds
Started Jul 24 04:59:07 PM PDT 24
Finished Jul 24 04:59:10 PM PDT 24
Peak memory 218120 kb
Host smart-a65f05de-1a1b-4109-91a7-382b0db94642
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029571490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.4029571490
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1606044849
Short name T901
Test name
Test status
Simulation time 69218514 ps
CPU time 0.98 seconds
Started Jul 24 04:59:06 PM PDT 24
Finished Jul 24 04:59:08 PM PDT 24
Peak memory 220356 kb
Host smart-40bc2b84-d78c-48de-b4cb-897ccb0d3cf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606044849 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1606044849
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2226965468
Short name T885
Test name
Test status
Simulation time 60650891 ps
CPU time 0.92 seconds
Started Jul 24 04:59:05 PM PDT 24
Finished Jul 24 04:59:07 PM PDT 24
Peak memory 210032 kb
Host smart-b99d9c68-5f86-455a-b008-af358c52ea3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226965468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2226965468
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2198480012
Short name T996
Test name
Test status
Simulation time 27977020 ps
CPU time 1.05 seconds
Started Jul 24 04:59:10 PM PDT 24
Finished Jul 24 04:59:11 PM PDT 24
Peak memory 209996 kb
Host smart-cc3134d1-d621-4c02-b025-1491d8617dd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198480012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2198480012
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3613535087
Short name T974
Test name
Test status
Simulation time 17148345 ps
CPU time 1.31 seconds
Started Jul 24 04:59:19 PM PDT 24
Finished Jul 24 04:59:26 PM PDT 24
Peak memory 219320 kb
Host smart-e98eae0b-07d4-4c56-a725-31e74f590f7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613535087 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3613535087
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1778995906
Short name T166
Test name
Test status
Simulation time 31405502 ps
CPU time 0.86 seconds
Started Jul 24 04:59:28 PM PDT 24
Finished Jul 24 04:59:29 PM PDT 24
Peak memory 209820 kb
Host smart-cc23b1ff-231d-41c6-80c2-da06bf83bef4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778995906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1778995906
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.643995479
Short name T912
Test name
Test status
Simulation time 38071369 ps
CPU time 1.32 seconds
Started Jul 24 04:59:06 PM PDT 24
Finished Jul 24 04:59:08 PM PDT 24
Peak memory 210076 kb
Host smart-3e2eb1d6-c51a-4ade-a682-c4fa82e3d70a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643995479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.643995479
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4231926450
Short name T989
Test name
Test status
Simulation time 35936107 ps
CPU time 2.47 seconds
Started Jul 24 04:59:25 PM PDT 24
Finished Jul 24 04:59:28 PM PDT 24
Peak memory 219264 kb
Host smart-ee6ba2f3-d6e5-4b59-8ec9-2d4ca7573322
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231926450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.4231926450
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.494980551
Short name T105
Test name
Test status
Simulation time 212570990 ps
CPU time 1.85 seconds
Started Jul 24 04:59:21 PM PDT 24
Finished Jul 24 04:59:23 PM PDT 24
Peak memory 213608 kb
Host smart-3162d59f-c902-4c16-ac64-b2136fb93ead
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494980551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.494980551
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1023366745
Short name T966
Test name
Test status
Simulation time 37324108 ps
CPU time 1.33 seconds
Started Jul 24 04:59:26 PM PDT 24
Finished Jul 24 04:59:27 PM PDT 24
Peak memory 218400 kb
Host smart-2a3f4961-492f-4b98-a313-a1554b6d0c00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023366745 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1023366745
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1811526426
Short name T171
Test name
Test status
Simulation time 12064547 ps
CPU time 1.05 seconds
Started Jul 24 04:59:09 PM PDT 24
Finished Jul 24 04:59:10 PM PDT 24
Peak memory 209668 kb
Host smart-71b0e790-ce1c-4880-bc12-33e92699242c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811526426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1811526426
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1157214384
Short name T936
Test name
Test status
Simulation time 27128172 ps
CPU time 1.09 seconds
Started Jul 24 04:59:09 PM PDT 24
Finished Jul 24 04:59:11 PM PDT 24
Peak memory 209936 kb
Host smart-15c863e5-6d2b-4f29-a1c8-6481d8254764
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157214384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1157214384
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.4141443566
Short name T106
Test name
Test status
Simulation time 439772964 ps
CPU time 3.12 seconds
Started Jul 24 04:59:19 PM PDT 24
Finished Jul 24 04:59:23 PM PDT 24
Peak memory 218208 kb
Host smart-08643609-cc13-45a7-b6ac-70aa0e84a8a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141443566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.4141443566
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3348593475
Short name T129
Test name
Test status
Simulation time 289468846 ps
CPU time 2.36 seconds
Started Jul 24 04:59:23 PM PDT 24
Finished Jul 24 04:59:25 PM PDT 24
Peak memory 218232 kb
Host smart-47147132-9fa6-4671-b6c6-c0397e665c83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348593475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3348593475
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3094669443
Short name T913
Test name
Test status
Simulation time 79106416 ps
CPU time 1.27 seconds
Started Jul 24 04:59:29 PM PDT 24
Finished Jul 24 04:59:31 PM PDT 24
Peak memory 218308 kb
Host smart-e8b00fa7-be66-4c0b-91f6-b79eb1fede1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094669443 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3094669443
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3045105874
Short name T968
Test name
Test status
Simulation time 47082410 ps
CPU time 0.86 seconds
Started Jul 24 04:59:07 PM PDT 24
Finished Jul 24 04:59:08 PM PDT 24
Peak memory 209268 kb
Host smart-43ec5b1a-6fec-4763-b981-9869b3610719
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045105874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3045105874
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.4176112856
Short name T176
Test name
Test status
Simulation time 112218384 ps
CPU time 1.13 seconds
Started Jul 24 04:59:13 PM PDT 24
Finished Jul 24 04:59:15 PM PDT 24
Peak memory 209920 kb
Host smart-29879432-3554-4b85-9f55-3e47be66c89a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176112856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.4176112856
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1677240245
Short name T120
Test name
Test status
Simulation time 599477520 ps
CPU time 2.61 seconds
Started Jul 24 04:59:07 PM PDT 24
Finished Jul 24 04:59:10 PM PDT 24
Peak memory 218188 kb
Host smart-ed9c8ed4-df3a-4aca-b49f-6649a3224bec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677240245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1677240245
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3309610971
Short name T112
Test name
Test status
Simulation time 17263091 ps
CPU time 1.13 seconds
Started Jul 24 04:59:17 PM PDT 24
Finished Jul 24 04:59:18 PM PDT 24
Peak memory 219312 kb
Host smart-8a6eff3f-dfe8-45e0-a24e-4133289689f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309610971 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3309610971
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3330139968
Short name T174
Test name
Test status
Simulation time 28631491 ps
CPU time 1.05 seconds
Started Jul 24 04:59:10 PM PDT 24
Finished Jul 24 04:59:11 PM PDT 24
Peak memory 210036 kb
Host smart-d2b99de1-f71b-4465-be60-a333cef78777
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330139968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3330139968
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3913317877
Short name T990
Test name
Test status
Simulation time 22926484 ps
CPU time 1.34 seconds
Started Jul 24 04:59:08 PM PDT 24
Finished Jul 24 04:59:10 PM PDT 24
Peak memory 209928 kb
Host smart-52932ff0-95ef-41d1-bc63-79ddba4e0126
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913317877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3913317877
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1112832093
Short name T951
Test name
Test status
Simulation time 159768813 ps
CPU time 2.87 seconds
Started Jul 24 04:59:35 PM PDT 24
Finished Jul 24 04:59:38 PM PDT 24
Peak memory 218248 kb
Host smart-11087b4b-d3c2-4fb6-9773-f6e8082e4f64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112832093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1112832093
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1584577959
Short name T117
Test name
Test status
Simulation time 52480561 ps
CPU time 2.43 seconds
Started Jul 24 04:59:06 PM PDT 24
Finished Jul 24 04:59:09 PM PDT 24
Peak memory 222032 kb
Host smart-4f970325-c0c4-4dcf-b7ce-cb7f67c28341
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584577959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1584577959
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3297252581
Short name T948
Test name
Test status
Simulation time 22211198 ps
CPU time 1.54 seconds
Started Jul 24 04:59:15 PM PDT 24
Finished Jul 24 04:59:16 PM PDT 24
Peak memory 219616 kb
Host smart-b9de5837-73af-47fd-83ff-484e9818c813
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297252581 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3297252581
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.294162485
Short name T173
Test name
Test status
Simulation time 16526696 ps
CPU time 0.82 seconds
Started Jul 24 04:59:05 PM PDT 24
Finished Jul 24 04:59:06 PM PDT 24
Peak memory 209744 kb
Host smart-818d6af5-7f41-4ebf-bb7c-e4199771752b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294162485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.294162485
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3692350489
Short name T146
Test name
Test status
Simulation time 102156119 ps
CPU time 1.03 seconds
Started Jul 24 04:59:11 PM PDT 24
Finished Jul 24 04:59:12 PM PDT 24
Peak memory 209936 kb
Host smart-d4d041b9-0e4f-43e1-9a7b-f4eba6bd0af2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692350489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3692350489
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.555447637
Short name T125
Test name
Test status
Simulation time 87755725 ps
CPU time 1.98 seconds
Started Jul 24 04:59:19 PM PDT 24
Finished Jul 24 04:59:22 PM PDT 24
Peak memory 218256 kb
Host smart-5e1652c7-4b27-49ff-add9-014702f2b924
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555447637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.555447637
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1641174079
Short name T994
Test name
Test status
Simulation time 26430869 ps
CPU time 1.55 seconds
Started Jul 24 04:59:07 PM PDT 24
Finished Jul 24 04:59:09 PM PDT 24
Peak memory 218244 kb
Host smart-e23fe7b5-29bd-4886-bf00-8bd3aa1ab5a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641174079 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1641174079
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1542328684
Short name T169
Test name
Test status
Simulation time 11218175 ps
CPU time 0.83 seconds
Started Jul 24 04:59:08 PM PDT 24
Finished Jul 24 04:59:09 PM PDT 24
Peak memory 209924 kb
Host smart-264082f5-bc26-45f0-a06d-cff38a6fe6c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542328684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1542328684
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3031579683
Short name T965
Test name
Test status
Simulation time 145132167 ps
CPU time 1.74 seconds
Started Jul 24 04:59:26 PM PDT 24
Finished Jul 24 04:59:28 PM PDT 24
Peak memory 212072 kb
Host smart-c447e3d0-6617-4efc-8a66-acb3c2759423
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031579683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3031579683
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3162745495
Short name T145
Test name
Test status
Simulation time 91346284 ps
CPU time 3.4 seconds
Started Jul 24 04:59:06 PM PDT 24
Finished Jul 24 04:59:09 PM PDT 24
Peak memory 218076 kb
Host smart-b91d6ecd-3179-495e-bf93-6fbb7cd21913
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162745495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3162745495
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2321035902
Short name T144
Test name
Test status
Simulation time 32987473 ps
CPU time 1.68 seconds
Started Jul 24 04:59:17 PM PDT 24
Finished Jul 24 04:59:19 PM PDT 24
Peak memory 218216 kb
Host smart-8862a294-0e02-4a85-bcb0-a826376d2fe0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321035902 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2321035902
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1642011570
Short name T931
Test name
Test status
Simulation time 43562330 ps
CPU time 0.97 seconds
Started Jul 24 04:59:28 PM PDT 24
Finished Jul 24 04:59:30 PM PDT 24
Peak memory 210068 kb
Host smart-e4ce631f-34c1-4aba-bd94-9624f1258159
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642011570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1642011570
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3466268040
Short name T177
Test name
Test status
Simulation time 17827930 ps
CPU time 1.09 seconds
Started Jul 24 04:59:08 PM PDT 24
Finished Jul 24 04:59:10 PM PDT 24
Peak memory 209912 kb
Host smart-2ab0f6a6-2df0-47d5-bbc7-7b45b2b0c6c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466268040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3466268040
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3619162508
Short name T119
Test name
Test status
Simulation time 243727591 ps
CPU time 1.98 seconds
Started Jul 24 04:59:15 PM PDT 24
Finished Jul 24 04:59:17 PM PDT 24
Peak memory 218164 kb
Host smart-b193feb9-b12f-43eb-800a-0cd4f63a97f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619162508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3619162508
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.55494895
Short name T133
Test name
Test status
Simulation time 45666268 ps
CPU time 1.83 seconds
Started Jul 24 04:59:18 PM PDT 24
Finished Jul 24 04:59:20 PM PDT 24
Peak memory 222352 kb
Host smart-bb8de36f-5027-4ecb-bfa1-fa88a0b649a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55494895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_e
rr.55494895
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.4286174138
Short name T903
Test name
Test status
Simulation time 32280933 ps
CPU time 1.64 seconds
Started Jul 24 04:59:29 PM PDT 24
Finished Jul 24 04:59:31 PM PDT 24
Peak memory 224812 kb
Host smart-38ee9bb8-2bcd-4588-b7ff-83a3998e0d26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286174138 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.4286174138
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1585088938
Short name T995
Test name
Test status
Simulation time 18015736 ps
CPU time 0.88 seconds
Started Jul 24 04:59:22 PM PDT 24
Finished Jul 24 04:59:23 PM PDT 24
Peak memory 210044 kb
Host smart-8df4c274-9cb5-4996-96fc-0c4732963b26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585088938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1585088938
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3777337580
Short name T947
Test name
Test status
Simulation time 30834776 ps
CPU time 1.38 seconds
Started Jul 24 04:59:12 PM PDT 24
Finished Jul 24 04:59:14 PM PDT 24
Peak memory 209932 kb
Host smart-f998a90e-f456-4263-a532-1b67bb76da32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777337580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3777337580
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3587857515
Short name T999
Test name
Test status
Simulation time 175882543 ps
CPU time 1.65 seconds
Started Jul 24 04:59:18 PM PDT 24
Finished Jul 24 04:59:20 PM PDT 24
Peak memory 218256 kb
Host smart-d86fc64f-035c-45c9-b1bb-b3a7a1076505
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587857515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3587857515
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.51995599
Short name T127
Test name
Test status
Simulation time 73262413 ps
CPU time 3.4 seconds
Started Jul 24 04:59:23 PM PDT 24
Finished Jul 24 04:59:26 PM PDT 24
Peak memory 218168 kb
Host smart-ad2ecbdc-6c09-4636-b6cb-ba4de0094204
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51995599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_e
rr.51995599
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2321677752
Short name T170
Test name
Test status
Simulation time 29886067 ps
CPU time 1.37 seconds
Started Jul 24 04:59:00 PM PDT 24
Finished Jul 24 04:59:02 PM PDT 24
Peak memory 209856 kb
Host smart-110179e0-71c7-4e48-abc6-019390433587
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321677752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2321677752
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1959171588
Short name T916
Test name
Test status
Simulation time 19208031 ps
CPU time 1.16 seconds
Started Jul 24 04:58:58 PM PDT 24
Finished Jul 24 04:58:59 PM PDT 24
Peak memory 209784 kb
Host smart-c12b5d14-95ab-49ca-ba4f-6f7f89764360
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959171588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1959171588
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.278008516
Short name T873
Test name
Test status
Simulation time 59771609 ps
CPU time 1.01 seconds
Started Jul 24 04:58:57 PM PDT 24
Finished Jul 24 04:58:59 PM PDT 24
Peak memory 210444 kb
Host smart-3deeef03-9175-4227-bd27-6946b2b4c185
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278008516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.278008516
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1119123842
Short name T928
Test name
Test status
Simulation time 26081301 ps
CPU time 1.32 seconds
Started Jul 24 04:58:52 PM PDT 24
Finished Jul 24 04:58:54 PM PDT 24
Peak memory 222532 kb
Host smart-e9f97f88-09ce-4f74-b533-5f826210cd9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119123842 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1119123842
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2292610581
Short name T987
Test name
Test status
Simulation time 14853884 ps
CPU time 0.89 seconds
Started Jul 24 04:58:59 PM PDT 24
Finished Jul 24 04:59:00 PM PDT 24
Peak memory 209900 kb
Host smart-faa4cfcf-2aee-4515-8803-4d4bcaea5959
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292610581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2292610581
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3700893362
Short name T887
Test name
Test status
Simulation time 68960990 ps
CPU time 0.89 seconds
Started Jul 24 04:58:57 PM PDT 24
Finished Jul 24 04:58:58 PM PDT 24
Peak memory 208432 kb
Host smart-1d265ebd-7b36-4de7-b412-47ca9173ea28
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700893362 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3700893362
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.99163481
Short name T925
Test name
Test status
Simulation time 2896945609 ps
CPU time 16.87 seconds
Started Jul 24 04:58:55 PM PDT 24
Finished Jul 24 04:59:12 PM PDT 24
Peak memory 210084 kb
Host smart-a8a6b10e-71e2-4160-8b17-bb99cb5ab8f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99163481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.lc_ctrl_jtag_csr_aliasing.99163481
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2029539424
Short name T924
Test name
Test status
Simulation time 3669901878 ps
CPU time 4.42 seconds
Started Jul 24 04:58:53 PM PDT 24
Finished Jul 24 04:58:57 PM PDT 24
Peak memory 210084 kb
Host smart-57a5fc52-dafd-4a24-9993-d9e0211521a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029539424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2029539424
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1054019698
Short name T889
Test name
Test status
Simulation time 304528908 ps
CPU time 1.47 seconds
Started Jul 24 04:58:54 PM PDT 24
Finished Jul 24 04:58:56 PM PDT 24
Peak memory 211380 kb
Host smart-0895fd9c-2d1e-410f-82c0-fa36066c5420
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054019698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1054019698
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.940478193
Short name T959
Test name
Test status
Simulation time 49540774 ps
CPU time 2.05 seconds
Started Jul 24 04:58:57 PM PDT 24
Finished Jul 24 04:58:59 PM PDT 24
Peak memory 218484 kb
Host smart-8f8afbea-51af-40af-8198-193357e2152b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940478
193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.940478193
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1705027386
Short name T893
Test name
Test status
Simulation time 105261132 ps
CPU time 1.46 seconds
Started Jul 24 04:59:00 PM PDT 24
Finished Jul 24 04:59:02 PM PDT 24
Peak memory 210124 kb
Host smart-bbf0aece-97dc-48b0-a73f-df8200e0b98c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705027386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1705027386
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.141351899
Short name T922
Test name
Test status
Simulation time 35150453 ps
CPU time 1.19 seconds
Started Jul 24 04:59:02 PM PDT 24
Finished Jul 24 04:59:04 PM PDT 24
Peak memory 209992 kb
Host smart-d700aeaf-a4ac-425b-81ad-0b4bd04e74c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141351899 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.141351899
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1974245554
Short name T926
Test name
Test status
Simulation time 138950122 ps
CPU time 1.8 seconds
Started Jul 24 04:58:56 PM PDT 24
Finished Jul 24 04:58:59 PM PDT 24
Peak memory 209920 kb
Host smart-7212a93a-08b6-427f-ab03-78d4ddc75cf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974245554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1974245554
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2702513245
Short name T921
Test name
Test status
Simulation time 666524916 ps
CPU time 1.86 seconds
Started Jul 24 04:59:03 PM PDT 24
Finished Jul 24 04:59:05 PM PDT 24
Peak memory 218172 kb
Host smart-0be772e1-b7c1-4879-a91b-01b658bfdf1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702513245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2702513245
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1943438896
Short name T132
Test name
Test status
Simulation time 147148801 ps
CPU time 4.22 seconds
Started Jul 24 04:58:53 PM PDT 24
Finished Jul 24 04:58:57 PM PDT 24
Peak memory 218176 kb
Host smart-9fc6cf85-fbf9-4042-b28c-aad0ca18a7b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943438896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1943438896
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3083038079
Short name T902
Test name
Test status
Simulation time 24597520 ps
CPU time 1.36 seconds
Started Jul 24 04:59:02 PM PDT 24
Finished Jul 24 04:59:04 PM PDT 24
Peak memory 210044 kb
Host smart-4e857b6a-bea9-44f3-a482-ed09fb68f9f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083038079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3083038079
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2672567967
Short name T875
Test name
Test status
Simulation time 20687413 ps
CPU time 1.16 seconds
Started Jul 24 04:58:57 PM PDT 24
Finished Jul 24 04:58:59 PM PDT 24
Peak memory 209832 kb
Host smart-b838ab53-38bb-406b-a783-5ebb163eabe0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672567967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2672567967
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2917056270
Short name T963
Test name
Test status
Simulation time 24449838 ps
CPU time 0.9 seconds
Started Jul 24 04:58:54 PM PDT 24
Finished Jul 24 04:58:55 PM PDT 24
Peak memory 210428 kb
Host smart-b15a8f67-88f9-42ea-815b-3d45cd3666ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917056270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2917056270
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3611683912
Short name T985
Test name
Test status
Simulation time 24872063 ps
CPU time 1.44 seconds
Started Jul 24 04:58:52 PM PDT 24
Finished Jul 24 04:58:54 PM PDT 24
Peak memory 219416 kb
Host smart-a31a9b56-cc9e-4e6e-947c-ff8fce44ff8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611683912 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3611683912
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1630793426
Short name T165
Test name
Test status
Simulation time 24188244 ps
CPU time 0.81 seconds
Started Jul 24 04:58:52 PM PDT 24
Finished Jul 24 04:58:53 PM PDT 24
Peak memory 209888 kb
Host smart-31a2b662-c9fd-4f28-808e-bf14a8f16ad6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630793426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1630793426
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1516834510
Short name T874
Test name
Test status
Simulation time 530595498 ps
CPU time 3.64 seconds
Started Jul 24 04:58:59 PM PDT 24
Finished Jul 24 04:59:03 PM PDT 24
Peak memory 209668 kb
Host smart-d795134e-dac8-44fd-89fd-3688c20e9cab
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516834510 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1516834510
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.402268559
Short name T952
Test name
Test status
Simulation time 658471589 ps
CPU time 14.81 seconds
Started Jul 24 04:58:55 PM PDT 24
Finished Jul 24 04:59:10 PM PDT 24
Peak memory 209708 kb
Host smart-ed908caf-2300-4055-a9d0-f5985ecd8e69
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402268559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.402268559
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2400642288
Short name T954
Test name
Test status
Simulation time 2506317296 ps
CPU time 5.53 seconds
Started Jul 24 04:59:01 PM PDT 24
Finished Jul 24 04:59:07 PM PDT 24
Peak memory 210064 kb
Host smart-fbe88fc5-7e10-48f8-9491-48fd88a8a225
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400642288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2400642288
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1442150940
Short name T880
Test name
Test status
Simulation time 220413473 ps
CPU time 2.03 seconds
Started Jul 24 04:58:52 PM PDT 24
Finished Jul 24 04:58:54 PM PDT 24
Peak memory 211460 kb
Host smart-5a79f84f-c097-4d9c-a2b0-4c972cc1675c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442150940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1442150940
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3946394737
Short name T877
Test name
Test status
Simulation time 3307719055 ps
CPU time 3.01 seconds
Started Jul 24 04:59:02 PM PDT 24
Finished Jul 24 04:59:05 PM PDT 24
Peak memory 218264 kb
Host smart-c26eff97-4027-49e2-a787-5566483aefa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394639
4737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3946394737
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3974423250
Short name T135
Test name
Test status
Simulation time 87023925 ps
CPU time 2.1 seconds
Started Jul 24 04:58:57 PM PDT 24
Finished Jul 24 04:58:59 PM PDT 24
Peak memory 209984 kb
Host smart-39548558-47d1-4ffa-be52-fdc57ea17b72
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974423250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3974423250
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4107287805
Short name T980
Test name
Test status
Simulation time 38715551 ps
CPU time 1.43 seconds
Started Jul 24 04:59:02 PM PDT 24
Finished Jul 24 04:59:04 PM PDT 24
Peak memory 211992 kb
Host smart-0f67c9d2-72d8-4106-8ef3-32040f787b35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107287805 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.4107287805
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3439812456
Short name T938
Test name
Test status
Simulation time 184807450 ps
CPU time 1.29 seconds
Started Jul 24 04:58:56 PM PDT 24
Finished Jul 24 04:58:57 PM PDT 24
Peak memory 210040 kb
Host smart-72a62e27-ec32-487a-93da-cba700d03457
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439812456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3439812456
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4266719307
Short name T111
Test name
Test status
Simulation time 143279777 ps
CPU time 2.93 seconds
Started Jul 24 04:58:48 PM PDT 24
Finished Jul 24 04:58:51 PM PDT 24
Peak memory 218116 kb
Host smart-fb505527-e009-408b-95f8-3b4f9df32f54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266719307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.4266719307
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4072994031
Short name T109
Test name
Test status
Simulation time 283464915 ps
CPU time 2.61 seconds
Started Jul 24 04:59:02 PM PDT 24
Finished Jul 24 04:59:05 PM PDT 24
Peak memory 218244 kb
Host smart-397f6658-6fd8-4c00-a28d-62b6489dfea0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072994031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.4072994031
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4039023980
Short name T920
Test name
Test status
Simulation time 306448982 ps
CPU time 1.32 seconds
Started Jul 24 04:59:01 PM PDT 24
Finished Jul 24 04:59:02 PM PDT 24
Peak memory 210036 kb
Host smart-0f7dda94-ba47-48ed-8107-388d61c0d510
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039023980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.4039023980
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2792729576
Short name T932
Test name
Test status
Simulation time 91979133 ps
CPU time 3.13 seconds
Started Jul 24 04:59:02 PM PDT 24
Finished Jul 24 04:59:05 PM PDT 24
Peak memory 209904 kb
Host smart-67998e84-fb75-40d8-b2f2-c07666cb5c6b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792729576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2792729576
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2847495334
Short name T943
Test name
Test status
Simulation time 20876663 ps
CPU time 1.13 seconds
Started Jul 24 04:59:04 PM PDT 24
Finished Jul 24 04:59:05 PM PDT 24
Peak memory 219864 kb
Host smart-86824c90-3a4f-4682-9ea6-437c76d39933
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847495334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2847495334
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.349368018
Short name T981
Test name
Test status
Simulation time 36995234 ps
CPU time 1.8 seconds
Started Jul 24 04:58:58 PM PDT 24
Finished Jul 24 04:59:00 PM PDT 24
Peak memory 222040 kb
Host smart-65cf6ccc-fec4-411e-8a4d-c65d63644cb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349368018 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.349368018
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.198213133
Short name T992
Test name
Test status
Simulation time 20836467 ps
CPU time 1.08 seconds
Started Jul 24 04:58:58 PM PDT 24
Finished Jul 24 04:58:59 PM PDT 24
Peak memory 210012 kb
Host smart-5dd5235f-c8cf-4ce7-8d52-7d706c8af5d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198213133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.198213133
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3955730242
Short name T909
Test name
Test status
Simulation time 92470661 ps
CPU time 1.69 seconds
Started Jul 24 04:59:03 PM PDT 24
Finished Jul 24 04:59:05 PM PDT 24
Peak memory 208576 kb
Host smart-62a302b0-9ab5-438b-8d8c-2b75bf7a865e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955730242 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3955730242
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2129821255
Short name T915
Test name
Test status
Simulation time 370734267 ps
CPU time 5.75 seconds
Started Jul 24 04:59:02 PM PDT 24
Finished Jul 24 04:59:08 PM PDT 24
Peak memory 209312 kb
Host smart-ce1ea0c3-892b-48c0-8791-03811b7b9723
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129821255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2129821255
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.679074065
Short name T937
Test name
Test status
Simulation time 1527569968 ps
CPU time 30.08 seconds
Started Jul 24 04:59:02 PM PDT 24
Finished Jul 24 04:59:32 PM PDT 24
Peak memory 209864 kb
Host smart-ff31c338-2530-4ddb-b8d6-6fe4732be52e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679074065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.679074065
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1365247170
Short name T957
Test name
Test status
Simulation time 154114135 ps
CPU time 1.7 seconds
Started Jul 24 04:58:58 PM PDT 24
Finished Jul 24 04:59:00 PM PDT 24
Peak memory 211724 kb
Host smart-81e1c7f3-bc03-45cc-a43a-985abdbc8561
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365247170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1365247170
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1261811208
Short name T898
Test name
Test status
Simulation time 94966605 ps
CPU time 1.87 seconds
Started Jul 24 04:59:05 PM PDT 24
Finished Jul 24 04:59:07 PM PDT 24
Peak memory 219340 kb
Host smart-2863a520-0646-4fc1-a576-65deb89f0bde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126181
1208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1261811208
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.205927717
Short name T983
Test name
Test status
Simulation time 79226371 ps
CPU time 1.31 seconds
Started Jul 24 04:58:58 PM PDT 24
Finished Jul 24 04:58:59 PM PDT 24
Peak memory 210020 kb
Host smart-c69d316b-07dd-4324-b5fc-d27395354ed2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205927717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.205927717
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2820137443
Short name T178
Test name
Test status
Simulation time 141536254 ps
CPU time 1.44 seconds
Started Jul 24 04:59:00 PM PDT 24
Finished Jul 24 04:59:02 PM PDT 24
Peak memory 212188 kb
Host smart-a363f3be-f979-4ffb-be98-c3a1430cd34b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820137443 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2820137443
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.4125877583
Short name T953
Test name
Test status
Simulation time 34332306 ps
CPU time 1.22 seconds
Started Jul 24 04:58:53 PM PDT 24
Finished Jul 24 04:58:54 PM PDT 24
Peak memory 209724 kb
Host smart-3a018689-440c-4663-9bc1-41865a15b331
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125877583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.4125877583
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1731515018
Short name T914
Test name
Test status
Simulation time 403436185 ps
CPU time 3.19 seconds
Started Jul 24 04:59:05 PM PDT 24
Finished Jul 24 04:59:09 PM PDT 24
Peak memory 218100 kb
Host smart-30477f7d-44ba-47b0-badc-05de9f2ee553
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731515018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1731515018
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3616237782
Short name T896
Test name
Test status
Simulation time 18557242 ps
CPU time 1.36 seconds
Started Jul 24 04:59:01 PM PDT 24
Finished Jul 24 04:59:03 PM PDT 24
Peak memory 222028 kb
Host smart-910e3186-f280-4b9b-b113-d4620edef0ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616237782 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3616237782
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2441135800
Short name T163
Test name
Test status
Simulation time 18447792 ps
CPU time 0.86 seconds
Started Jul 24 04:59:00 PM PDT 24
Finished Jul 24 04:59:01 PM PDT 24
Peak memory 209768 kb
Host smart-2381af2a-ed26-408d-a9f2-c58894fe9028
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441135800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2441135800
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2448576018
Short name T969
Test name
Test status
Simulation time 480032662 ps
CPU time 1.24 seconds
Started Jul 24 04:58:55 PM PDT 24
Finished Jul 24 04:58:57 PM PDT 24
Peak memory 209836 kb
Host smart-dd5d7c14-1b20-4f26-9b89-e4ec77a827d3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448576018 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2448576018
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3582449614
Short name T876
Test name
Test status
Simulation time 482056966 ps
CPU time 2.9 seconds
Started Jul 24 04:58:54 PM PDT 24
Finished Jul 24 04:58:57 PM PDT 24
Peak memory 209708 kb
Host smart-0cf80dba-f990-42bd-a67a-deb61aec21d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582449614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3582449614
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1403852963
Short name T137
Test name
Test status
Simulation time 5381450872 ps
CPU time 11.17 seconds
Started Jul 24 04:58:58 PM PDT 24
Finished Jul 24 04:59:09 PM PDT 24
Peak memory 210120 kb
Host smart-d2d86129-4c2a-49f3-a1cb-1387c9dd6d4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403852963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1403852963
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2670822583
Short name T964
Test name
Test status
Simulation time 1099155317 ps
CPU time 1.37 seconds
Started Jul 24 04:58:56 PM PDT 24
Finished Jul 24 04:58:57 PM PDT 24
Peak memory 211432 kb
Host smart-6b7c4458-0514-4f62-9e7b-99448c16b34c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670822583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2670822583
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4278400172
Short name T892
Test name
Test status
Simulation time 213743316 ps
CPU time 2.35 seconds
Started Jul 24 04:59:00 PM PDT 24
Finished Jul 24 04:59:03 PM PDT 24
Peak memory 218216 kb
Host smart-443a87b5-14cb-46de-8b3d-bb7c12ff266f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427840
0172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4278400172
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.100794518
Short name T904
Test name
Test status
Simulation time 105255742 ps
CPU time 1.39 seconds
Started Jul 24 04:59:00 PM PDT 24
Finished Jul 24 04:59:02 PM PDT 24
Peak memory 209920 kb
Host smart-cd031000-1b3d-4ea1-9894-20d79a5f27e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100794518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.100794518
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.236926884
Short name T972
Test name
Test status
Simulation time 169127215 ps
CPU time 1.91 seconds
Started Jul 24 04:58:58 PM PDT 24
Finished Jul 24 04:59:00 PM PDT 24
Peak memory 211956 kb
Host smart-98c62da8-0194-4b70-82be-2ee8dd086f02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236926884 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.236926884
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.279854848
Short name T910
Test name
Test status
Simulation time 34732611 ps
CPU time 1.44 seconds
Started Jul 24 04:59:00 PM PDT 24
Finished Jul 24 04:59:02 PM PDT 24
Peak memory 211960 kb
Host smart-7a8b5c9d-5bf9-4491-a864-bd2eb47a7ec2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279854848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.279854848
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1342875357
Short name T918
Test name
Test status
Simulation time 51086979 ps
CPU time 2.33 seconds
Started Jul 24 04:59:06 PM PDT 24
Finished Jul 24 04:59:09 PM PDT 24
Peak memory 218296 kb
Host smart-174f4760-bede-4494-90ec-16ea952dd92b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342875357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1342875357
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.436495416
Short name T118
Test name
Test status
Simulation time 63358040 ps
CPU time 2.68 seconds
Started Jul 24 04:59:01 PM PDT 24
Finished Jul 24 04:59:04 PM PDT 24
Peak memory 218176 kb
Host smart-fc26c7a6-0d0d-4a4a-b7cc-9535710ddde7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436495416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.436495416
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3078596602
Short name T927
Test name
Test status
Simulation time 37234952 ps
CPU time 1.06 seconds
Started Jul 24 04:59:05 PM PDT 24
Finished Jul 24 04:59:06 PM PDT 24
Peak memory 218300 kb
Host smart-417f66d7-5257-4731-9e44-0cbc89dd4a1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078596602 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3078596602
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1782305006
Short name T164
Test name
Test status
Simulation time 45676684 ps
CPU time 0.98 seconds
Started Jul 24 04:58:59 PM PDT 24
Finished Jul 24 04:59:01 PM PDT 24
Peak memory 209636 kb
Host smart-171fff86-94ac-43b2-876e-21006e9ad24b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782305006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1782305006
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1151614458
Short name T883
Test name
Test status
Simulation time 37320702 ps
CPU time 1.13 seconds
Started Jul 24 04:59:04 PM PDT 24
Finished Jul 24 04:59:05 PM PDT 24
Peak memory 209788 kb
Host smart-6cdb14e3-8773-41ca-a40f-2def7685f2b7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151614458 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1151614458
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.4226737592
Short name T973
Test name
Test status
Simulation time 1321823605 ps
CPU time 7.54 seconds
Started Jul 24 04:58:59 PM PDT 24
Finished Jul 24 04:59:07 PM PDT 24
Peak memory 209180 kb
Host smart-b63260a0-d5f9-4d6c-8c3d-3f00046567d9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226737592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.4226737592
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.324916828
Short name T976
Test name
Test status
Simulation time 5082045135 ps
CPU time 27.02 seconds
Started Jul 24 04:59:00 PM PDT 24
Finished Jul 24 04:59:27 PM PDT 24
Peak memory 209992 kb
Host smart-2d69c659-2337-4ce6-b37d-2da814122641
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324916828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.324916828
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.20675992
Short name T991
Test name
Test status
Simulation time 1042075131 ps
CPU time 1.38 seconds
Started Jul 24 04:59:06 PM PDT 24
Finished Jul 24 04:59:08 PM PDT 24
Peak memory 209892 kb
Host smart-9765cb1f-a8e9-439a-891a-27618c75acfd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20675992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.20675992
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2323670763
Short name T986
Test name
Test status
Simulation time 285632489 ps
CPU time 1.48 seconds
Started Jul 24 04:58:59 PM PDT 24
Finished Jul 24 04:59:01 PM PDT 24
Peak memory 219248 kb
Host smart-c2e191cc-1996-4d45-ac34-4337e3bf9872
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232367
0763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2323670763
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1347508811
Short name T884
Test name
Test status
Simulation time 55262719 ps
CPU time 2.01 seconds
Started Jul 24 04:58:57 PM PDT 24
Finished Jul 24 04:59:00 PM PDT 24
Peak memory 209904 kb
Host smart-d28d8414-df7c-4948-8e64-10e41e61a4c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347508811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1347508811
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.39797218
Short name T975
Test name
Test status
Simulation time 116558908 ps
CPU time 1.12 seconds
Started Jul 24 04:59:02 PM PDT 24
Finished Jul 24 04:59:03 PM PDT 24
Peak memory 209948 kb
Host smart-78379d81-4fb7-4ded-a736-821432ecd872
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39797218 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.39797218
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2226261426
Short name T942
Test name
Test status
Simulation time 355544443 ps
CPU time 1.39 seconds
Started Jul 24 04:59:03 PM PDT 24
Finished Jul 24 04:59:05 PM PDT 24
Peak memory 212076 kb
Host smart-130a07ec-eb50-4965-be8d-ab1681b92a63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226261426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2226261426
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2877674360
Short name T956
Test name
Test status
Simulation time 106160153 ps
CPU time 2.66 seconds
Started Jul 24 04:59:02 PM PDT 24
Finished Jul 24 04:59:05 PM PDT 24
Peak memory 218344 kb
Host smart-c828d9d9-c866-4a62-9f5d-d7319bde8505
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877674360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2877674360
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1202380415
Short name T961
Test name
Test status
Simulation time 38138954 ps
CPU time 1.3 seconds
Started Jul 24 04:59:11 PM PDT 24
Finished Jul 24 04:59:13 PM PDT 24
Peak memory 218372 kb
Host smart-a8831a99-c190-48aa-a73c-8a5b2fa3800c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202380415 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1202380415
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3006093011
Short name T906
Test name
Test status
Simulation time 15751133 ps
CPU time 0.91 seconds
Started Jul 24 04:58:59 PM PDT 24
Finished Jul 24 04:59:01 PM PDT 24
Peak memory 209956 kb
Host smart-0dea6e62-d39c-42cf-8baa-3330943cb3e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006093011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3006093011
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1817251981
Short name T967
Test name
Test status
Simulation time 138999900 ps
CPU time 1.55 seconds
Started Jul 24 04:59:22 PM PDT 24
Finished Jul 24 04:59:23 PM PDT 24
Peak memory 209872 kb
Host smart-972d0890-9e00-4782-b48d-af5d30c6c5b5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817251981 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1817251981
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2275647799
Short name T890
Test name
Test status
Simulation time 530776447 ps
CPU time 3.29 seconds
Started Jul 24 04:59:03 PM PDT 24
Finished Jul 24 04:59:06 PM PDT 24
Peak memory 209184 kb
Host smart-b41435b7-80a7-4946-833a-f0fcbb8c8295
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275647799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2275647799
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3254316928
Short name T982
Test name
Test status
Simulation time 6107280491 ps
CPU time 8.31 seconds
Started Jul 24 04:59:00 PM PDT 24
Finished Jul 24 04:59:09 PM PDT 24
Peak memory 210004 kb
Host smart-b1d018b4-911d-45af-9450-ca26583fa7a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254316928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3254316928
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2351052315
Short name T899
Test name
Test status
Simulation time 111084332 ps
CPU time 3.31 seconds
Started Jul 24 04:59:02 PM PDT 24
Finished Jul 24 04:59:05 PM PDT 24
Peak memory 211672 kb
Host smart-5ee3ada8-49be-4d36-942f-ad4f8222557e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351052315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2351052315
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2803726929
Short name T881
Test name
Test status
Simulation time 317154536 ps
CPU time 1.61 seconds
Started Jul 24 04:58:58 PM PDT 24
Finished Jul 24 04:59:00 PM PDT 24
Peak memory 219472 kb
Host smart-85827f37-1216-43d9-8d7a-996a9ee9ca69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280372
6929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2803726929
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3084483259
Short name T134
Test name
Test status
Simulation time 321711338 ps
CPU time 1.99 seconds
Started Jul 24 04:59:00 PM PDT 24
Finished Jul 24 04:59:02 PM PDT 24
Peak memory 209992 kb
Host smart-0af581d6-2aee-4ed1-80a7-fb85208167d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084483259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3084483259
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3757003759
Short name T939
Test name
Test status
Simulation time 54856497 ps
CPU time 1.36 seconds
Started Jul 24 04:59:05 PM PDT 24
Finished Jul 24 04:59:06 PM PDT 24
Peak memory 209960 kb
Host smart-62d44c77-56b8-4365-8d2e-cc82567ac62d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757003759 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3757003759
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.486294981
Short name T911
Test name
Test status
Simulation time 106955064 ps
CPU time 1.39 seconds
Started Jul 24 04:59:26 PM PDT 24
Finished Jul 24 04:59:28 PM PDT 24
Peak memory 209956 kb
Host smart-aa8b6f3e-97c6-45b7-9b8d-57ed7efdbceb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486294981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.486294981
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3204501958
Short name T993
Test name
Test status
Simulation time 40232123 ps
CPU time 2.89 seconds
Started Jul 24 04:58:59 PM PDT 24
Finished Jul 24 04:59:03 PM PDT 24
Peak memory 218220 kb
Host smart-ced73140-5f88-4ce3-8ba2-4b09c65c0797
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204501958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3204501958
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2462644264
Short name T900
Test name
Test status
Simulation time 35229501 ps
CPU time 1.2 seconds
Started Jul 24 04:59:32 PM PDT 24
Finished Jul 24 04:59:34 PM PDT 24
Peak memory 218920 kb
Host smart-19da9a8d-5be7-4168-b173-5bd875461f55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462644264 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2462644264
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3475058165
Short name T172
Test name
Test status
Simulation time 18946426 ps
CPU time 0.94 seconds
Started Jul 24 04:59:10 PM PDT 24
Finished Jul 24 04:59:11 PM PDT 24
Peak memory 209980 kb
Host smart-6dadd36f-a7da-4a3c-9f34-38934844a8c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475058165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3475058165
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2756739562
Short name T878
Test name
Test status
Simulation time 57853187 ps
CPU time 1.94 seconds
Started Jul 24 04:59:00 PM PDT 24
Finished Jul 24 04:59:03 PM PDT 24
Peak memory 209796 kb
Host smart-eb9076f6-eb7e-4121-8a21-456de5a20ade
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756739562 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2756739562
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2715237675
Short name T955
Test name
Test status
Simulation time 1641954171 ps
CPU time 10.18 seconds
Started Jul 24 04:59:06 PM PDT 24
Finished Jul 24 04:59:16 PM PDT 24
Peak memory 209712 kb
Host smart-363c569a-472e-46c3-95eb-2c42afdae4a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715237675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2715237675
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3072123472
Short name T895
Test name
Test status
Simulation time 4115157442 ps
CPU time 10.79 seconds
Started Jul 24 04:58:59 PM PDT 24
Finished Jul 24 04:59:10 PM PDT 24
Peak memory 209244 kb
Host smart-32b2ef16-7d4f-4e30-ac3c-c8aae47d15db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072123472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3072123472
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2822327756
Short name T997
Test name
Test status
Simulation time 126733703 ps
CPU time 2.12 seconds
Started Jul 24 04:59:06 PM PDT 24
Finished Jul 24 04:59:09 PM PDT 24
Peak memory 211116 kb
Host smart-cfc59b70-7f2d-4cdb-b2cb-d0a8c499dc15
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822327756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2822327756
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3274512838
Short name T886
Test name
Test status
Simulation time 854935539 ps
CPU time 2.44 seconds
Started Jul 24 04:59:04 PM PDT 24
Finished Jul 24 04:59:06 PM PDT 24
Peak memory 218180 kb
Host smart-318e7636-e9b6-4385-8935-dd660054b99a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327451
2838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3274512838
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2674028831
Short name T949
Test name
Test status
Simulation time 102273673 ps
CPU time 2.97 seconds
Started Jul 24 04:59:01 PM PDT 24
Finished Jul 24 04:59:04 PM PDT 24
Peak memory 209880 kb
Host smart-2f748b84-1605-44e1-88a8-c67b732af593
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674028831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2674028831
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2354547252
Short name T970
Test name
Test status
Simulation time 25235177 ps
CPU time 1.02 seconds
Started Jul 24 04:59:03 PM PDT 24
Finished Jul 24 04:59:04 PM PDT 24
Peak memory 209904 kb
Host smart-5357a374-eaa6-4297-adbf-c2308c4fb05d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354547252 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2354547252
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2644364151
Short name T175
Test name
Test status
Simulation time 33852907 ps
CPU time 1.67 seconds
Started Jul 24 04:59:05 PM PDT 24
Finished Jul 24 04:59:07 PM PDT 24
Peak memory 209908 kb
Host smart-23e16f30-34c9-4e0d-80e8-fb8102393ba9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644364151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2644364151
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.4258123965
Short name T958
Test name
Test status
Simulation time 67483755 ps
CPU time 2.14 seconds
Started Jul 24 04:59:02 PM PDT 24
Finished Jul 24 04:59:04 PM PDT 24
Peak memory 218084 kb
Host smart-e5a01632-e3b4-4bb1-b5b4-f5dab3bfda7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258123965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.4258123965
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2740389006
Short name T131
Test name
Test status
Simulation time 103974881 ps
CPU time 3.24 seconds
Started Jul 24 04:59:24 PM PDT 24
Finished Jul 24 04:59:27 PM PDT 24
Peak memory 218164 kb
Host smart-6c9624b4-267c-4d94-9c90-2fe3f6591a94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740389006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2740389006
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1992283752
Short name T944
Test name
Test status
Simulation time 51424362 ps
CPU time 1.21 seconds
Started Jul 24 04:59:04 PM PDT 24
Finished Jul 24 04:59:06 PM PDT 24
Peak memory 219660 kb
Host smart-68ac79d1-28d5-4849-b513-1ec8cb3ce01b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992283752 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1992283752
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.181689965
Short name T930
Test name
Test status
Simulation time 17729466 ps
CPU time 1.08 seconds
Started Jul 24 04:59:13 PM PDT 24
Finished Jul 24 04:59:14 PM PDT 24
Peak memory 218108 kb
Host smart-b143db20-dc47-44bb-9f1d-8158a8213e3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181689965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.181689965
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.116644762
Short name T984
Test name
Test status
Simulation time 84574794 ps
CPU time 1.08 seconds
Started Jul 24 04:59:03 PM PDT 24
Finished Jul 24 04:59:04 PM PDT 24
Peak memory 209800 kb
Host smart-6e88865a-6208-4fa4-8cb7-aa17140a3b6e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116644762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.116644762
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1222897617
Short name T1000
Test name
Test status
Simulation time 665022129 ps
CPU time 12.59 seconds
Started Jul 24 04:59:22 PM PDT 24
Finished Jul 24 04:59:34 PM PDT 24
Peak memory 209760 kb
Host smart-aef9c5c1-dd29-4fd1-8bf0-d9ea37c276dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222897617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1222897617
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.217702936
Short name T891
Test name
Test status
Simulation time 695080810 ps
CPU time 6.54 seconds
Started Jul 24 04:59:23 PM PDT 24
Finished Jul 24 04:59:29 PM PDT 24
Peak memory 209724 kb
Host smart-4c64d9f3-5b27-44bf-825d-aa44873af517
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217702936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.217702936
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3363311703
Short name T971
Test name
Test status
Simulation time 151722955 ps
CPU time 2.08 seconds
Started Jul 24 04:59:05 PM PDT 24
Finished Jul 24 04:59:08 PM PDT 24
Peak memory 211396 kb
Host smart-57a9578b-bc64-43a0-8f32-cd047bc2298a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363311703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3363311703
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1235229433
Short name T908
Test name
Test status
Simulation time 671547345 ps
CPU time 2.76 seconds
Started Jul 24 04:59:00 PM PDT 24
Finished Jul 24 04:59:03 PM PDT 24
Peak memory 218180 kb
Host smart-d1d9e4e3-4df5-426a-ab55-859836c94214
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123522
9433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1235229433
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.4279499706
Short name T136
Test name
Test status
Simulation time 201155339 ps
CPU time 1.37 seconds
Started Jul 24 04:59:00 PM PDT 24
Finished Jul 24 04:59:02 PM PDT 24
Peak memory 209960 kb
Host smart-756971fc-7efe-4ed1-8454-f207d272ca0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279499706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.4279499706
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1335883257
Short name T180
Test name
Test status
Simulation time 67048151 ps
CPU time 1.7 seconds
Started Jul 24 04:58:57 PM PDT 24
Finished Jul 24 04:58:59 PM PDT 24
Peak memory 210068 kb
Host smart-a5332e97-2e40-4f0a-98bf-cc7a57a59825
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335883257 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1335883257
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2734487677
Short name T181
Test name
Test status
Simulation time 90080224 ps
CPU time 1.43 seconds
Started Jul 24 04:59:06 PM PDT 24
Finished Jul 24 04:59:08 PM PDT 24
Peak memory 218104 kb
Host smart-d705693a-29fe-4335-af5c-eef0dbc506e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734487677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2734487677
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4011831892
Short name T897
Test name
Test status
Simulation time 41381976 ps
CPU time 2.4 seconds
Started Jul 24 04:58:59 PM PDT 24
Finished Jul 24 04:59:01 PM PDT 24
Peak memory 219240 kb
Host smart-3eef74d3-cf4e-4598-a92b-d19b00020992
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011831892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.4011831892
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3508936801
Short name T124
Test name
Test status
Simulation time 1074560029 ps
CPU time 2.69 seconds
Started Jul 24 04:59:01 PM PDT 24
Finished Jul 24 04:59:04 PM PDT 24
Peak memory 222652 kb
Host smart-d52f425e-f838-4525-badd-8e2ffecc246d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508936801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3508936801
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2025598071
Short name T253
Test name
Test status
Simulation time 14535040 ps
CPU time 1.08 seconds
Started Jul 24 06:57:07 PM PDT 24
Finished Jul 24 06:57:08 PM PDT 24
Peak memory 208952 kb
Host smart-a374be31-6207-450d-9bd7-5a193a362260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025598071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2025598071
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2521437901
Short name T97
Test name
Test status
Simulation time 839623125 ps
CPU time 11.32 seconds
Started Jul 24 06:56:54 PM PDT 24
Finished Jul 24 06:57:05 PM PDT 24
Peak memory 226200 kb
Host smart-22480b48-5cf8-4b23-8d30-13704d61a21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521437901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2521437901
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2720243537
Short name T685
Test name
Test status
Simulation time 2176341018 ps
CPU time 4.1 seconds
Started Jul 24 06:57:00 PM PDT 24
Finished Jul 24 06:57:04 PM PDT 24
Peak memory 217816 kb
Host smart-ef7d9681-7d85-45df-9875-c4eb61785d15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720243537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2720243537
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.948397007
Short name T292
Test name
Test status
Simulation time 12221232667 ps
CPU time 50.63 seconds
Started Jul 24 06:57:00 PM PDT 24
Finished Jul 24 06:57:51 PM PDT 24
Peak memory 219012 kb
Host smart-e19f3e28-31f1-43fc-b30d-a6eeb2d7d6a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948397007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.948397007
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2025763609
Short name T836
Test name
Test status
Simulation time 601369269 ps
CPU time 2.32 seconds
Started Jul 24 06:56:59 PM PDT 24
Finished Jul 24 06:57:02 PM PDT 24
Peak memory 217864 kb
Host smart-34fa4471-1dde-4305-a9fc-eda9b9454b53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025763609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2
025763609
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2799773229
Short name T522
Test name
Test status
Simulation time 1080404739 ps
CPU time 15.55 seconds
Started Jul 24 06:56:58 PM PDT 24
Finished Jul 24 06:57:14 PM PDT 24
Peak memory 218304 kb
Host smart-c7e29719-0a53-41cc-9a53-34693a87ccce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799773229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2799773229
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.33043832
Short name T613
Test name
Test status
Simulation time 3683772976 ps
CPU time 33.46 seconds
Started Jul 24 06:56:58 PM PDT 24
Finished Jul 24 06:57:31 PM PDT 24
Peak memory 217768 kb
Host smart-62abf5eb-7d73-4a0f-b4bc-86bf0bd71e7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33043832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jt
ag_regwen_during_op.33043832
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3413919926
Short name T819
Test name
Test status
Simulation time 1219530802 ps
CPU time 6.91 seconds
Started Jul 24 06:57:03 PM PDT 24
Finished Jul 24 06:57:10 PM PDT 24
Peak memory 217828 kb
Host smart-aaef1e5f-fdfd-4601-8363-632d5d8eb536
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413919926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3413919926
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.87281376
Short name T236
Test name
Test status
Simulation time 1668903459 ps
CPU time 40.56 seconds
Started Jul 24 06:56:58 PM PDT 24
Finished Jul 24 06:57:38 PM PDT 24
Peak memory 250872 kb
Host smart-356cc9f2-0d70-4b2d-beaa-896b66075a6c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87281376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
state_failure.87281376
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1595794038
Short name T356
Test name
Test status
Simulation time 2030534958 ps
CPU time 17.6 seconds
Started Jul 24 06:56:59 PM PDT 24
Finished Jul 24 06:57:17 PM PDT 24
Peak memory 250940 kb
Host smart-dc4850b3-1bdf-488b-baee-adffa1b6877c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595794038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1595794038
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1154917713
Short name T268
Test name
Test status
Simulation time 45280250 ps
CPU time 2.51 seconds
Started Jul 24 06:56:50 PM PDT 24
Finished Jul 24 06:56:53 PM PDT 24
Peak memory 222316 kb
Host smart-26ebced6-fcd6-4167-bceb-b1ae6ae06eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154917713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1154917713
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2158025972
Short name T160
Test name
Test status
Simulation time 1082334883 ps
CPU time 9.11 seconds
Started Jul 24 06:57:00 PM PDT 24
Finished Jul 24 06:57:09 PM PDT 24
Peak memory 214676 kb
Host smart-806cb83f-4e28-4e48-b700-bc95a04aa0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158025972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2158025972
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2960544158
Short name T65
Test name
Test status
Simulation time 201517299 ps
CPU time 34.37 seconds
Started Jul 24 06:57:07 PM PDT 24
Finished Jul 24 06:57:41 PM PDT 24
Peak memory 269800 kb
Host smart-6eb5394e-f074-4105-bae3-38ae2ec7aa67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960544158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2960544158
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2482312896
Short name T279
Test name
Test status
Simulation time 411877922 ps
CPU time 9.74 seconds
Started Jul 24 06:56:59 PM PDT 24
Finished Jul 24 06:57:09 PM PDT 24
Peak memory 218508 kb
Host smart-87f95dd1-2416-41d9-b9d3-1aa8f7d2dcd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482312896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2482312896
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.684840787
Short name T577
Test name
Test status
Simulation time 755366275 ps
CPU time 16.04 seconds
Started Jul 24 06:56:59 PM PDT 24
Finished Jul 24 06:57:16 PM PDT 24
Peak memory 225984 kb
Host smart-ebc604ae-cb6c-48c4-8e44-807e72fb2694
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684840787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.684840787
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.4037996135
Short name T788
Test name
Test status
Simulation time 940390658 ps
CPU time 11.79 seconds
Started Jul 24 06:56:58 PM PDT 24
Finished Jul 24 06:57:10 PM PDT 24
Peak memory 218420 kb
Host smart-347771a8-b7b7-40a4-aebd-700da9567482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037996135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.4037996135
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2021848852
Short name T722
Test name
Test status
Simulation time 153335025 ps
CPU time 1.77 seconds
Started Jul 24 06:56:50 PM PDT 24
Finished Jul 24 06:56:52 PM PDT 24
Peak memory 217756 kb
Host smart-e39e71ae-3c90-45b8-bbe8-54f13a83e55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021848852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2021848852
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2055382951
Short name T101
Test name
Test status
Simulation time 293690055 ps
CPU time 29.03 seconds
Started Jul 24 06:56:49 PM PDT 24
Finished Jul 24 06:57:18 PM PDT 24
Peak memory 250992 kb
Host smart-8cf65727-e7e2-4b77-8d62-630f05e9a137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055382951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2055382951
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.891433256
Short name T657
Test name
Test status
Simulation time 96580603 ps
CPU time 3.35 seconds
Started Jul 24 06:56:50 PM PDT 24
Finished Jul 24 06:56:53 PM PDT 24
Peak memory 222484 kb
Host smart-e0c3176c-e29e-47f8-b7f3-1c4301ba31f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891433256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.891433256
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.4025864377
Short name T829
Test name
Test status
Simulation time 4022465170 ps
CPU time 48.44 seconds
Started Jul 24 06:57:07 PM PDT 24
Finished Jul 24 06:57:56 PM PDT 24
Peak memory 250868 kb
Host smart-1f6ec557-78db-44bf-bac7-d485eec61455
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025864377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.4025864377
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.4208663383
Short name T157
Test name
Test status
Simulation time 37992698452 ps
CPU time 212.1 seconds
Started Jul 24 06:57:06 PM PDT 24
Finished Jul 24 07:00:38 PM PDT 24
Peak memory 278376 kb
Host smart-9de79667-1a0b-4bbc-b7b3-471c604ba1f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4208663383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.4208663383
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.553950341
Short name T854
Test name
Test status
Simulation time 23943837 ps
CPU time 1.12 seconds
Started Jul 24 06:56:51 PM PDT 24
Finished Jul 24 06:56:53 PM PDT 24
Peak memory 211920 kb
Host smart-dd12387f-757a-4ff1-beba-8cd5c76e37d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553950341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.553950341
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3913319810
Short name T696
Test name
Test status
Simulation time 58767230 ps
CPU time 0.83 seconds
Started Jul 24 06:57:18 PM PDT 24
Finished Jul 24 06:57:19 PM PDT 24
Peak memory 208888 kb
Host smart-2733961e-aa48-4cb2-a613-088e521fa55c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913319810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3913319810
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.262020255
Short name T625
Test name
Test status
Simulation time 139932368 ps
CPU time 0.89 seconds
Started Jul 24 06:57:09 PM PDT 24
Finished Jul 24 06:57:10 PM PDT 24
Peak memory 208844 kb
Host smart-d9817809-affd-4151-9f47-9ea6e3c534ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262020255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.262020255
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3030243312
Short name T764
Test name
Test status
Simulation time 378082872 ps
CPU time 16.6 seconds
Started Jul 24 06:57:06 PM PDT 24
Finished Jul 24 06:57:23 PM PDT 24
Peak memory 226140 kb
Host smart-85861886-0ea8-4059-ab5c-d7db1c6e3fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030243312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3030243312
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1609922354
Short name T621
Test name
Test status
Simulation time 2466535392 ps
CPU time 14.81 seconds
Started Jul 24 06:57:13 PM PDT 24
Finished Jul 24 06:57:28 PM PDT 24
Peak memory 217772 kb
Host smart-86088ee8-7bcc-4240-8e95-ad7b0efe17c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609922354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1609922354
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1997898990
Short name T350
Test name
Test status
Simulation time 5817418604 ps
CPU time 23.3 seconds
Started Jul 24 06:57:13 PM PDT 24
Finished Jul 24 06:57:36 PM PDT 24
Peak memory 218632 kb
Host smart-da449a7e-408e-4a57-8a0b-65eb17dcae29
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997898990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1997898990
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1297226822
Short name T652
Test name
Test status
Simulation time 3676370455 ps
CPU time 4.23 seconds
Started Jul 24 06:57:13 PM PDT 24
Finished Jul 24 06:57:18 PM PDT 24
Peak memory 217796 kb
Host smart-961012db-25d3-4103-87fd-6ef78dc860c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297226822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.1
297226822
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.4241373854
Short name T783
Test name
Test status
Simulation time 697105360 ps
CPU time 10.02 seconds
Started Jul 24 06:57:12 PM PDT 24
Finished Jul 24 06:57:22 PM PDT 24
Peak memory 218332 kb
Host smart-e44bda79-88e9-46f1-8043-7ed36feebb0e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241373854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.4241373854
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2842279457
Short name T558
Test name
Test status
Simulation time 998868543 ps
CPU time 30.97 seconds
Started Jul 24 06:57:13 PM PDT 24
Finished Jul 24 06:57:44 PM PDT 24
Peak memory 217700 kb
Host smart-56341900-42e8-42b2-bab0-44db3a39a766
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842279457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2842279457
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.558440074
Short name T663
Test name
Test status
Simulation time 728350307 ps
CPU time 5.75 seconds
Started Jul 24 06:57:07 PM PDT 24
Finished Jul 24 06:57:12 PM PDT 24
Peak memory 217636 kb
Host smart-6ce78ba1-be68-438b-a6e9-6a348084c852
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558440074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.558440074
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3652363977
Short name T731
Test name
Test status
Simulation time 6444973192 ps
CPU time 33.47 seconds
Started Jul 24 06:57:07 PM PDT 24
Finished Jul 24 06:57:41 PM PDT 24
Peak memory 251008 kb
Host smart-b919a656-a1c3-4970-b533-df998617a1de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652363977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3652363977
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3687797054
Short name T863
Test name
Test status
Simulation time 1668738783 ps
CPU time 30.64 seconds
Started Jul 24 06:57:13 PM PDT 24
Finished Jul 24 06:57:44 PM PDT 24
Peak memory 250908 kb
Host smart-178813c4-be44-49ce-8632-7096ea622818
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687797054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3687797054
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2938491562
Short name T535
Test name
Test status
Simulation time 62773993 ps
CPU time 2.44 seconds
Started Jul 24 06:57:06 PM PDT 24
Finished Jul 24 06:57:09 PM PDT 24
Peak memory 218356 kb
Host smart-1f6009a1-4fdf-4103-afc6-0b267edfb1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938491562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2938491562
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2625005021
Short name T454
Test name
Test status
Simulation time 203989433 ps
CPU time 12.98 seconds
Started Jul 24 06:57:08 PM PDT 24
Finished Jul 24 06:57:21 PM PDT 24
Peak memory 214044 kb
Host smart-d28fdce3-f8a2-4e75-b434-09b37a9beeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625005021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2625005021
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3126835162
Short name T92
Test name
Test status
Simulation time 243030477 ps
CPU time 21.66 seconds
Started Jul 24 06:57:21 PM PDT 24
Finished Jul 24 06:57:43 PM PDT 24
Peak memory 281284 kb
Host smart-24570370-c1dc-41b5-bc20-de5bbf75290b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126835162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3126835162
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.553283275
Short name T204
Test name
Test status
Simulation time 740310004 ps
CPU time 8.73 seconds
Started Jul 24 06:57:20 PM PDT 24
Finished Jul 24 06:57:29 PM PDT 24
Peak memory 225404 kb
Host smart-cb694e22-5ac5-4a96-852a-a13a5b013ec7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553283275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.553283275
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2194380558
Short name T576
Test name
Test status
Simulation time 519984084 ps
CPU time 12.28 seconds
Started Jul 24 06:57:06 PM PDT 24
Finished Jul 24 06:57:19 PM PDT 24
Peak memory 218412 kb
Host smart-e61cfc0b-c0e0-43d0-96b6-105ac4b19215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194380558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2194380558
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.4151048036
Short name T569
Test name
Test status
Simulation time 54194854 ps
CPU time 3.99 seconds
Started Jul 24 06:57:09 PM PDT 24
Finished Jul 24 06:57:13 PM PDT 24
Peak memory 214512 kb
Host smart-67e90a50-5ab0-47fb-833c-616d72d93b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151048036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.4151048036
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2708799506
Short name T17
Test name
Test status
Simulation time 636529933 ps
CPU time 30.47 seconds
Started Jul 24 06:57:05 PM PDT 24
Finished Jul 24 06:57:36 PM PDT 24
Peak memory 250960 kb
Host smart-d8ac91c5-2e1f-49cd-b0a8-d5ae515559e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708799506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2708799506
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1763213122
Short name T614
Test name
Test status
Simulation time 490018739 ps
CPU time 8.36 seconds
Started Jul 24 06:57:07 PM PDT 24
Finished Jul 24 06:57:16 PM PDT 24
Peak memory 250932 kb
Host smart-4942efa1-38fe-44f3-98ba-762e3f6b5274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763213122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1763213122
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.4005943943
Short name T656
Test name
Test status
Simulation time 3262222523 ps
CPU time 109.46 seconds
Started Jul 24 06:57:20 PM PDT 24
Finished Jul 24 06:59:09 PM PDT 24
Peak memory 277916 kb
Host smart-3b5434de-9134-40e0-9c27-8c6cc548b478
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005943943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.4005943943
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3711554776
Short name T629
Test name
Test status
Simulation time 140380975318 ps
CPU time 306.74 seconds
Started Jul 24 06:57:20 PM PDT 24
Finished Jul 24 07:02:27 PM PDT 24
Peak memory 311300 kb
Host smart-82823926-04b8-4011-be8a-89f364c56886
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3711554776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.3711554776
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2117685267
Short name T598
Test name
Test status
Simulation time 12307140 ps
CPU time 0.99 seconds
Started Jul 24 06:57:06 PM PDT 24
Finished Jul 24 06:57:07 PM PDT 24
Peak memory 209248 kb
Host smart-88405921-9136-4260-adc7-954a9fea4711
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117685267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2117685267
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.133569528
Short name T413
Test name
Test status
Simulation time 44543361 ps
CPU time 0.87 seconds
Started Jul 24 06:58:51 PM PDT 24
Finished Jul 24 06:58:52 PM PDT 24
Peak memory 208908 kb
Host smart-40349f05-550b-4819-adbd-6a6bdcc4d761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133569528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.133569528
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1780217117
Short name T56
Test name
Test status
Simulation time 898582871 ps
CPU time 20.12 seconds
Started Jul 24 06:58:44 PM PDT 24
Finished Jul 24 06:59:04 PM PDT 24
Peak memory 218512 kb
Host smart-2aa09dc1-d378-49b2-ac79-da90e60579ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780217117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1780217117
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2390314311
Short name T161
Test name
Test status
Simulation time 1320579434 ps
CPU time 4.34 seconds
Started Jul 24 06:58:44 PM PDT 24
Finished Jul 24 06:58:49 PM PDT 24
Peak memory 217284 kb
Host smart-56555474-359b-4162-9975-03bd9f900d22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390314311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2390314311
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3030306747
Short name T91
Test name
Test status
Simulation time 13774548786 ps
CPU time 91.46 seconds
Started Jul 24 06:58:44 PM PDT 24
Finished Jul 24 07:00:15 PM PDT 24
Peak memory 218976 kb
Host smart-23da887a-f4ea-493c-9ea4-767e37eca2f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030306747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3030306747
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3465328293
Short name T747
Test name
Test status
Simulation time 690482714 ps
CPU time 7.89 seconds
Started Jul 24 06:58:45 PM PDT 24
Finished Jul 24 06:58:53 PM PDT 24
Peak memory 218280 kb
Host smart-b0b5192c-a9ca-4340-be68-67a88f21ce67
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465328293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3465328293
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.853920034
Short name T305
Test name
Test status
Simulation time 866773522 ps
CPU time 5.36 seconds
Started Jul 24 06:58:48 PM PDT 24
Finished Jul 24 06:58:53 PM PDT 24
Peak memory 217708 kb
Host smart-09930536-feb8-4b29-9dcb-86575b78b54d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853920034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
853920034
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3994663974
Short name T480
Test name
Test status
Simulation time 1547697299 ps
CPU time 50.44 seconds
Started Jul 24 06:58:45 PM PDT 24
Finished Jul 24 06:59:35 PM PDT 24
Peak memory 283708 kb
Host smart-d4cbfc14-d34b-42bc-8ea4-8ee7e4923f83
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994663974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3994663974
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.888629017
Short name T381
Test name
Test status
Simulation time 2889708237 ps
CPU time 17.03 seconds
Started Jul 24 06:58:44 PM PDT 24
Finished Jul 24 06:59:01 PM PDT 24
Peak memory 250984 kb
Host smart-4b920455-8505-4363-89ec-65b7fc367dc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888629017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.888629017
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.1258449957
Short name T635
Test name
Test status
Simulation time 209886375 ps
CPU time 2.71 seconds
Started Jul 24 06:58:44 PM PDT 24
Finished Jul 24 06:58:47 PM PDT 24
Peak memory 218280 kb
Host smart-55c1a8b8-f3c0-440f-baf3-919929a92403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258449957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1258449957
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3312812504
Short name T231
Test name
Test status
Simulation time 488482311 ps
CPU time 15.59 seconds
Started Jul 24 06:58:45 PM PDT 24
Finished Jul 24 06:59:01 PM PDT 24
Peak memory 226124 kb
Host smart-c93cf345-ea0e-4c15-a970-cf1deb28192f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312812504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3312812504
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3222829148
Short name T807
Test name
Test status
Simulation time 1508994091 ps
CPU time 12.17 seconds
Started Jul 24 06:58:54 PM PDT 24
Finished Jul 24 06:59:07 PM PDT 24
Peak memory 226068 kb
Host smart-a2d3c809-de65-4a9a-a2d4-330d3cf921a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222829148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3222829148
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3984808597
Short name T563
Test name
Test status
Simulation time 984394960 ps
CPU time 7.06 seconds
Started Jul 24 06:58:49 PM PDT 24
Finished Jul 24 06:58:56 PM PDT 24
Peak memory 218264 kb
Host smart-6268ae4f-d612-4e77-8360-727574bec63d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984808597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3984808597
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3327215486
Short name T327
Test name
Test status
Simulation time 338929936 ps
CPU time 8.26 seconds
Started Jul 24 06:58:44 PM PDT 24
Finished Jul 24 06:58:53 PM PDT 24
Peak memory 226168 kb
Host smart-68295ce6-4d58-4865-816a-a4d466f1a0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327215486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3327215486
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.2050780959
Short name T307
Test name
Test status
Simulation time 367791778 ps
CPU time 3.36 seconds
Started Jul 24 06:58:47 PM PDT 24
Finished Jul 24 06:58:51 PM PDT 24
Peak memory 217840 kb
Host smart-176ea448-97c4-4083-9a01-eda39977d02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050780959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2050780959
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3805556780
Short name T473
Test name
Test status
Simulation time 780038494 ps
CPU time 23.09 seconds
Started Jul 24 06:58:48 PM PDT 24
Finished Jul 24 06:59:11 PM PDT 24
Peak memory 246484 kb
Host smart-3440cb95-63ff-45f4-93e1-c3deccaf2ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805556780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3805556780
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3625635974
Short name T81
Test name
Test status
Simulation time 227538854 ps
CPU time 10.42 seconds
Started Jul 24 06:58:44 PM PDT 24
Finished Jul 24 06:58:54 PM PDT 24
Peak memory 250980 kb
Host smart-526e3147-4453-4f2e-be66-e5bda7fa02a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625635974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3625635974
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1942873771
Short name T308
Test name
Test status
Simulation time 5507116196 ps
CPU time 196.93 seconds
Started Jul 24 06:58:52 PM PDT 24
Finished Jul 24 07:02:09 PM PDT 24
Peak memory 268420 kb
Host smart-b14e0d78-322e-4a6e-9901-736c1ddb9b34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942873771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1942873771
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.992401482
Short name T778
Test name
Test status
Simulation time 20368929 ps
CPU time 1.28 seconds
Started Jul 24 06:58:45 PM PDT 24
Finished Jul 24 06:58:46 PM PDT 24
Peak memory 217812 kb
Host smart-54f87ea9-6666-41ea-b0a4-6a0723b69dd3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992401482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.992401482
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.275511880
Short name T256
Test name
Test status
Simulation time 49384519 ps
CPU time 0.85 seconds
Started Jul 24 06:58:57 PM PDT 24
Finished Jul 24 06:58:58 PM PDT 24
Peak memory 208904 kb
Host smart-6e83c008-3e84-4e8c-a461-5a9ab2be1220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275511880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.275511880
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2517556432
Short name T408
Test name
Test status
Simulation time 993296117 ps
CPU time 10.59 seconds
Started Jul 24 06:58:55 PM PDT 24
Finished Jul 24 06:59:06 PM PDT 24
Peak memory 226164 kb
Host smart-12408fd6-443e-4a00-bd89-381cd936e610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517556432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2517556432
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1142898019
Short name T594
Test name
Test status
Simulation time 416124474 ps
CPU time 3.24 seconds
Started Jul 24 06:58:51 PM PDT 24
Finished Jul 24 06:58:55 PM PDT 24
Peak memory 217344 kb
Host smart-115efce6-cdda-41e0-8438-ddc3a5dd5960
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142898019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1142898019
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1000093136
Short name T567
Test name
Test status
Simulation time 9481524817 ps
CPU time 34.75 seconds
Started Jul 24 06:58:54 PM PDT 24
Finished Jul 24 06:59:29 PM PDT 24
Peak memory 218992 kb
Host smart-212248b5-4438-4de9-a029-ea2f834c17e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000093136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1000093136
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1062749776
Short name T540
Test name
Test status
Simulation time 1328491166 ps
CPU time 8.28 seconds
Started Jul 24 06:58:54 PM PDT 24
Finished Jul 24 06:59:03 PM PDT 24
Peak memory 218320 kb
Host smart-bbfe3e2b-0d90-4260-87e9-34c49fec2110
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062749776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1062749776
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2877600566
Short name T368
Test name
Test status
Simulation time 2567781713 ps
CPU time 16.28 seconds
Started Jul 24 06:58:50 PM PDT 24
Finished Jul 24 06:59:06 PM PDT 24
Peak memory 217748 kb
Host smart-e155e6e4-9bf9-41c5-853c-d8f8209d21f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877600566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2877600566
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3620307747
Short name T589
Test name
Test status
Simulation time 5881839855 ps
CPU time 65.11 seconds
Started Jul 24 06:58:55 PM PDT 24
Finished Jul 24 07:00:00 PM PDT 24
Peak memory 268936 kb
Host smart-1fafca91-8afa-4c69-adfa-0fd4b58bca70
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620307747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3620307747
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2981613605
Short name T738
Test name
Test status
Simulation time 730267589 ps
CPU time 24.68 seconds
Started Jul 24 06:58:52 PM PDT 24
Finished Jul 24 06:59:17 PM PDT 24
Peak memory 250500 kb
Host smart-0f3e54f7-c86b-44df-b33d-e65862d4d649
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981613605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2981613605
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1917587937
Short name T453
Test name
Test status
Simulation time 33000298 ps
CPU time 1.77 seconds
Started Jul 24 06:58:51 PM PDT 24
Finished Jul 24 06:58:53 PM PDT 24
Peak memory 222168 kb
Host smart-7a7ddd22-0cc2-416c-976c-6746d5a02f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917587937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1917587937
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.696668116
Short name T604
Test name
Test status
Simulation time 2585384901 ps
CPU time 17.46 seconds
Started Jul 24 06:58:54 PM PDT 24
Finished Jul 24 06:59:11 PM PDT 24
Peak memory 219452 kb
Host smart-8dfd641a-d423-4611-b922-570b27a1e657
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696668116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.696668116
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3970576577
Short name T403
Test name
Test status
Simulation time 8702690633 ps
CPU time 12.11 seconds
Started Jul 24 06:58:49 PM PDT 24
Finished Jul 24 06:59:02 PM PDT 24
Peak memory 226152 kb
Host smart-d21d5db7-c66c-454c-a66a-317e395a5753
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970576577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3970576577
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.21631073
Short name T806
Test name
Test status
Simulation time 1203807568 ps
CPU time 7.93 seconds
Started Jul 24 06:58:51 PM PDT 24
Finished Jul 24 06:58:59 PM PDT 24
Peak memory 226104 kb
Host smart-ff444b0e-d9fd-4cf9-b71f-ad7e4e89956e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21631073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.21631073
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3771047031
Short name T506
Test name
Test status
Simulation time 253498723 ps
CPU time 7.37 seconds
Started Jul 24 06:58:53 PM PDT 24
Finished Jul 24 06:59:00 PM PDT 24
Peak memory 218404 kb
Host smart-94083fe6-ce64-43b5-a92a-3df15163cd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771047031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3771047031
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2022065589
Short name T209
Test name
Test status
Simulation time 106134614 ps
CPU time 1.83 seconds
Started Jul 24 06:58:51 PM PDT 24
Finished Jul 24 06:58:53 PM PDT 24
Peak memory 213988 kb
Host smart-1e12ebdb-783b-4955-a44f-84c8a2cf6b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022065589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2022065589
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3656042900
Short name T215
Test name
Test status
Simulation time 1085894342 ps
CPU time 27.56 seconds
Started Jul 24 06:58:50 PM PDT 24
Finished Jul 24 06:59:18 PM PDT 24
Peak memory 250920 kb
Host smart-98c5d275-d6e1-4b50-a33f-fe3675cd0b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656042900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3656042900
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.135750572
Short name T336
Test name
Test status
Simulation time 227532041 ps
CPU time 6.97 seconds
Started Jul 24 06:58:50 PM PDT 24
Finished Jul 24 06:58:57 PM PDT 24
Peak memory 246728 kb
Host smart-e38d1e3a-b13b-4d42-bc54-003bf7a884ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135750572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.135750572
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.1779490672
Short name T241
Test name
Test status
Simulation time 140096865351 ps
CPU time 233.48 seconds
Started Jul 24 06:59:00 PM PDT 24
Finished Jul 24 07:02:54 PM PDT 24
Peak memory 269612 kb
Host smart-d58ad04c-ee2e-4b75-b2a6-10a93b08fab9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779490672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.1779490672
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3637061315
Short name T425
Test name
Test status
Simulation time 140495146 ps
CPU time 0.79 seconds
Started Jul 24 06:58:55 PM PDT 24
Finished Jul 24 06:58:56 PM PDT 24
Peak memory 209184 kb
Host smart-2d9ca47a-9500-4218-825b-054494c89b12
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637061315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3637061315
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.994552837
Short name T321
Test name
Test status
Simulation time 52060114 ps
CPU time 0.97 seconds
Started Jul 24 06:59:04 PM PDT 24
Finished Jul 24 06:59:05 PM PDT 24
Peak memory 209056 kb
Host smart-82599a75-14dc-4f12-9daa-d53b937bdda3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994552837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.994552837
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2922341766
Short name T401
Test name
Test status
Simulation time 418082896 ps
CPU time 18.85 seconds
Started Jul 24 06:58:58 PM PDT 24
Finished Jul 24 06:59:17 PM PDT 24
Peak memory 226176 kb
Host smart-36b48841-c82f-4ca1-8e8d-735328fa81d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922341766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2922341766
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1112663122
Short name T754
Test name
Test status
Simulation time 488922515 ps
CPU time 2.55 seconds
Started Jul 24 06:59:05 PM PDT 24
Finished Jul 24 06:59:08 PM PDT 24
Peak memory 217788 kb
Host smart-6e6473be-dc57-489e-a8d2-86f289c3b8e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112663122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1112663122
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2522791899
Short name T532
Test name
Test status
Simulation time 1851457167 ps
CPU time 51.68 seconds
Started Jul 24 06:59:05 PM PDT 24
Finished Jul 24 06:59:56 PM PDT 24
Peak memory 218296 kb
Host smart-cdf8d5c2-2fdf-427d-b3e5-c00e8c96f16e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522791899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2522791899
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2499004806
Short name T210
Test name
Test status
Simulation time 1207140650 ps
CPU time 5.02 seconds
Started Jul 24 06:59:05 PM PDT 24
Finished Jul 24 06:59:10 PM PDT 24
Peak memory 218308 kb
Host smart-44e94ebe-6a0d-4b8d-995b-96b7c90a1eeb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499004806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2499004806
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3646777297
Short name T409
Test name
Test status
Simulation time 107377594 ps
CPU time 2.31 seconds
Started Jul 24 06:58:57 PM PDT 24
Finished Jul 24 06:58:59 PM PDT 24
Peak memory 217724 kb
Host smart-97dffa87-39b0-4767-bd96-d114af1b7c5d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646777297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3646777297
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2284465964
Short name T799
Test name
Test status
Simulation time 5325302319 ps
CPU time 56.18 seconds
Started Jul 24 06:58:58 PM PDT 24
Finished Jul 24 06:59:54 PM PDT 24
Peak memory 253452 kb
Host smart-008012c0-d5f1-4e4a-bec6-984d4e6c30c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284465964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2284465964
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.4156207473
Short name T267
Test name
Test status
Simulation time 5898883823 ps
CPU time 11.15 seconds
Started Jul 24 06:58:58 PM PDT 24
Finished Jul 24 06:59:10 PM PDT 24
Peak memory 246664 kb
Host smart-4f886988-350c-4381-8876-b144e2ef8ff9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156207473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.4156207473
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.4120091011
Short name T775
Test name
Test status
Simulation time 69433013 ps
CPU time 3.33 seconds
Started Jul 24 06:59:06 PM PDT 24
Finished Jul 24 06:59:10 PM PDT 24
Peak memory 218296 kb
Host smart-ad46fec9-4697-404d-a112-5462097d7d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120091011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.4120091011
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.3189281995
Short name T787
Test name
Test status
Simulation time 762207206 ps
CPU time 11.3 seconds
Started Jul 24 06:59:04 PM PDT 24
Finished Jul 24 06:59:16 PM PDT 24
Peak memory 226164 kb
Host smart-83fdc68b-709c-4f81-8dae-5a144529ee7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189281995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3189281995
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1245234166
Short name T420
Test name
Test status
Simulation time 514200832 ps
CPU time 11.76 seconds
Started Jul 24 06:59:04 PM PDT 24
Finished Jul 24 06:59:16 PM PDT 24
Peak memory 226044 kb
Host smart-3755a3cc-e274-470a-86cc-324389ce094c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245234166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1245234166
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3929400134
Short name T272
Test name
Test status
Simulation time 233792493 ps
CPU time 10.03 seconds
Started Jul 24 06:59:06 PM PDT 24
Finished Jul 24 06:59:16 PM PDT 24
Peak memory 218304 kb
Host smart-7517e0d7-0707-49c0-8ba5-2faf285c92b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929400134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3929400134
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3456475519
Short name T777
Test name
Test status
Simulation time 592436967 ps
CPU time 11.56 seconds
Started Jul 24 06:58:57 PM PDT 24
Finished Jul 24 06:59:09 PM PDT 24
Peak memory 225596 kb
Host smart-e81a3c6e-0ffc-4554-a05e-337b535cae2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456475519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3456475519
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.897040667
Short name T555
Test name
Test status
Simulation time 34497399 ps
CPU time 1.9 seconds
Started Jul 24 06:59:02 PM PDT 24
Finished Jul 24 06:59:04 PM PDT 24
Peak memory 214244 kb
Host smart-2a801e06-ecb7-4aa4-a564-c104b4afda0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897040667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.897040667
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2893430840
Short name T795
Test name
Test status
Simulation time 398028729 ps
CPU time 25.39 seconds
Started Jul 24 06:58:57 PM PDT 24
Finished Jul 24 06:59:23 PM PDT 24
Peak memory 250960 kb
Host smart-3e251356-7921-4d1f-9a1d-8d435ac15c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893430840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2893430840
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2381616320
Short name T677
Test name
Test status
Simulation time 473585949 ps
CPU time 10.65 seconds
Started Jul 24 06:58:57 PM PDT 24
Finished Jul 24 06:59:08 PM PDT 24
Peak memory 250944 kb
Host smart-b20f7ab3-798f-4883-997f-ba70b14ebd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381616320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2381616320
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2694247821
Short name T461
Test name
Test status
Simulation time 9039714782 ps
CPU time 23.54 seconds
Started Jul 24 06:59:05 PM PDT 24
Finished Jul 24 06:59:28 PM PDT 24
Peak memory 242804 kb
Host smart-78e768ca-e50e-465d-87a2-1f38fe086e2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694247821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2694247821
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2801544888
Short name T83
Test name
Test status
Simulation time 14465888 ps
CPU time 1.13 seconds
Started Jul 24 06:58:57 PM PDT 24
Finished Jul 24 06:58:58 PM PDT 24
Peak memory 212064 kb
Host smart-8f845a2e-66df-4186-915f-257bb0fb7c2a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801544888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.2801544888
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2791725912
Short name T405
Test name
Test status
Simulation time 21848052 ps
CPU time 0.92 seconds
Started Jul 24 06:59:13 PM PDT 24
Finished Jul 24 06:59:14 PM PDT 24
Peak memory 208904 kb
Host smart-2731f1e9-13f7-4d18-a846-bf6d0deeeaff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791725912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2791725912
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2522624932
Short name T670
Test name
Test status
Simulation time 2763854207 ps
CPU time 16.95 seconds
Started Jul 24 06:59:07 PM PDT 24
Finished Jul 24 06:59:24 PM PDT 24
Peak memory 226200 kb
Host smart-06879f3a-cc6e-47c7-93b4-736b7845a5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522624932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2522624932
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1555588766
Short name T765
Test name
Test status
Simulation time 57492520 ps
CPU time 1.35 seconds
Started Jul 24 06:59:06 PM PDT 24
Finished Jul 24 06:59:08 PM PDT 24
Peak memory 217752 kb
Host smart-da1040b6-2862-4737-882b-e09c36d2137f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555588766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1555588766
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1012601489
Short name T680
Test name
Test status
Simulation time 3904278461 ps
CPU time 40.17 seconds
Started Jul 24 06:59:06 PM PDT 24
Finished Jul 24 06:59:46 PM PDT 24
Peak memory 218988 kb
Host smart-cd222536-3870-4124-bc03-912860f3a16f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012601489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1012601489
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2896692416
Short name T23
Test name
Test status
Simulation time 686252434 ps
CPU time 11.73 seconds
Started Jul 24 06:59:05 PM PDT 24
Finished Jul 24 06:59:17 PM PDT 24
Peak memory 218356 kb
Host smart-de0be2ba-8b42-4c97-8f8b-f5ba9a181580
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896692416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2896692416
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2190124927
Short name T217
Test name
Test status
Simulation time 644200772 ps
CPU time 4.19 seconds
Started Jul 24 06:59:05 PM PDT 24
Finished Jul 24 06:59:09 PM PDT 24
Peak memory 217664 kb
Host smart-32a4cebf-2f5c-4f41-8a17-936e41cd70fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190124927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2190124927
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3303971978
Short name T21
Test name
Test status
Simulation time 8672070321 ps
CPU time 54.79 seconds
Started Jul 24 06:59:05 PM PDT 24
Finished Jul 24 07:00:00 PM PDT 24
Peak memory 282572 kb
Host smart-defdf819-6895-4c45-a3d7-7a2c4392ddcb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303971978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3303971978
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.158869942
Short name T216
Test name
Test status
Simulation time 1680240326 ps
CPU time 17.62 seconds
Started Jul 24 06:59:04 PM PDT 24
Finished Jul 24 06:59:22 PM PDT 24
Peak memory 246132 kb
Host smart-8a245b26-5039-4ac7-b993-5db160ebb54c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158869942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.158869942
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1027698606
Short name T498
Test name
Test status
Simulation time 46456129 ps
CPU time 1.48 seconds
Started Jul 24 06:59:05 PM PDT 24
Finished Jul 24 06:59:07 PM PDT 24
Peak memory 218332 kb
Host smart-05e37065-64c4-4579-ba91-0b40d4b7e4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027698606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1027698606
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2363974254
Short name T857
Test name
Test status
Simulation time 1294174636 ps
CPU time 9.67 seconds
Started Jul 24 06:59:05 PM PDT 24
Finished Jul 24 06:59:15 PM PDT 24
Peak memory 219060 kb
Host smart-ebd51bcf-9858-451e-9414-92db95e8b87a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363974254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2363974254
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3444354329
Short name T278
Test name
Test status
Simulation time 558895440 ps
CPU time 12.82 seconds
Started Jul 24 06:59:17 PM PDT 24
Finished Jul 24 06:59:30 PM PDT 24
Peak memory 226068 kb
Host smart-1f14519d-56b8-491d-ac4b-46f727735fb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444354329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3444354329
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2714840713
Short name T733
Test name
Test status
Simulation time 286685584 ps
CPU time 10.63 seconds
Started Jul 24 06:59:13 PM PDT 24
Finished Jul 24 06:59:24 PM PDT 24
Peak memory 226052 kb
Host smart-24e53c83-aa6c-4e4c-8952-a2f030196d61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714840713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2714840713
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1651696033
Short name T407
Test name
Test status
Simulation time 212910033 ps
CPU time 7.36 seconds
Started Jul 24 06:59:05 PM PDT 24
Finished Jul 24 06:59:13 PM PDT 24
Peak memory 218400 kb
Host smart-e88ac04c-487a-4a3c-b6f1-302e22a20271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651696033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1651696033
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.774545021
Short name T814
Test name
Test status
Simulation time 49431083 ps
CPU time 3.04 seconds
Started Jul 24 06:59:05 PM PDT 24
Finished Jul 24 06:59:08 PM PDT 24
Peak memory 217764 kb
Host smart-9666dee8-8756-4ee4-bffd-34809cab3472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774545021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.774545021
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.21294529
Short name T442
Test name
Test status
Simulation time 261040979 ps
CPU time 31.71 seconds
Started Jul 24 06:59:05 PM PDT 24
Finished Jul 24 06:59:37 PM PDT 24
Peak memory 250980 kb
Host smart-eeeac103-06d6-4dab-8a3d-0cacb27381d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21294529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.21294529
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.221120253
Short name T450
Test name
Test status
Simulation time 116978942 ps
CPU time 9.8 seconds
Started Jul 24 06:59:07 PM PDT 24
Finished Jul 24 06:59:17 PM PDT 24
Peak memory 244804 kb
Host smart-9599ad65-1c99-4af5-8e11-4266dcb51208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221120253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.221120253
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3041475871
Short name T264
Test name
Test status
Simulation time 9391693398 ps
CPU time 65.23 seconds
Started Jul 24 06:59:15 PM PDT 24
Finished Jul 24 07:00:20 PM PDT 24
Peak memory 249016 kb
Host smart-6ad04231-23ea-439d-ae6d-02b56dc1f688
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041475871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3041475871
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.3587492047
Short name T849
Test name
Test status
Simulation time 32038605876 ps
CPU time 552.08 seconds
Started Jul 24 06:59:10 PM PDT 24
Finished Jul 24 07:08:22 PM PDT 24
Peak memory 280544 kb
Host smart-166b6f9b-b3a6-4231-a8c3-7d274c49bb7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3587492047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.3587492047
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.76412314
Short name T424
Test name
Test status
Simulation time 19600228 ps
CPU time 0.9 seconds
Started Jul 24 06:59:06 PM PDT 24
Finished Jul 24 06:59:07 PM PDT 24
Peak memory 211968 kb
Host smart-17d5bc8d-3bdf-4b05-8c35-ee8060ed1e94
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76412314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_volatile_unlock_smoke.76412314
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3547039271
Short name T588
Test name
Test status
Simulation time 16677096 ps
CPU time 0.89 seconds
Started Jul 24 06:59:20 PM PDT 24
Finished Jul 24 06:59:21 PM PDT 24
Peak memory 209076 kb
Host smart-6f9b54e1-08d7-459d-b651-7a9e6468bdcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547039271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3547039271
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.908455072
Short name T14
Test name
Test status
Simulation time 256051759 ps
CPU time 10.53 seconds
Started Jul 24 06:59:11 PM PDT 24
Finished Jul 24 06:59:22 PM PDT 24
Peak memory 226124 kb
Host smart-29994dbb-d05a-40a2-8511-0dab52e08101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908455072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.908455072
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2682183735
Short name T26
Test name
Test status
Simulation time 575839148 ps
CPU time 14.88 seconds
Started Jul 24 06:59:17 PM PDT 24
Finished Jul 24 06:59:32 PM PDT 24
Peak memory 217400 kb
Host smart-551a572f-6e8e-408c-abb7-6804a8311491
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682183735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2682183735
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3801026596
Short name T246
Test name
Test status
Simulation time 1277786227 ps
CPU time 42.06 seconds
Started Jul 24 06:59:13 PM PDT 24
Finished Jul 24 06:59:55 PM PDT 24
Peak memory 218376 kb
Host smart-26fbc548-cf4e-499d-a0dd-babd2edf130e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801026596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3801026596
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3115060739
Short name T355
Test name
Test status
Simulation time 223819786 ps
CPU time 2.75 seconds
Started Jul 24 06:59:17 PM PDT 24
Finished Jul 24 06:59:20 PM PDT 24
Peak memory 218400 kb
Host smart-af494b37-c570-4c15-9c31-419671e8ba87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115060739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3115060739
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.729550960
Short name T525
Test name
Test status
Simulation time 637993762 ps
CPU time 4.9 seconds
Started Jul 24 06:59:12 PM PDT 24
Finished Jul 24 06:59:17 PM PDT 24
Peak memory 217696 kb
Host smart-4b6532b4-f558-4cd0-8b80-ff3c0f0796ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729550960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
729550960
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2762647873
Short name T386
Test name
Test status
Simulation time 6940450051 ps
CPU time 63.17 seconds
Started Jul 24 06:59:14 PM PDT 24
Finished Jul 24 07:00:18 PM PDT 24
Peak memory 267360 kb
Host smart-64723ff9-0049-45f1-8ad2-0732c4a18fdb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762647873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2762647873
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.3636180333
Short name T430
Test name
Test status
Simulation time 566361306 ps
CPU time 10.14 seconds
Started Jul 24 06:59:12 PM PDT 24
Finished Jul 24 06:59:22 PM PDT 24
Peak memory 218292 kb
Host smart-6678782b-c304-4c04-b0cd-918c6f12c1b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636180333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.3636180333
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.4262337134
Short name T575
Test name
Test status
Simulation time 243114073 ps
CPU time 2.59 seconds
Started Jul 24 06:59:16 PM PDT 24
Finished Jul 24 06:59:19 PM PDT 24
Peak memory 218320 kb
Host smart-c681eda9-77b2-49ac-8a5c-8fcafb84d226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262337134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.4262337134
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.3378388534
Short name T690
Test name
Test status
Simulation time 857744882 ps
CPU time 9.21 seconds
Started Jul 24 06:59:14 PM PDT 24
Finished Jul 24 06:59:23 PM PDT 24
Peak memory 218348 kb
Host smart-41891db0-0213-4786-ad56-125fdeac9f51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378388534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3378388534
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2239868186
Short name T620
Test name
Test status
Simulation time 411036981 ps
CPU time 7.68 seconds
Started Jul 24 06:59:17 PM PDT 24
Finished Jul 24 06:59:25 PM PDT 24
Peak memory 226068 kb
Host smart-12670a59-9914-4653-b2db-227f78cb6032
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239868186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2239868186
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1993004632
Short name T363
Test name
Test status
Simulation time 276127231 ps
CPU time 7.63 seconds
Started Jul 24 06:59:12 PM PDT 24
Finished Jul 24 06:59:20 PM PDT 24
Peak memory 218308 kb
Host smart-b8c99607-3117-4660-be2f-858375c926bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993004632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1993004632
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1845315534
Short name T687
Test name
Test status
Simulation time 246157354 ps
CPU time 8.19 seconds
Started Jul 24 06:59:13 PM PDT 24
Finished Jul 24 06:59:21 PM PDT 24
Peak memory 218324 kb
Host smart-8246151e-9666-4cb8-a11c-b72db4627e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845315534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1845315534
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1285391537
Short name T659
Test name
Test status
Simulation time 87310258 ps
CPU time 2.89 seconds
Started Jul 24 06:59:16 PM PDT 24
Finished Jul 24 06:59:19 PM PDT 24
Peak memory 217748 kb
Host smart-6ffd858c-deb2-4a68-b7d0-05bc80356d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285391537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1285391537
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.567478164
Short name T440
Test name
Test status
Simulation time 1504649209 ps
CPU time 29.29 seconds
Started Jul 24 06:59:12 PM PDT 24
Finished Jul 24 06:59:41 PM PDT 24
Peak memory 248284 kb
Host smart-2d0c545f-2c3d-4ef8-96f6-12b5671cad88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567478164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.567478164
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2304645708
Short name T416
Test name
Test status
Simulation time 64211588 ps
CPU time 7.7 seconds
Started Jul 24 06:59:10 PM PDT 24
Finished Jul 24 06:59:18 PM PDT 24
Peak memory 250956 kb
Host smart-5af94e55-2157-42e8-a7e1-81062188b69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304645708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2304645708
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2611198679
Short name T533
Test name
Test status
Simulation time 2099746864 ps
CPU time 56.28 seconds
Started Jul 24 06:59:18 PM PDT 24
Finished Jul 24 07:00:15 PM PDT 24
Peak memory 217816 kb
Host smart-c710765b-e5de-410a-83e9-8e209aeb6030
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611198679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2611198679
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.2435583187
Short name T674
Test name
Test status
Simulation time 40054936476 ps
CPU time 190.53 seconds
Started Jul 24 06:59:19 PM PDT 24
Finished Jul 24 07:02:30 PM PDT 24
Peak memory 283896 kb
Host smart-b01e513c-c2e0-44f2-afcb-e955c9c63921
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2435583187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.2435583187
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3340035853
Short name T753
Test name
Test status
Simulation time 11797283 ps
CPU time 1.07 seconds
Started Jul 24 06:59:11 PM PDT 24
Finished Jul 24 06:59:12 PM PDT 24
Peak memory 211972 kb
Host smart-f64632f7-d585-4dc6-8f45-52177e866176
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340035853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3340035853
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.4250677319
Short name T842
Test name
Test status
Simulation time 38935976 ps
CPU time 0.94 seconds
Started Jul 24 06:59:20 PM PDT 24
Finished Jul 24 06:59:22 PM PDT 24
Peak memory 209008 kb
Host smart-e53b6347-7c6a-4973-825c-76ab30a8ce84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250677319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.4250677319
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.915933410
Short name T422
Test name
Test status
Simulation time 1408426040 ps
CPU time 11.69 seconds
Started Jul 24 06:59:21 PM PDT 24
Finished Jul 24 06:59:33 PM PDT 24
Peak memory 218348 kb
Host smart-e25bb111-936d-4b6b-8865-1ee8741509c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915933410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.915933410
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3716460601
Short name T801
Test name
Test status
Simulation time 1189927651 ps
CPU time 11.19 seconds
Started Jul 24 06:59:19 PM PDT 24
Finished Jul 24 06:59:30 PM PDT 24
Peak memory 217456 kb
Host smart-86525fcc-e73e-4b91-a458-ee98e9b354c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716460601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3716460601
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.4011220009
Short name T523
Test name
Test status
Simulation time 11166496993 ps
CPU time 31.69 seconds
Started Jul 24 06:59:20 PM PDT 24
Finished Jul 24 06:59:52 PM PDT 24
Peak memory 219048 kb
Host smart-7f662cb0-cca8-4736-9b74-a977976e9873
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011220009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.4011220009
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1159851773
Short name T837
Test name
Test status
Simulation time 258784957 ps
CPU time 3.35 seconds
Started Jul 24 06:59:22 PM PDT 24
Finished Jul 24 06:59:26 PM PDT 24
Peak memory 218200 kb
Host smart-976f063e-9d2f-4d62-84cc-bee09cc63417
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159851773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.1159851773
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1917786649
Short name T550
Test name
Test status
Simulation time 431908637 ps
CPU time 2.33 seconds
Started Jul 24 06:59:21 PM PDT 24
Finished Jul 24 06:59:24 PM PDT 24
Peak memory 217688 kb
Host smart-c0f87611-ebdc-4e85-aefa-5c5b412d7297
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917786649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1917786649
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1007407054
Short name T672
Test name
Test status
Simulation time 9397564876 ps
CPU time 54.25 seconds
Started Jul 24 06:59:19 PM PDT 24
Finished Jul 24 07:00:13 PM PDT 24
Peak memory 281596 kb
Host smart-5fc30fa1-21b8-41a7-8759-2a609df558d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007407054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1007407054
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1053779823
Short name T497
Test name
Test status
Simulation time 1174270036 ps
CPU time 11.09 seconds
Started Jul 24 06:59:23 PM PDT 24
Finished Jul 24 06:59:35 PM PDT 24
Peak memory 223064 kb
Host smart-54dbc66c-fda9-4a43-90d9-c80bb59c6f31
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053779823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1053779823
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2376436443
Short name T417
Test name
Test status
Simulation time 191766588 ps
CPU time 2.88 seconds
Started Jul 24 06:59:20 PM PDT 24
Finished Jul 24 06:59:23 PM PDT 24
Peak memory 218324 kb
Host smart-b551add2-b0d2-4aa8-a206-49a316286fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376436443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2376436443
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.4251689636
Short name T552
Test name
Test status
Simulation time 1130435006 ps
CPU time 13.86 seconds
Started Jul 24 06:59:20 PM PDT 24
Finished Jul 24 06:59:34 PM PDT 24
Peak memory 226144 kb
Host smart-01f7efff-a5fa-499d-b29d-5a5d55f8e3cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251689636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.4251689636
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3234842151
Short name T557
Test name
Test status
Simulation time 1244030111 ps
CPU time 12.29 seconds
Started Jul 24 06:59:19 PM PDT 24
Finished Jul 24 06:59:31 PM PDT 24
Peak memory 226104 kb
Host smart-82430c77-d0b8-476a-b0a8-c3d78d1d1c73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234842151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3234842151
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3773336566
Short name T11
Test name
Test status
Simulation time 408713133 ps
CPU time 8.16 seconds
Started Jul 24 06:59:22 PM PDT 24
Finished Jul 24 06:59:30 PM PDT 24
Peak memory 226096 kb
Host smart-3b0446be-e33f-4036-878a-c7f28d8f37f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773336566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3773336566
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2119461190
Short name T435
Test name
Test status
Simulation time 346441307 ps
CPU time 12.36 seconds
Started Jul 24 06:59:21 PM PDT 24
Finished Jul 24 06:59:33 PM PDT 24
Peak memory 218444 kb
Host smart-4d1d11f4-ce65-49a2-955c-3e222f42f051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119461190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2119461190
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2986953482
Short name T511
Test name
Test status
Simulation time 76869181 ps
CPU time 3.22 seconds
Started Jul 24 06:59:19 PM PDT 24
Finished Jul 24 06:59:22 PM PDT 24
Peak memory 215084 kb
Host smart-64475ca1-7788-4b61-b907-b1f18589d69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986953482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2986953482
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3491469724
Short name T861
Test name
Test status
Simulation time 198941837 ps
CPU time 22.67 seconds
Started Jul 24 06:59:20 PM PDT 24
Finished Jul 24 06:59:43 PM PDT 24
Peak memory 251136 kb
Host smart-8fddfef0-93c6-4133-9867-3daaf3c2f539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491469724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3491469724
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2509512398
Short name T748
Test name
Test status
Simulation time 744940171 ps
CPU time 4.33 seconds
Started Jul 24 06:59:20 PM PDT 24
Finished Jul 24 06:59:24 PM PDT 24
Peak memory 222932 kb
Host smart-f3ab82c5-cc2a-461e-a4ed-bf57786a57b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509512398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2509512398
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3206383215
Short name T184
Test name
Test status
Simulation time 2941068332 ps
CPU time 105.96 seconds
Started Jul 24 06:59:19 PM PDT 24
Finished Jul 24 07:01:06 PM PDT 24
Peak memory 269856 kb
Host smart-cd9325a9-6699-4afd-b041-38b6511b527e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206383215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3206383215
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.2993446898
Short name T96
Test name
Test status
Simulation time 69782298017 ps
CPU time 565.84 seconds
Started Jul 24 06:59:19 PM PDT 24
Finished Jul 24 07:08:45 PM PDT 24
Peak memory 333096 kb
Host smart-40dedebe-ce2c-4f15-b50c-1f37aadc91de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2993446898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.2993446898
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3001382651
Short name T38
Test name
Test status
Simulation time 14987573 ps
CPU time 1.21 seconds
Started Jul 24 06:59:18 PM PDT 24
Finished Jul 24 06:59:20 PM PDT 24
Peak memory 212004 kb
Host smart-5122d54b-94b9-4b9c-912b-2a406da69e05
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001382651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3001382651
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.102530871
Short name T481
Test name
Test status
Simulation time 36771176 ps
CPU time 0.89 seconds
Started Jul 24 06:59:29 PM PDT 24
Finished Jul 24 06:59:30 PM PDT 24
Peak memory 208968 kb
Host smart-95104b3f-6d1e-42e0-b03d-aa7ead94359a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102530871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.102530871
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.437466964
Short name T548
Test name
Test status
Simulation time 811180645 ps
CPU time 16.72 seconds
Started Jul 24 06:59:27 PM PDT 24
Finished Jul 24 06:59:44 PM PDT 24
Peak memory 218260 kb
Host smart-36bbfb40-5b3d-446d-86b8-e0c2f02d6f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437466964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.437466964
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.820796654
Short name T780
Test name
Test status
Simulation time 1137344493 ps
CPU time 7.87 seconds
Started Jul 24 06:59:25 PM PDT 24
Finished Jul 24 06:59:33 PM PDT 24
Peak memory 217768 kb
Host smart-f9c77ebb-bbc4-445e-b048-0853e37b7853
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820796654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.820796654
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2915620424
Short name T631
Test name
Test status
Simulation time 1212185161 ps
CPU time 41.35 seconds
Started Jul 24 06:59:27 PM PDT 24
Finished Jul 24 07:00:09 PM PDT 24
Peak memory 218280 kb
Host smart-54cadba6-8593-4ffd-9acc-50107a9039a7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915620424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2915620424
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3256187342
Short name T609
Test name
Test status
Simulation time 315849283 ps
CPU time 7.3 seconds
Started Jul 24 06:59:27 PM PDT 24
Finished Jul 24 06:59:35 PM PDT 24
Peak memory 218304 kb
Host smart-4f971caa-bb05-44d0-92c2-48207033adcd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256187342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3256187342
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.980652882
Short name T438
Test name
Test status
Simulation time 48657445 ps
CPU time 1.39 seconds
Started Jul 24 06:59:28 PM PDT 24
Finished Jul 24 06:59:30 PM PDT 24
Peak memory 217712 kb
Host smart-28506d08-4115-44e5-bf5e-8bd37fc6bf19
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980652882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
980652882
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3724213049
Short name T334
Test name
Test status
Simulation time 9470281082 ps
CPU time 78.61 seconds
Started Jul 24 06:59:28 PM PDT 24
Finished Jul 24 07:00:47 PM PDT 24
Peak memory 280680 kb
Host smart-dfa1c4da-5dbb-40fa-af86-d0b60b4497cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724213049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3724213049
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3069337796
Short name T18
Test name
Test status
Simulation time 358132536 ps
CPU time 12.47 seconds
Started Jul 24 06:59:29 PM PDT 24
Finished Jul 24 06:59:41 PM PDT 24
Peak memory 250892 kb
Host smart-b145ab3a-5035-46ef-952a-3fd874cabef0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069337796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3069337796
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2917559540
Short name T439
Test name
Test status
Simulation time 47478706 ps
CPU time 2.99 seconds
Started Jul 24 06:59:28 PM PDT 24
Finished Jul 24 06:59:31 PM PDT 24
Peak memory 218320 kb
Host smart-5be48116-22b0-4ec3-a230-cb6c7e5cb85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917559540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2917559540
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1156105207
Short name T688
Test name
Test status
Simulation time 330462544 ps
CPU time 14.34 seconds
Started Jul 24 06:59:29 PM PDT 24
Finished Jul 24 06:59:43 PM PDT 24
Peak memory 226116 kb
Host smart-bcd988f1-7bc1-46ad-8fe3-0f7d2f608b76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156105207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1156105207
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.377792168
Short name T560
Test name
Test status
Simulation time 308756736 ps
CPU time 12.51 seconds
Started Jul 24 06:59:25 PM PDT 24
Finished Jul 24 06:59:38 PM PDT 24
Peak memory 226064 kb
Host smart-14272a6a-0710-473b-bca9-3ed8d24827b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377792168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.377792168
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2293007941
Short name T512
Test name
Test status
Simulation time 2259115975 ps
CPU time 20.27 seconds
Started Jul 24 06:59:26 PM PDT 24
Finished Jul 24 06:59:46 PM PDT 24
Peak memory 226132 kb
Host smart-cca1cdad-cb03-4326-89b5-1a370a7a9b0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293007941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2293007941
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1594289303
Short name T456
Test name
Test status
Simulation time 1364728269 ps
CPU time 7.81 seconds
Started Jul 24 06:59:26 PM PDT 24
Finished Jul 24 06:59:34 PM PDT 24
Peak memory 218424 kb
Host smart-8892c9f0-6ff9-4ce7-9220-e0ffa31702b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594289303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1594289303
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3610026039
Short name T650
Test name
Test status
Simulation time 351880277 ps
CPU time 3.19 seconds
Started Jul 24 06:59:20 PM PDT 24
Finished Jul 24 06:59:23 PM PDT 24
Peak memory 215188 kb
Host smart-7cdeadc3-9913-469a-8614-78177c403a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610026039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3610026039
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3525745471
Short name T360
Test name
Test status
Simulation time 348772454 ps
CPU time 26.22 seconds
Started Jul 24 06:59:26 PM PDT 24
Finished Jul 24 06:59:53 PM PDT 24
Peak memory 251000 kb
Host smart-5b135a39-bd56-4367-9390-b80da1d7ad36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525745471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3525745471
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.383671992
Short name T200
Test name
Test status
Simulation time 204358751 ps
CPU time 7.91 seconds
Started Jul 24 06:59:26 PM PDT 24
Finished Jul 24 06:59:34 PM PDT 24
Peak memory 250980 kb
Host smart-edae3414-b704-4ad4-91e2-ba6eab32d112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383671992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.383671992
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2035895586
Short name T67
Test name
Test status
Simulation time 17103595518 ps
CPU time 333.39 seconds
Started Jul 24 06:59:27 PM PDT 24
Finished Jul 24 07:05:00 PM PDT 24
Peak memory 275620 kb
Host smart-9299b6c1-ea5d-44a8-9907-ab85a6a55bf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035895586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2035895586
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3602610979
Short name T51
Test name
Test status
Simulation time 61300908 ps
CPU time 1 seconds
Started Jul 24 06:59:21 PM PDT 24
Finished Jul 24 06:59:22 PM PDT 24
Peak memory 217804 kb
Host smart-7e6ec12b-8fe3-4645-9540-98bc19bdd1bf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602610979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3602610979
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.781206881
Short name T343
Test name
Test status
Simulation time 829814086 ps
CPU time 1.67 seconds
Started Jul 24 06:59:33 PM PDT 24
Finished Jul 24 06:59:35 PM PDT 24
Peak memory 217764 kb
Host smart-00abcbd3-9bc7-4d61-b61a-5748db4dc236
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781206881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.781206881
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1598519671
Short name T817
Test name
Test status
Simulation time 1894437364 ps
CPU time 54.43 seconds
Started Jul 24 06:59:37 PM PDT 24
Finished Jul 24 07:00:32 PM PDT 24
Peak memory 218232 kb
Host smart-701a36f4-e53c-4838-8826-088858b45937
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598519671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1598519671
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3328805949
Short name T433
Test name
Test status
Simulation time 290304076 ps
CPU time 9.28 seconds
Started Jul 24 06:59:34 PM PDT 24
Finished Jul 24 06:59:43 PM PDT 24
Peak memory 223144 kb
Host smart-ce32bfae-9b64-4e2a-a267-c929017f1fb2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328805949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3328805949
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.4176943044
Short name T468
Test name
Test status
Simulation time 413014830 ps
CPU time 3.5 seconds
Started Jul 24 06:59:37 PM PDT 24
Finished Jul 24 06:59:40 PM PDT 24
Peak memory 217648 kb
Host smart-f4dab165-3a02-43d2-8830-b18512c3de1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176943044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.4176943044
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.584101430
Short name T752
Test name
Test status
Simulation time 7480021356 ps
CPU time 41.36 seconds
Started Jul 24 06:59:36 PM PDT 24
Finished Jul 24 07:00:18 PM PDT 24
Peak memory 268224 kb
Host smart-6b7e62da-5a90-448f-a80f-2d38296ebee3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584101430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.584101430
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.186912418
Short name T844
Test name
Test status
Simulation time 556286208 ps
CPU time 13.31 seconds
Started Jul 24 06:59:31 PM PDT 24
Finished Jul 24 06:59:44 PM PDT 24
Peak memory 250928 kb
Host smart-b73a08dc-9577-42a6-aa4a-80eebb1da41e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186912418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.186912418
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1697869098
Short name T297
Test name
Test status
Simulation time 314171839 ps
CPU time 2.89 seconds
Started Jul 24 06:59:29 PM PDT 24
Finished Jul 24 06:59:32 PM PDT 24
Peak memory 218320 kb
Host smart-43acddc3-ab89-4298-998d-9c4f5296ad89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697869098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1697869098
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1196978036
Short name T502
Test name
Test status
Simulation time 444142110 ps
CPU time 18.34 seconds
Started Jul 24 06:59:37 PM PDT 24
Finished Jul 24 06:59:56 PM PDT 24
Peak memory 226084 kb
Host smart-7ed6be19-b0bf-4751-8b5e-3b5cb9ad9fc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196978036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1196978036
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3660762145
Short name T338
Test name
Test status
Simulation time 247655096 ps
CPU time 9.82 seconds
Started Jul 24 06:59:34 PM PDT 24
Finished Jul 24 06:59:44 PM PDT 24
Peak memory 226072 kb
Host smart-b2a84e67-f3a4-4343-9e0c-0bb71b60a953
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660762145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3660762145
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2741958532
Short name T255
Test name
Test status
Simulation time 565741517 ps
CPU time 8.45 seconds
Started Jul 24 06:59:31 PM PDT 24
Finished Jul 24 06:59:40 PM PDT 24
Peak memory 218284 kb
Host smart-ae2233f9-bd6d-4985-9539-db5f2fc3d6e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741958532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2741958532
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3798148573
Short name T586
Test name
Test status
Simulation time 1082106738 ps
CPU time 7.38 seconds
Started Jul 24 06:59:34 PM PDT 24
Finished Jul 24 06:59:41 PM PDT 24
Peak memory 218376 kb
Host smart-3094df71-0b66-4a54-8781-9143ec416b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798148573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3798148573
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2196904014
Short name T314
Test name
Test status
Simulation time 55140811 ps
CPU time 3.16 seconds
Started Jul 24 06:59:25 PM PDT 24
Finished Jul 24 06:59:28 PM PDT 24
Peak memory 214976 kb
Host smart-7b81ca42-70ef-4e01-aa97-ebb359953fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196904014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2196904014
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.147589690
Short name T741
Test name
Test status
Simulation time 618546460 ps
CPU time 20.54 seconds
Started Jul 24 06:59:26 PM PDT 24
Finished Jul 24 06:59:47 PM PDT 24
Peak memory 251056 kb
Host smart-ffa9350a-3fcd-4ac2-8382-8df0e0755bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147589690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.147589690
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3322395190
Short name T862
Test name
Test status
Simulation time 136967083 ps
CPU time 5.96 seconds
Started Jul 24 06:59:27 PM PDT 24
Finished Jul 24 06:59:33 PM PDT 24
Peak memory 222940 kb
Host smart-6b767618-a421-4501-86f1-b77825275e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322395190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3322395190
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3446560604
Short name T284
Test name
Test status
Simulation time 11431013106 ps
CPU time 78.9 seconds
Started Jul 24 06:59:31 PM PDT 24
Finished Jul 24 07:00:50 PM PDT 24
Peak memory 267568 kb
Host smart-22edec99-9016-41fd-99cb-4c553101c65f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446560604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3446560604
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.1030988923
Short name T142
Test name
Test status
Simulation time 20290575926 ps
CPU time 421.15 seconds
Started Jul 24 06:59:32 PM PDT 24
Finished Jul 24 07:06:34 PM PDT 24
Peak memory 291888 kb
Host smart-2c95c7a8-2a72-4fa6-bc70-09f0bfe333a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1030988923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.1030988923
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1482683152
Short name T393
Test name
Test status
Simulation time 11876816 ps
CPU time 0.91 seconds
Started Jul 24 06:59:26 PM PDT 24
Finished Jul 24 06:59:27 PM PDT 24
Peak memory 209020 kb
Host smart-3a1e9ce4-398e-4276-b27b-99a71ce6c993
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482683152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1482683152
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2250949644
Short name T262
Test name
Test status
Simulation time 78362403 ps
CPU time 0.96 seconds
Started Jul 24 06:59:37 PM PDT 24
Finished Jul 24 06:59:38 PM PDT 24
Peak memory 209008 kb
Host smart-7667d31a-7bc0-46c0-ba3a-16380b13c531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250949644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2250949644
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.15995808
Short name T322
Test name
Test status
Simulation time 2524281700 ps
CPU time 18.23 seconds
Started Jul 24 06:59:33 PM PDT 24
Finished Jul 24 06:59:51 PM PDT 24
Peak memory 218408 kb
Host smart-137720b8-558c-4561-9e5b-101177eedacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15995808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.15995808
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2538623404
Short name T9
Test name
Test status
Simulation time 1135367255 ps
CPU time 24.23 seconds
Started Jul 24 06:59:39 PM PDT 24
Finished Jul 24 07:00:03 PM PDT 24
Peak memory 217416 kb
Host smart-9b61bb70-1935-46ff-be01-a90e3661f57b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538623404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2538623404
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.83106292
Short name T389
Test name
Test status
Simulation time 1926384093 ps
CPU time 56.62 seconds
Started Jul 24 06:59:39 PM PDT 24
Finished Jul 24 07:00:35 PM PDT 24
Peak memory 218904 kb
Host smart-a090996d-7f64-4a6b-9a29-b240cfcc8ca8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83106292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_err
ors.83106292
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.381711432
Short name T415
Test name
Test status
Simulation time 250268220 ps
CPU time 8.3 seconds
Started Jul 24 06:59:39 PM PDT 24
Finished Jul 24 06:59:48 PM PDT 24
Peak memory 223460 kb
Host smart-f8150e37-a7c8-4122-8ae5-82c9365d9c1a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381711432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.381711432
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2261070196
Short name T86
Test name
Test status
Simulation time 183616422 ps
CPU time 6 seconds
Started Jul 24 06:59:32 PM PDT 24
Finished Jul 24 06:59:38 PM PDT 24
Peak memory 217692 kb
Host smart-70937a8b-e596-4349-8f94-2e62712ec4e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261070196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2261070196
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.4084133537
Short name T265
Test name
Test status
Simulation time 1352330052 ps
CPU time 55.87 seconds
Started Jul 24 06:59:32 PM PDT 24
Finished Jul 24 07:00:28 PM PDT 24
Peak memory 250924 kb
Host smart-ab43f7c8-a030-4b91-8f1c-699f032ee096
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084133537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.4084133537
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2384185487
Short name T712
Test name
Test status
Simulation time 444194353 ps
CPU time 7.53 seconds
Started Jul 24 06:59:40 PM PDT 24
Finished Jul 24 06:59:48 PM PDT 24
Peak memory 221992 kb
Host smart-8f1b85f9-d702-4a8d-81e4-26f98e898559
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384185487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2384185487
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2460531498
Short name T487
Test name
Test status
Simulation time 1631033133 ps
CPU time 2.91 seconds
Started Jul 24 06:59:32 PM PDT 24
Finished Jul 24 06:59:35 PM PDT 24
Peak memory 218336 kb
Host smart-e1e30749-67bc-41e8-ab52-9debbf147f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460531498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2460531498
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3983691356
Short name T227
Test name
Test status
Simulation time 1622346779 ps
CPU time 15.72 seconds
Started Jul 24 06:59:37 PM PDT 24
Finished Jul 24 06:59:53 PM PDT 24
Peak memory 218480 kb
Host smart-7dff01e5-cf43-46c2-ab93-f00f0f0d5a37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983691356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3983691356
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3044760757
Short name T591
Test name
Test status
Simulation time 3635989462 ps
CPU time 17.46 seconds
Started Jul 24 06:59:37 PM PDT 24
Finished Jul 24 06:59:55 PM PDT 24
Peak memory 226152 kb
Host smart-f07c011c-582e-48b3-a437-f9c534593857
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044760757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3044760757
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.4284602761
Short name T311
Test name
Test status
Simulation time 1285310073 ps
CPU time 8.44 seconds
Started Jul 24 06:59:38 PM PDT 24
Finished Jul 24 06:59:47 PM PDT 24
Peak memory 218328 kb
Host smart-fe5f471b-335b-4d64-a084-3cbf4bc9dfa9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284602761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
4284602761
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1226917020
Short name T723
Test name
Test status
Simulation time 235540064 ps
CPU time 7.87 seconds
Started Jul 24 06:59:32 PM PDT 24
Finished Jul 24 06:59:40 PM PDT 24
Peak memory 218436 kb
Host smart-a8d5864a-71d7-4097-9989-eb010bd68a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226917020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1226917020
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2284645658
Short name T668
Test name
Test status
Simulation time 36654787 ps
CPU time 1.17 seconds
Started Jul 24 06:59:37 PM PDT 24
Finished Jul 24 06:59:38 PM PDT 24
Peak memory 217696 kb
Host smart-d13be31c-afe3-4bd4-a0c7-fe2530f14856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284645658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2284645658
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1895418199
Short name T526
Test name
Test status
Simulation time 230624713 ps
CPU time 27 seconds
Started Jul 24 06:59:32 PM PDT 24
Finished Jul 24 06:59:59 PM PDT 24
Peak memory 251128 kb
Host smart-c38ca695-eee6-42fb-9f37-dbf00fa1c1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895418199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1895418199
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2904960293
Short name T220
Test name
Test status
Simulation time 287405951 ps
CPU time 6.58 seconds
Started Jul 24 06:59:31 PM PDT 24
Finished Jul 24 06:59:38 PM PDT 24
Peak memory 247128 kb
Host smart-02098946-bbe5-40a2-a56e-f1b2afe56259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904960293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2904960293
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3303125717
Short name T870
Test name
Test status
Simulation time 23947954954 ps
CPU time 191.16 seconds
Started Jul 24 06:59:43 PM PDT 24
Finished Jul 24 07:02:54 PM PDT 24
Peak memory 277016 kb
Host smart-1127e0eb-6188-47a4-b5d9-68d1e4313176
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303125717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3303125717
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3272987327
Short name T222
Test name
Test status
Simulation time 45557537 ps
CPU time 1.04 seconds
Started Jul 24 06:59:31 PM PDT 24
Finished Jul 24 06:59:33 PM PDT 24
Peak memory 211996 kb
Host smart-a03a432e-47f9-47c9-b27d-659fb299ad8a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272987327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3272987327
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.62789627
Short name T856
Test name
Test status
Simulation time 12487934 ps
CPU time 1.02 seconds
Started Jul 24 06:59:46 PM PDT 24
Finished Jul 24 06:59:47 PM PDT 24
Peak memory 209192 kb
Host smart-39759968-4652-4f35-b266-cb57f1310c68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62789627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.62789627
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3564205136
Short name T524
Test name
Test status
Simulation time 378366803 ps
CPU time 11.09 seconds
Started Jul 24 06:59:38 PM PDT 24
Finished Jul 24 06:59:49 PM PDT 24
Peak memory 218336 kb
Host smart-74323101-8d7d-40d4-a7ef-9577717390bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564205136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3564205136
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1822587146
Short name T839
Test name
Test status
Simulation time 1267855660 ps
CPU time 3.32 seconds
Started Jul 24 06:59:44 PM PDT 24
Finished Jul 24 06:59:47 PM PDT 24
Peak memory 217768 kb
Host smart-91426777-603f-4784-a570-01ca63a2008a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822587146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1822587146
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2927475956
Short name T54
Test name
Test status
Simulation time 9021063732 ps
CPU time 35.01 seconds
Started Jul 24 06:59:45 PM PDT 24
Finished Jul 24 07:00:20 PM PDT 24
Peak memory 218896 kb
Host smart-87f35e7b-6c18-4373-82d0-f217c0a295be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927475956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2927475956
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1265985151
Short name T237
Test name
Test status
Simulation time 1166871784 ps
CPU time 5.98 seconds
Started Jul 24 06:59:51 PM PDT 24
Finished Jul 24 06:59:57 PM PDT 24
Peak memory 223232 kb
Host smart-61916306-f2ff-45ab-8ca4-f40ffec45edf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265985151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1265985151
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.647975300
Short name T466
Test name
Test status
Simulation time 91876625 ps
CPU time 1.74 seconds
Started Jul 24 06:59:45 PM PDT 24
Finished Jul 24 06:59:47 PM PDT 24
Peak memory 217696 kb
Host smart-732f55e2-d8bc-45b2-905f-e6670fab00f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647975300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.
647975300
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3856897102
Short name T472
Test name
Test status
Simulation time 1680892926 ps
CPU time 47.74 seconds
Started Jul 24 06:59:45 PM PDT 24
Finished Jul 24 07:00:32 PM PDT 24
Peak memory 250904 kb
Host smart-38c3cfd8-7c1e-4d5f-a9e8-25ad66421305
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856897102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3856897102
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1581197300
Short name T335
Test name
Test status
Simulation time 1336494768 ps
CPU time 10.47 seconds
Started Jul 24 06:59:51 PM PDT 24
Finished Jul 24 07:00:02 PM PDT 24
Peak memory 246472 kb
Host smart-b4bd69ae-1ec3-4742-8d42-c6d570be480b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581197300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1581197300
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2300506051
Short name T329
Test name
Test status
Simulation time 248541405 ps
CPU time 3.85 seconds
Started Jul 24 06:59:39 PM PDT 24
Finished Jul 24 06:59:43 PM PDT 24
Peak memory 218344 kb
Host smart-5ab7b6a7-2957-4c42-8d39-8ea2e757fd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300506051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2300506051
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3324216861
Short name T239
Test name
Test status
Simulation time 1372951647 ps
CPU time 13.54 seconds
Started Jul 24 06:59:45 PM PDT 24
Finished Jul 24 06:59:59 PM PDT 24
Peak memory 219076 kb
Host smart-466365e4-52ba-4f05-9197-4acf2d13a914
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324216861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3324216861
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3148891126
Short name T287
Test name
Test status
Simulation time 3717538304 ps
CPU time 24.53 seconds
Started Jul 24 06:59:44 PM PDT 24
Finished Jul 24 07:00:09 PM PDT 24
Peak memory 226168 kb
Host smart-3d4e8f16-b8b2-4b03-93bd-525d3c131e20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148891126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3148891126
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.411121036
Short name T813
Test name
Test status
Simulation time 1289100019 ps
CPU time 8.05 seconds
Started Jul 24 06:59:45 PM PDT 24
Finished Jul 24 06:59:54 PM PDT 24
Peak memory 218328 kb
Host smart-4afc2339-b2e9-4789-a042-b9ab22d0abe8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411121036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.411121036
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3227016980
Short name T496
Test name
Test status
Simulation time 372246665 ps
CPU time 8.55 seconds
Started Jul 24 06:59:39 PM PDT 24
Finished Jul 24 06:59:47 PM PDT 24
Peak memory 218400 kb
Host smart-6b3799b0-b86f-49b3-858d-9da634977509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227016980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3227016980
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1468777268
Short name T679
Test name
Test status
Simulation time 1905514475 ps
CPU time 6.72 seconds
Started Jul 24 06:59:37 PM PDT 24
Finished Jul 24 06:59:44 PM PDT 24
Peak memory 217664 kb
Host smart-1f131707-cfb0-4c34-999c-63672607308a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468777268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1468777268
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3587183894
Short name T148
Test name
Test status
Simulation time 263463243 ps
CPU time 29.29 seconds
Started Jul 24 06:59:39 PM PDT 24
Finished Jul 24 07:00:09 PM PDT 24
Peak memory 250984 kb
Host smart-59cd866b-ea69-4dea-bd0b-bbea410ea05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587183894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3587183894
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3383966149
Short name T501
Test name
Test status
Simulation time 61267727 ps
CPU time 3.05 seconds
Started Jul 24 06:59:40 PM PDT 24
Finished Jul 24 06:59:43 PM PDT 24
Peak memory 222668 kb
Host smart-3866ceb4-f0a6-48ea-b1e5-9e29466ee404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383966149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3383966149
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1147242383
Short name T339
Test name
Test status
Simulation time 100546886125 ps
CPU time 204.47 seconds
Started Jul 24 06:59:43 PM PDT 24
Finished Jul 24 07:03:08 PM PDT 24
Peak memory 251032 kb
Host smart-1e96784b-c430-41c3-8243-777633613975
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147242383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1147242383
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1096697430
Short name T494
Test name
Test status
Simulation time 12462420 ps
CPU time 0.96 seconds
Started Jul 24 06:59:39 PM PDT 24
Finished Jul 24 06:59:40 PM PDT 24
Peak memory 209012 kb
Host smart-e4719a17-486a-46c0-8905-8289f6b5b801
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096697430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.1096697430
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.443486511
Short name T351
Test name
Test status
Simulation time 46678471 ps
CPU time 0.84 seconds
Started Jul 24 06:57:40 PM PDT 24
Finished Jul 24 06:57:41 PM PDT 24
Peak memory 208820 kb
Host smart-68e10c2b-c0cb-4bca-a25c-a5a8c984b6c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443486511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.443486511
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.592491026
Short name T702
Test name
Test status
Simulation time 2598858667 ps
CPU time 14.49 seconds
Started Jul 24 06:57:26 PM PDT 24
Finished Jul 24 06:57:41 PM PDT 24
Peak memory 219220 kb
Host smart-b7ae972c-9ab5-40c7-8c0a-aae705b782d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592491026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.592491026
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3025502152
Short name T29
Test name
Test status
Simulation time 178426702 ps
CPU time 5.31 seconds
Started Jul 24 06:57:34 PM PDT 24
Finished Jul 24 06:57:39 PM PDT 24
Peak memory 217304 kb
Host smart-c4d5addc-bac7-461a-b8e3-1d64909a670b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025502152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3025502152
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.421717840
Short name T601
Test name
Test status
Simulation time 1237494870 ps
CPU time 39.18 seconds
Started Jul 24 06:57:31 PM PDT 24
Finished Jul 24 06:58:10 PM PDT 24
Peak memory 218940 kb
Host smart-c6825656-3f29-4e03-be5d-1bcc227d6bd4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421717840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.421717840
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3471969750
Short name T266
Test name
Test status
Simulation time 351931745 ps
CPU time 2.08 seconds
Started Jul 24 06:57:32 PM PDT 24
Finished Jul 24 06:57:34 PM PDT 24
Peak memory 217804 kb
Host smart-bc45b17f-1737-487e-8650-cf809ebc0d83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471969750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
471969750
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.600965135
Short name T150
Test name
Test status
Simulation time 561975694 ps
CPU time 7.75 seconds
Started Jul 24 06:57:32 PM PDT 24
Finished Jul 24 06:57:40 PM PDT 24
Peak memory 224104 kb
Host smart-b9fc20cd-8b35-456c-ad11-3527f6d17543
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600965135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
prog_failure.600965135
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2620799646
Short name T234
Test name
Test status
Simulation time 869792893 ps
CPU time 13.64 seconds
Started Jul 24 06:57:32 PM PDT 24
Finished Jul 24 06:57:46 PM PDT 24
Peak memory 217692 kb
Host smart-02cde25f-00e0-4acd-85ce-f8866353c512
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620799646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2620799646
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1682183907
Short name T84
Test name
Test status
Simulation time 478828379 ps
CPU time 5.04 seconds
Started Jul 24 06:57:25 PM PDT 24
Finished Jul 24 06:57:30 PM PDT 24
Peak memory 217696 kb
Host smart-305ab04a-4cb4-424e-a3f5-3a5f6179a709
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682183907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1682183907
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3595980596
Short name T592
Test name
Test status
Simulation time 17845280329 ps
CPU time 74.27 seconds
Started Jul 24 06:57:25 PM PDT 24
Finished Jul 24 06:58:39 PM PDT 24
Peak memory 283676 kb
Host smart-3395a265-2147-4bf0-8f47-b33af413eb8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595980596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3595980596
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3402294031
Short name T447
Test name
Test status
Simulation time 2119635369 ps
CPU time 14.13 seconds
Started Jul 24 06:57:25 PM PDT 24
Finished Jul 24 06:57:39 PM PDT 24
Peak memory 250912 kb
Host smart-11dba12a-7b79-4e25-a7e9-288dcbd7ae19
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402294031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3402294031
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.401520248
Short name T612
Test name
Test status
Simulation time 267218591 ps
CPU time 2.94 seconds
Started Jul 24 06:57:25 PM PDT 24
Finished Jul 24 06:57:28 PM PDT 24
Peak memory 218324 kb
Host smart-c6a59721-ec3a-4560-8f5c-7bc095511233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401520248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.401520248
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2399772484
Short name T376
Test name
Test status
Simulation time 381347529 ps
CPU time 5.19 seconds
Started Jul 24 06:57:24 PM PDT 24
Finished Jul 24 06:57:30 PM PDT 24
Peak memory 213888 kb
Host smart-9d8360ef-37d4-4ac8-8a87-1ea05d2c7288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399772484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2399772484
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1409486470
Short name T66
Test name
Test status
Simulation time 1969468985 ps
CPU time 34.39 seconds
Started Jul 24 06:57:39 PM PDT 24
Finished Jul 24 06:58:14 PM PDT 24
Peak memory 284232 kb
Host smart-0517e173-b238-42e4-88d2-3a58818e4752
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409486470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1409486470
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2482298656
Short name T822
Test name
Test status
Simulation time 2194775498 ps
CPU time 24.08 seconds
Started Jul 24 06:57:34 PM PDT 24
Finished Jul 24 06:57:58 PM PDT 24
Peak memory 226188 kb
Host smart-563cd23d-f08a-4fc2-b77b-6b40efd4f5ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482298656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2482298656
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3434907069
Short name T770
Test name
Test status
Simulation time 2659748624 ps
CPU time 26 seconds
Started Jul 24 06:57:33 PM PDT 24
Finished Jul 24 06:57:59 PM PDT 24
Peak memory 226236 kb
Host smart-208eff62-fa7d-47d8-94f3-37eb3401c2ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434907069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3434907069
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3374040595
Short name T331
Test name
Test status
Simulation time 1579838771 ps
CPU time 9.43 seconds
Started Jul 24 06:57:33 PM PDT 24
Finished Jul 24 06:57:43 PM PDT 24
Peak memory 226072 kb
Host smart-641ecec0-8a61-4a65-9daf-86a107108515
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374040595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
374040595
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2969484112
Short name T510
Test name
Test status
Simulation time 262742303 ps
CPU time 11.12 seconds
Started Jul 24 06:57:24 PM PDT 24
Finished Jul 24 06:57:35 PM PDT 24
Peak memory 218492 kb
Host smart-60f3dfac-1b21-41c4-bf9b-1b645aad2339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969484112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2969484112
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1759122152
Short name T88
Test name
Test status
Simulation time 64695183 ps
CPU time 1.21 seconds
Started Jul 24 06:57:22 PM PDT 24
Finished Jul 24 06:57:23 PM PDT 24
Peak memory 217756 kb
Host smart-b57d7dcc-222b-48df-aeef-c93f8dc13980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759122152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1759122152
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3650468205
Short name T72
Test name
Test status
Simulation time 1199929661 ps
CPU time 24.25 seconds
Started Jul 24 06:57:19 PM PDT 24
Finished Jul 24 06:57:44 PM PDT 24
Peak memory 251000 kb
Host smart-34c620d1-b94e-4fe3-8932-b39b8158e36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650468205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3650468205
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3470577677
Short name T400
Test name
Test status
Simulation time 387547146 ps
CPU time 3.63 seconds
Started Jul 24 06:57:23 PM PDT 24
Finished Jul 24 06:57:27 PM PDT 24
Peak memory 226416 kb
Host smart-607d4b37-a5d3-4b24-bde4-11a8b4cb41eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470577677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3470577677
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3786424058
Short name T649
Test name
Test status
Simulation time 21510980 ps
CPU time 1.07 seconds
Started Jul 24 06:57:18 PM PDT 24
Finished Jul 24 06:57:19 PM PDT 24
Peak memory 217788 kb
Host smart-2fb6e028-2801-47cb-a053-db20c4891fd5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786424058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3786424058
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1152140260
Short name T291
Test name
Test status
Simulation time 67072160 ps
CPU time 0.94 seconds
Started Jul 24 06:59:51 PM PDT 24
Finished Jul 24 06:59:52 PM PDT 24
Peak memory 208952 kb
Host smart-ecb37d26-6d3b-4999-a9ce-5be753832472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152140260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1152140260
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3634503290
Short name T639
Test name
Test status
Simulation time 3874593733 ps
CPU time 25.75 seconds
Started Jul 24 06:59:51 PM PDT 24
Finished Jul 24 07:00:17 PM PDT 24
Peak memory 219020 kb
Host smart-77e05ac3-93e9-4cc9-a010-7a5d958ec314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634503290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3634503290
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.889637699
Short name T6
Test name
Test status
Simulation time 299932442 ps
CPU time 4.3 seconds
Started Jul 24 06:59:45 PM PDT 24
Finished Jul 24 06:59:50 PM PDT 24
Peak memory 217748 kb
Host smart-fcc2d53c-5887-4d23-aceb-ae31252d9550
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889637699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.889637699
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2899268202
Short name T273
Test name
Test status
Simulation time 71426318 ps
CPU time 3.03 seconds
Started Jul 24 06:59:45 PM PDT 24
Finished Jul 24 06:59:48 PM PDT 24
Peak memory 218340 kb
Host smart-73c89bc5-b0d2-442d-9d88-895af68ab4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899268202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2899268202
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3359367049
Short name T205
Test name
Test status
Simulation time 1165423774 ps
CPU time 9.97 seconds
Started Jul 24 06:59:44 PM PDT 24
Finished Jul 24 06:59:54 PM PDT 24
Peak memory 218572 kb
Host smart-8f2afbe5-21e7-43a3-a80a-fdc174d68042
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359367049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3359367049
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3752367075
Short name T304
Test name
Test status
Simulation time 202746890 ps
CPU time 9.69 seconds
Started Jul 24 06:59:46 PM PDT 24
Finished Jul 24 06:59:56 PM PDT 24
Peak memory 226044 kb
Host smart-79a47748-8632-4996-940c-257e0b0b2788
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752367075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3752367075
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2466115631
Short name T544
Test name
Test status
Simulation time 2132499041 ps
CPU time 16.66 seconds
Started Jul 24 06:59:47 PM PDT 24
Finished Jul 24 07:00:04 PM PDT 24
Peak memory 218284 kb
Host smart-04508c5c-bd91-438a-ac3d-cacf95813364
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466115631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2466115631
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1913583957
Short name T527
Test name
Test status
Simulation time 707408499 ps
CPU time 12.32 seconds
Started Jul 24 06:59:51 PM PDT 24
Finished Jul 24 07:00:03 PM PDT 24
Peak memory 218372 kb
Host smart-71810a3c-0f02-49ed-934f-572cc94f3e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913583957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1913583957
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2131833731
Short name T75
Test name
Test status
Simulation time 217761088 ps
CPU time 3.14 seconds
Started Jul 24 06:59:45 PM PDT 24
Finished Jul 24 06:59:49 PM PDT 24
Peak memory 214896 kb
Host smart-5678f006-1e11-41cd-ac63-47c30194a999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131833731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2131833731
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.818304674
Short name T785
Test name
Test status
Simulation time 2199459639 ps
CPU time 25.19 seconds
Started Jul 24 06:59:47 PM PDT 24
Finished Jul 24 07:00:12 PM PDT 24
Peak memory 247552 kb
Host smart-7cfcb2e2-a288-4ec3-a84b-334bd84bdd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818304674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.818304674
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.3332484508
Short name T830
Test name
Test status
Simulation time 584697036 ps
CPU time 9.2 seconds
Started Jul 24 06:59:46 PM PDT 24
Finished Jul 24 06:59:55 PM PDT 24
Peak memory 243812 kb
Host smart-d946a76c-f042-46f8-9b2d-e3d4fa3dfd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332484508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3332484508
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3124724876
Short name T653
Test name
Test status
Simulation time 1497964919 ps
CPU time 81.05 seconds
Started Jul 24 06:59:50 PM PDT 24
Finished Jul 24 07:01:12 PM PDT 24
Peak memory 267328 kb
Host smart-cd74e492-6886-403b-aa1b-083acd849002
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124724876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3124724876
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3292733874
Short name T744
Test name
Test status
Simulation time 12019162 ps
CPU time 0.93 seconds
Started Jul 24 06:59:49 PM PDT 24
Finished Jul 24 06:59:50 PM PDT 24
Peak memory 208704 kb
Host smart-063aba7c-d2b7-47fe-ac6f-908f2c6777fc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292733874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3292733874
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.4040157393
Short name T818
Test name
Test status
Simulation time 35027139 ps
CPU time 0.97 seconds
Started Jul 24 06:59:57 PM PDT 24
Finished Jul 24 06:59:58 PM PDT 24
Peak memory 209068 kb
Host smart-b95bd823-29cd-4b01-a916-8cd216738a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040157393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.4040157393
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1274163487
Short name T55
Test name
Test status
Simulation time 878845545 ps
CPU time 13.63 seconds
Started Jul 24 06:59:55 PM PDT 24
Finished Jul 24 07:00:09 PM PDT 24
Peak memory 218308 kb
Host smart-41ccfe12-6ecb-43b0-b1ec-7036ddc2fd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274163487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1274163487
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3236559397
Short name T779
Test name
Test status
Simulation time 589981724 ps
CPU time 2.51 seconds
Started Jul 24 06:59:52 PM PDT 24
Finished Jul 24 06:59:54 PM PDT 24
Peak memory 217172 kb
Host smart-fb59678d-b042-4152-8f74-326f7cb2b66b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236559397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3236559397
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3015301595
Short name T530
Test name
Test status
Simulation time 56682130 ps
CPU time 2.78 seconds
Started Jul 24 06:59:50 PM PDT 24
Finished Jul 24 06:59:53 PM PDT 24
Peak memory 222608 kb
Host smart-9d9575c5-d573-4775-8db9-cb434d31526c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015301595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3015301595
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3141257867
Short name T48
Test name
Test status
Simulation time 1601767425 ps
CPU time 13.32 seconds
Started Jul 24 06:59:53 PM PDT 24
Finished Jul 24 07:00:06 PM PDT 24
Peak memory 219060 kb
Host smart-d9173452-a81a-4bbc-9df5-883685181bb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141257867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3141257867
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2355236029
Short name T790
Test name
Test status
Simulation time 765529739 ps
CPU time 17.43 seconds
Started Jul 24 06:59:58 PM PDT 24
Finished Jul 24 07:00:15 PM PDT 24
Peak memory 226064 kb
Host smart-e498e0dc-d46d-4d36-b03e-ecf1d9e06104
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355236029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2355236029
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3707405523
Short name T379
Test name
Test status
Simulation time 199153453 ps
CPU time 8.17 seconds
Started Jul 24 06:59:51 PM PDT 24
Finished Jul 24 06:59:59 PM PDT 24
Peak memory 218292 kb
Host smart-e308ef91-45be-48ae-afad-260042e4ab62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707405523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3707405523
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1470826568
Short name T676
Test name
Test status
Simulation time 347817194 ps
CPU time 12.7 seconds
Started Jul 24 06:59:54 PM PDT 24
Finished Jul 24 07:00:07 PM PDT 24
Peak memory 218368 kb
Host smart-3d9017e2-08dd-4944-9c19-2f45fb7b923a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470826568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1470826568
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3704497980
Short name T705
Test name
Test status
Simulation time 77758964 ps
CPU time 1.8 seconds
Started Jul 24 06:59:51 PM PDT 24
Finished Jul 24 06:59:53 PM PDT 24
Peak memory 217812 kb
Host smart-c3925400-87d6-443a-a872-1ca287f3fc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704497980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3704497980
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.4002786105
Short name T428
Test name
Test status
Simulation time 770441104 ps
CPU time 17.96 seconds
Started Jul 24 06:59:50 PM PDT 24
Finished Jul 24 07:00:08 PM PDT 24
Peak memory 250920 kb
Host smart-47f9a9ae-4b0c-4e9e-920f-22a780da9070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002786105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.4002786105
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.581323741
Short name T666
Test name
Test status
Simulation time 294749323 ps
CPU time 3.2 seconds
Started Jul 24 06:59:53 PM PDT 24
Finished Jul 24 06:59:56 PM PDT 24
Peak memory 222396 kb
Host smart-a2573d3b-cc00-4089-a824-d7d700b7146c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581323741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.581323741
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1681718419
Short name T281
Test name
Test status
Simulation time 1238761187 ps
CPU time 65.05 seconds
Started Jul 24 06:59:58 PM PDT 24
Finished Jul 24 07:01:04 PM PDT 24
Peak memory 267560 kb
Host smart-31e828fa-3d61-48b5-9d59-506255c37680
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681718419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1681718419
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.122916136
Short name T138
Test name
Test status
Simulation time 69789546973 ps
CPU time 682.42 seconds
Started Jul 24 07:00:00 PM PDT 24
Finished Jul 24 07:11:22 PM PDT 24
Peak memory 299104 kb
Host smart-103a36d7-20c0-4c56-aad9-9675367e5651
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=122916136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.122916136
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.140632595
Short name T665
Test name
Test status
Simulation time 13437729 ps
CPU time 0.96 seconds
Started Jul 24 06:59:53 PM PDT 24
Finished Jul 24 06:59:54 PM PDT 24
Peak memory 211996 kb
Host smart-4b94127d-6698-464c-b6e5-432083ee10c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140632595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.140632595
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.4015068055
Short name T250
Test name
Test status
Simulation time 129826584 ps
CPU time 0.88 seconds
Started Jul 24 07:00:05 PM PDT 24
Finished Jul 24 07:00:09 PM PDT 24
Peak memory 208864 kb
Host smart-20c6db8a-ff89-43cd-bdb0-67c7135b89a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015068055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.4015068055
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2788809747
Short name T211
Test name
Test status
Simulation time 1420842986 ps
CPU time 13.28 seconds
Started Jul 24 06:59:57 PM PDT 24
Finished Jul 24 07:00:11 PM PDT 24
Peak memory 218280 kb
Host smart-c18c42d1-1e7c-40a1-93a2-324cf9b24a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788809747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2788809747
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1726412878
Short name T384
Test name
Test status
Simulation time 957308336 ps
CPU time 21.22 seconds
Started Jul 24 06:59:58 PM PDT 24
Finished Jul 24 07:00:20 PM PDT 24
Peak memory 217864 kb
Host smart-005d5c38-546c-480d-9bfc-da7d19515774
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726412878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1726412878
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3747503032
Short name T536
Test name
Test status
Simulation time 315600390 ps
CPU time 3.02 seconds
Started Jul 24 06:59:57 PM PDT 24
Finished Jul 24 07:00:00 PM PDT 24
Peak memory 218284 kb
Host smart-25c486dd-992a-4026-8a40-e630e41c7be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747503032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3747503032
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.160095433
Short name T359
Test name
Test status
Simulation time 1225913495 ps
CPU time 8.66 seconds
Started Jul 24 07:00:01 PM PDT 24
Finished Jul 24 07:00:16 PM PDT 24
Peak memory 218532 kb
Host smart-326852e0-216e-4f08-b276-063d62bf1e35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160095433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.160095433
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.136608884
Short name T332
Test name
Test status
Simulation time 2527262007 ps
CPU time 11.52 seconds
Started Jul 24 07:00:00 PM PDT 24
Finished Jul 24 07:00:11 PM PDT 24
Peak memory 226124 kb
Host smart-cac5382b-aeaa-4dbc-90f5-92bc5308e957
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136608884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.136608884
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2398157818
Short name T247
Test name
Test status
Simulation time 930178901 ps
CPU time 19.9 seconds
Started Jul 24 07:00:01 PM PDT 24
Finished Jul 24 07:00:27 PM PDT 24
Peak memory 226036 kb
Host smart-2f7c83f0-3920-4057-aac4-0b571fa39c81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398157818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2398157818
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.130787959
Short name T387
Test name
Test status
Simulation time 236830549 ps
CPU time 4.29 seconds
Started Jul 24 06:59:57 PM PDT 24
Finished Jul 24 07:00:02 PM PDT 24
Peak memory 217792 kb
Host smart-ed31c0ee-8998-47c6-9846-4d00670dc9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130787959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.130787959
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.72021662
Short name T695
Test name
Test status
Simulation time 960015499 ps
CPU time 22.18 seconds
Started Jul 24 06:59:56 PM PDT 24
Finished Jul 24 07:00:19 PM PDT 24
Peak memory 250924 kb
Host smart-eb3dcaab-9b02-4bf3-993d-344b731de1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72021662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.72021662
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.4150402315
Short name T429
Test name
Test status
Simulation time 96349056 ps
CPU time 6.16 seconds
Started Jul 24 07:00:04 PM PDT 24
Finished Jul 24 07:00:14 PM PDT 24
Peak memory 247004 kb
Host smart-41b0452d-0787-4267-8f34-a54e21ed0175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150402315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.4150402315
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3687075542
Short name T288
Test name
Test status
Simulation time 7658141057 ps
CPU time 158.75 seconds
Started Jul 24 07:00:00 PM PDT 24
Finished Jul 24 07:02:39 PM PDT 24
Peak memory 316512 kb
Host smart-aa734ce8-73c5-4717-ab0d-20ed2d312082
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687075542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3687075542
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3215521437
Short name T859
Test name
Test status
Simulation time 83491362 ps
CPU time 1.13 seconds
Started Jul 24 06:59:56 PM PDT 24
Finished Jul 24 06:59:58 PM PDT 24
Peak memory 217936 kb
Host smart-406bb4b5-96eb-4c82-a80d-2202c7b815b8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215521437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3215521437
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1244488629
Short name T546
Test name
Test status
Simulation time 71575383 ps
CPU time 1.22 seconds
Started Jul 24 07:00:05 PM PDT 24
Finished Jul 24 07:00:09 PM PDT 24
Peak memory 209376 kb
Host smart-45d27b2f-b2da-4ba2-91e1-64712abefc07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244488629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1244488629
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3882267935
Short name T850
Test name
Test status
Simulation time 266136582 ps
CPU time 9.17 seconds
Started Jul 24 07:00:16 PM PDT 24
Finished Jul 24 07:00:26 PM PDT 24
Peak memory 218324 kb
Host smart-6ce368b9-f705-459f-904a-b81d338908b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882267935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3882267935
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1003994208
Short name T27
Test name
Test status
Simulation time 1576566382 ps
CPU time 4.8 seconds
Started Jul 24 07:00:06 PM PDT 24
Finished Jul 24 07:00:12 PM PDT 24
Peak memory 217748 kb
Host smart-1e2d86ba-176c-4156-888d-e67f8a9514e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003994208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1003994208
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2162338699
Short name T782
Test name
Test status
Simulation time 86036533 ps
CPU time 2.1 seconds
Started Jul 24 06:59:58 PM PDT 24
Finished Jul 24 07:00:00 PM PDT 24
Peak memory 218360 kb
Host smart-f5560169-9472-437a-9a31-bb4d7b7f5d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162338699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2162338699
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1208048412
Short name T369
Test name
Test status
Simulation time 867550315 ps
CPU time 19.08 seconds
Started Jul 24 07:00:04 PM PDT 24
Finished Jul 24 07:00:27 PM PDT 24
Peak memory 218952 kb
Host smart-c402529c-e55c-45d9-b53b-88f27398f994
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208048412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1208048412
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.4059829592
Short name T455
Test name
Test status
Simulation time 478417252 ps
CPU time 9.65 seconds
Started Jul 24 07:00:04 PM PDT 24
Finished Jul 24 07:00:17 PM PDT 24
Peak memory 226088 kb
Host smart-6e04db4a-f83a-47a0-945c-ce1867a022e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059829592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.4059829592
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.112073348
Short name T318
Test name
Test status
Simulation time 281267945 ps
CPU time 10.07 seconds
Started Jul 24 07:00:08 PM PDT 24
Finished Jul 24 07:00:19 PM PDT 24
Peak memory 218288 kb
Host smart-26ec56a7-ec8b-43a0-bf92-f448e1910229
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112073348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.112073348
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.4055415400
Short name T694
Test name
Test status
Simulation time 1567584010 ps
CPU time 9.59 seconds
Started Jul 24 07:00:06 PM PDT 24
Finished Jul 24 07:00:17 PM PDT 24
Peak memory 226140 kb
Host smart-bdb39ca7-a47d-4844-b42a-8f85f8967f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055415400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.4055415400
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.387879321
Short name T73
Test name
Test status
Simulation time 79078518 ps
CPU time 3.69 seconds
Started Jul 24 06:59:57 PM PDT 24
Finished Jul 24 07:00:01 PM PDT 24
Peak memory 217864 kb
Host smart-49ec6687-c4a6-499e-9134-2aecfe2b143f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387879321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.387879321
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.4275855049
Short name T607
Test name
Test status
Simulation time 744298245 ps
CPU time 30.82 seconds
Started Jul 24 07:00:01 PM PDT 24
Finished Jul 24 07:00:38 PM PDT 24
Peak memory 250940 kb
Host smart-278c419a-356c-4c3e-a35c-37ae6d938a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275855049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.4275855049
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.773716649
Short name T492
Test name
Test status
Simulation time 166467225 ps
CPU time 2.44 seconds
Started Jul 24 06:59:56 PM PDT 24
Finished Jul 24 06:59:58 PM PDT 24
Peak memory 226400 kb
Host smart-bace6c55-5114-4a56-825c-fa4a316bdae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773716649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.773716649
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2197289971
Short name T90
Test name
Test status
Simulation time 6026858783 ps
CPU time 64.88 seconds
Started Jul 24 07:00:05 PM PDT 24
Finished Jul 24 07:01:13 PM PDT 24
Peak memory 250864 kb
Host smart-10c8eaa4-f687-4deb-b75c-a68d877fd0dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197289971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2197289971
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3094167796
Short name T636
Test name
Test status
Simulation time 32071350 ps
CPU time 0.76 seconds
Started Jul 24 07:00:02 PM PDT 24
Finished Jul 24 07:00:08 PM PDT 24
Peak memory 208892 kb
Host smart-7acd7a22-e486-42ff-bc45-e1799916dd45
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094167796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3094167796
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3195089648
Short name T475
Test name
Test status
Simulation time 23698556 ps
CPU time 0.96 seconds
Started Jul 24 07:00:14 PM PDT 24
Finished Jul 24 07:00:15 PM PDT 24
Peak memory 209012 kb
Host smart-1ee1aa19-7c50-4500-8e93-cc6e204101d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195089648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3195089648
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3908971440
Short name T554
Test name
Test status
Simulation time 394939595 ps
CPU time 13.93 seconds
Started Jul 24 07:00:04 PM PDT 24
Finished Jul 24 07:00:21 PM PDT 24
Peak memory 218360 kb
Host smart-209ae420-a49e-4daf-bed1-b9b6c97d8419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908971440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3908971440
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1954249015
Short name T365
Test name
Test status
Simulation time 87213436 ps
CPU time 1.85 seconds
Started Jul 24 07:00:12 PM PDT 24
Finished Jul 24 07:00:14 PM PDT 24
Peak memory 217812 kb
Host smart-71af9d25-a294-4db4-8561-e59f7a9ba1bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954249015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1954249015
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3818412562
Short name T462
Test name
Test status
Simulation time 162132784 ps
CPU time 2.63 seconds
Started Jul 24 07:00:04 PM PDT 24
Finished Jul 24 07:00:10 PM PDT 24
Peak memory 218296 kb
Host smart-3897557e-14f8-4920-9d9b-f6b721dddf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818412562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3818412562
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1479943993
Short name T303
Test name
Test status
Simulation time 2129102189 ps
CPU time 12 seconds
Started Jul 24 07:00:10 PM PDT 24
Finished Jul 24 07:00:23 PM PDT 24
Peak memory 218564 kb
Host smart-c69e9e8a-4313-4707-a059-d68498a94e8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479943993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1479943993
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.4292747188
Short name T786
Test name
Test status
Simulation time 976513783 ps
CPU time 9.47 seconds
Started Jul 24 07:00:12 PM PDT 24
Finished Jul 24 07:00:22 PM PDT 24
Peak memory 226096 kb
Host smart-50871251-d9ee-4895-a496-a29783caa181
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292747188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.4292747188
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2557339612
Short name T301
Test name
Test status
Simulation time 733290841 ps
CPU time 7.29 seconds
Started Jul 24 07:00:12 PM PDT 24
Finished Jul 24 07:00:20 PM PDT 24
Peak memory 225352 kb
Host smart-491bca32-6800-4292-a905-34963e9396bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557339612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2557339612
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1538011071
Short name T63
Test name
Test status
Simulation time 234719311 ps
CPU time 8.92 seconds
Started Jul 24 07:00:15 PM PDT 24
Finished Jul 24 07:00:24 PM PDT 24
Peak memory 218416 kb
Host smart-b53ee01a-51ab-4a64-9c5b-332a4c4ac737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538011071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1538011071
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2017817541
Short name T290
Test name
Test status
Simulation time 152133499 ps
CPU time 6.3 seconds
Started Jul 24 07:00:03 PM PDT 24
Finished Jul 24 07:00:14 PM PDT 24
Peak memory 217740 kb
Host smart-d97023e4-097a-48a1-9a60-1475d93baf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017817541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2017817541
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3037117844
Short name T803
Test name
Test status
Simulation time 257969153 ps
CPU time 32.61 seconds
Started Jul 24 07:00:08 PM PDT 24
Finished Jul 24 07:00:41 PM PDT 24
Peak memory 250960 kb
Host smart-61ca98cb-7c6a-4251-bbe0-d3d9f865ec70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037117844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3037117844
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.674625736
Short name T706
Test name
Test status
Simulation time 478842698 ps
CPU time 6.82 seconds
Started Jul 24 07:00:05 PM PDT 24
Finished Jul 24 07:00:14 PM PDT 24
Peak memory 250812 kb
Host smart-49684b71-a4df-4e8a-828b-99f50bef18d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674625736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.674625736
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2526133406
Short name T808
Test name
Test status
Simulation time 14682039527 ps
CPU time 140.42 seconds
Started Jul 24 07:00:12 PM PDT 24
Finished Jul 24 07:02:33 PM PDT 24
Peak memory 267348 kb
Host smart-edb9c3dd-db63-4bbc-8cda-78525f0475f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526133406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2526133406
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1879210162
Short name T342
Test name
Test status
Simulation time 24166392 ps
CPU time 0.81 seconds
Started Jul 24 07:00:07 PM PDT 24
Finished Jul 24 07:00:09 PM PDT 24
Peak memory 208988 kb
Host smart-2cc3fc34-2ba7-4dfe-bec6-db4b09edf89d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879210162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1879210162
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.771359931
Short name T207
Test name
Test status
Simulation time 16706199 ps
CPU time 1.11 seconds
Started Jul 24 07:00:12 PM PDT 24
Finished Jul 24 07:00:14 PM PDT 24
Peak memory 208988 kb
Host smart-197c7655-38ba-4e04-87ce-207405f3a48c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771359931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.771359931
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2142357
Short name T700
Test name
Test status
Simulation time 2737114206 ps
CPU time 10.11 seconds
Started Jul 24 07:00:12 PM PDT 24
Finished Jul 24 07:00:22 PM PDT 24
Peak memory 219108 kb
Host smart-f1a4a129-f245-4079-b0d5-a815cb3e30df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2142357
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2864051248
Short name T28
Test name
Test status
Simulation time 1722353387 ps
CPU time 10.56 seconds
Started Jul 24 07:00:10 PM PDT 24
Finished Jul 24 07:00:21 PM PDT 24
Peak memory 217760 kb
Host smart-ce389ae1-fdbc-4ebc-9207-e7d4967f76fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864051248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2864051248
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.64455599
Short name T385
Test name
Test status
Simulation time 53063529 ps
CPU time 2.86 seconds
Started Jul 24 07:00:13 PM PDT 24
Finished Jul 24 07:00:16 PM PDT 24
Peak memory 218268 kb
Host smart-1ac84410-5ffb-48ef-9505-13005663002b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64455599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.64455599
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.130446734
Short name T486
Test name
Test status
Simulation time 235593537 ps
CPU time 10.54 seconds
Started Jul 24 07:00:11 PM PDT 24
Finished Jul 24 07:00:21 PM PDT 24
Peak memory 219000 kb
Host smart-bd62e402-27ea-494a-a62a-5b5cbd487f4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130446734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.130446734
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.4192634923
Short name T242
Test name
Test status
Simulation time 1404481321 ps
CPU time 10.02 seconds
Started Jul 24 07:00:14 PM PDT 24
Finished Jul 24 07:00:24 PM PDT 24
Peak memory 226104 kb
Host smart-e8be7017-cca3-4ed9-93cd-c413874b1903
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192634923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.4192634923
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.4167675006
Short name T434
Test name
Test status
Simulation time 663763427 ps
CPU time 10.03 seconds
Started Jul 24 07:00:15 PM PDT 24
Finished Jul 24 07:00:25 PM PDT 24
Peak memory 225992 kb
Host smart-7c19a1d2-0fbd-4fbc-a458-85f8048d5fbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167675006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
4167675006
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2774218012
Short name T59
Test name
Test status
Simulation time 518420489 ps
CPU time 8.59 seconds
Started Jul 24 07:00:16 PM PDT 24
Finished Jul 24 07:00:25 PM PDT 24
Peak memory 226136 kb
Host smart-5836c9f9-f33f-4e3e-98d2-63ccc6a5ad0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774218012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2774218012
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.530576119
Short name T78
Test name
Test status
Simulation time 53756864 ps
CPU time 1.22 seconds
Started Jul 24 07:00:16 PM PDT 24
Finished Jul 24 07:00:17 PM PDT 24
Peak memory 217752 kb
Host smart-8f09a26f-0b38-4d63-b808-b999a277fc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530576119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.530576119
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2882457212
Short name T528
Test name
Test status
Simulation time 230881586 ps
CPU time 24.68 seconds
Started Jul 24 07:00:15 PM PDT 24
Finished Jul 24 07:00:40 PM PDT 24
Peak memory 250964 kb
Host smart-1137216a-faf5-4420-ab70-b0e24a018385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882457212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2882457212
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.2275451926
Short name T149
Test name
Test status
Simulation time 80236888 ps
CPU time 8.83 seconds
Started Jul 24 07:00:14 PM PDT 24
Finished Jul 24 07:00:23 PM PDT 24
Peak memory 251004 kb
Host smart-ae2917ae-ee84-4095-acf4-76ffdda437af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275451926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2275451926
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1606149585
Short name T531
Test name
Test status
Simulation time 19111641296 ps
CPU time 213.2 seconds
Started Jul 24 07:00:16 PM PDT 24
Finished Jul 24 07:03:49 PM PDT 24
Peak memory 421944 kb
Host smart-6da093ad-6600-4df9-9493-d349fb969a83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606149585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1606149585
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2073963164
Short name T871
Test name
Test status
Simulation time 30409868 ps
CPU time 1.01 seconds
Started Jul 24 07:00:12 PM PDT 24
Finished Jul 24 07:00:13 PM PDT 24
Peak memory 211960 kb
Host smart-e0c2da43-0f8d-4e1f-b399-600402d87880
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073963164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2073963164
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.3155639655
Short name T792
Test name
Test status
Simulation time 16537055 ps
CPU time 0.9 seconds
Started Jul 24 07:00:16 PM PDT 24
Finished Jul 24 07:00:18 PM PDT 24
Peak memory 208968 kb
Host smart-0e949892-9db5-4d12-8a21-fe459a194cd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155639655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3155639655
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2546795703
Short name T298
Test name
Test status
Simulation time 1291349275 ps
CPU time 13.23 seconds
Started Jul 24 07:00:14 PM PDT 24
Finished Jul 24 07:00:28 PM PDT 24
Peak memory 218260 kb
Host smart-09ef3cb4-a045-43c1-a1b7-1fa10e60f00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546795703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2546795703
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1381434662
Short name T826
Test name
Test status
Simulation time 1108011634 ps
CPU time 7.24 seconds
Started Jul 24 07:00:12 PM PDT 24
Finished Jul 24 07:00:19 PM PDT 24
Peak memory 217724 kb
Host smart-ef4a0f0d-075a-4259-a688-9ec53d78b222
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381434662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1381434662
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3242538319
Short name T823
Test name
Test status
Simulation time 73597297 ps
CPU time 3.21 seconds
Started Jul 24 07:00:13 PM PDT 24
Finished Jul 24 07:00:16 PM PDT 24
Peak memory 218316 kb
Host smart-666d9d08-437b-4e6f-91c0-d92605821d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242538319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3242538319
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3258698226
Short name T728
Test name
Test status
Simulation time 1386125884 ps
CPU time 14.48 seconds
Started Jul 24 07:00:12 PM PDT 24
Finished Jul 24 07:00:27 PM PDT 24
Peak memory 226152 kb
Host smart-bb0b6522-0731-4777-9453-e32db74ea39e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258698226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3258698226
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3677324746
Short name T12
Test name
Test status
Simulation time 982814028 ps
CPU time 10.85 seconds
Started Jul 24 07:00:18 PM PDT 24
Finished Jul 24 07:00:29 PM PDT 24
Peak memory 226068 kb
Host smart-f0e3f6fb-ad1a-4611-978b-de0651db62c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677324746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3677324746
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3579899232
Short name T729
Test name
Test status
Simulation time 413409882 ps
CPU time 9.67 seconds
Started Jul 24 07:00:19 PM PDT 24
Finished Jul 24 07:00:29 PM PDT 24
Peak memory 218280 kb
Host smart-1190320c-c8b0-438a-8053-a24c952b3662
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579899232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3579899232
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.775746632
Short name T835
Test name
Test status
Simulation time 330716947 ps
CPU time 7.98 seconds
Started Jul 24 07:00:15 PM PDT 24
Finished Jul 24 07:00:23 PM PDT 24
Peak memory 218280 kb
Host smart-1355b91a-6a76-48bd-8170-4537cba4074d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775746632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.775746632
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2100222719
Short name T224
Test name
Test status
Simulation time 27206744 ps
CPU time 1.54 seconds
Started Jul 24 07:00:13 PM PDT 24
Finished Jul 24 07:00:15 PM PDT 24
Peak memory 214060 kb
Host smart-742e20d0-b575-4cad-b97a-9e3223f8eec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100222719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2100222719
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.759011985
Short name T214
Test name
Test status
Simulation time 2523293032 ps
CPU time 23.2 seconds
Started Jul 24 07:00:14 PM PDT 24
Finished Jul 24 07:00:37 PM PDT 24
Peak memory 251052 kb
Host smart-2076f3ec-7fb4-4dcd-ba8e-8ffecfc6085a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759011985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.759011985
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1600803219
Short name T353
Test name
Test status
Simulation time 91291822 ps
CPU time 7.96 seconds
Started Jul 24 07:00:14 PM PDT 24
Finished Jul 24 07:00:22 PM PDT 24
Peak memory 250824 kb
Host smart-9d3f3402-fba4-4733-875d-275e1845927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600803219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1600803219
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1785993908
Short name T490
Test name
Test status
Simulation time 10733932506 ps
CPU time 96.36 seconds
Started Jul 24 07:00:18 PM PDT 24
Finished Jul 24 07:01:55 PM PDT 24
Peak memory 250648 kb
Host smart-76953f6c-ff27-4233-820a-6f4a61c584e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785993908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1785993908
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2859193651
Short name T648
Test name
Test status
Simulation time 12998791 ps
CPU time 0.85 seconds
Started Jul 24 07:00:15 PM PDT 24
Finished Jul 24 07:00:16 PM PDT 24
Peak memory 209012 kb
Host smart-4277b0b7-63ed-4fd1-9af1-d855a87c75b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859193651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2859193651
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.1120098076
Short name T251
Test name
Test status
Simulation time 19670359 ps
CPU time 1.17 seconds
Started Jul 24 07:00:18 PM PDT 24
Finished Jul 24 07:00:19 PM PDT 24
Peak memory 209032 kb
Host smart-b5ab2891-18b0-4c0e-9c5c-6e7b16f53c6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120098076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1120098076
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3488459852
Short name T774
Test name
Test status
Simulation time 462368475 ps
CPU time 17.93 seconds
Started Jul 24 07:00:20 PM PDT 24
Finished Jul 24 07:00:38 PM PDT 24
Peak memory 218352 kb
Host smart-b49e1b71-a371-417b-847d-d87eaae813ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488459852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3488459852
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.3071755731
Short name T583
Test name
Test status
Simulation time 4237754590 ps
CPU time 25.16 seconds
Started Jul 24 07:00:20 PM PDT 24
Finished Jul 24 07:00:45 PM PDT 24
Peak memory 217856 kb
Host smart-b8746521-10de-420d-901d-d33564472ec6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071755731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.3071755731
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.2996260962
Short name T756
Test name
Test status
Simulation time 82398056 ps
CPU time 2.59 seconds
Started Jul 24 07:00:19 PM PDT 24
Finished Jul 24 07:00:22 PM PDT 24
Peak memory 218324 kb
Host smart-9e77a5c7-20d4-4449-b4ef-cf7060e453d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996260962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2996260962
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3165563158
Short name T221
Test name
Test status
Simulation time 6650643962 ps
CPU time 13.54 seconds
Started Jul 24 07:00:18 PM PDT 24
Finished Jul 24 07:00:32 PM PDT 24
Peak memory 226116 kb
Host smart-8db06aca-21e7-49e4-bbd0-6d503efe8670
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165563158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3165563158
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.125783266
Short name T478
Test name
Test status
Simulation time 1680242981 ps
CPU time 9.38 seconds
Started Jul 24 07:00:20 PM PDT 24
Finished Jul 24 07:00:30 PM PDT 24
Peak memory 226068 kb
Host smart-235b5eb1-8a31-4958-b92d-5fdb47d9e33a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125783266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.125783266
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.173395672
Short name T751
Test name
Test status
Simulation time 510289174 ps
CPU time 8.04 seconds
Started Jul 24 07:00:20 PM PDT 24
Finished Jul 24 07:00:28 PM PDT 24
Peak memory 218232 kb
Host smart-445a70b9-3217-4081-97ff-2ab6bc40ae53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173395672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.173395672
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3794676706
Short name T545
Test name
Test status
Simulation time 307705218 ps
CPU time 12.51 seconds
Started Jul 24 07:00:18 PM PDT 24
Finished Jul 24 07:00:31 PM PDT 24
Peak memory 226160 kb
Host smart-bf155316-9d70-46d4-91ac-db0a482ecd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794676706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3794676706
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3462301816
Short name T485
Test name
Test status
Simulation time 124839404 ps
CPU time 1.78 seconds
Started Jul 24 07:00:17 PM PDT 24
Finished Jul 24 07:00:19 PM PDT 24
Peak memory 214076 kb
Host smart-843529fd-2c06-4986-9975-001e133fafa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462301816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3462301816
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2137226861
Short name T104
Test name
Test status
Simulation time 391732147 ps
CPU time 34.09 seconds
Started Jul 24 07:00:16 PM PDT 24
Finished Jul 24 07:00:51 PM PDT 24
Peak memory 251056 kb
Host smart-8492dc80-de4a-4436-bb63-20578668ae8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137226861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2137226861
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.4157560004
Short name T776
Test name
Test status
Simulation time 94735708 ps
CPU time 9 seconds
Started Jul 24 07:00:18 PM PDT 24
Finished Jul 24 07:00:28 PM PDT 24
Peak memory 242776 kb
Host smart-684b803c-44a4-459c-a5b1-332b9a68dace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157560004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.4157560004
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1560620526
Short name T43
Test name
Test status
Simulation time 31499060575 ps
CPU time 571.72 seconds
Started Jul 24 07:00:19 PM PDT 24
Finished Jul 24 07:09:51 PM PDT 24
Peak memory 267380 kb
Host smart-36c66856-745f-4f10-ac60-cc8f6bd0934c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560620526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1560620526
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.1308647209
Short name T154
Test name
Test status
Simulation time 35365350733 ps
CPU time 648.47 seconds
Started Jul 24 07:00:21 PM PDT 24
Finished Jul 24 07:11:10 PM PDT 24
Peak memory 284356 kb
Host smart-c6ea43e7-2267-4630-bf0b-4f892a1c4de7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1308647209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.1308647209
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3330264951
Short name T596
Test name
Test status
Simulation time 56354375 ps
CPU time 1.18 seconds
Started Jul 24 07:00:17 PM PDT 24
Finished Jul 24 07:00:19 PM PDT 24
Peak memory 217940 kb
Host smart-1f71cf1a-e681-43ff-9223-3d7344c62f8c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330264951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3330264951
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.323681744
Short name T151
Test name
Test status
Simulation time 63130242 ps
CPU time 1.11 seconds
Started Jul 24 07:00:26 PM PDT 24
Finished Jul 24 07:00:27 PM PDT 24
Peak memory 209112 kb
Host smart-64ce6ffe-5d92-44e9-9d98-af7168655510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323681744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.323681744
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3170705185
Short name T345
Test name
Test status
Simulation time 1081514435 ps
CPU time 8.59 seconds
Started Jul 24 07:00:38 PM PDT 24
Finished Jul 24 07:00:47 PM PDT 24
Peak memory 218308 kb
Host smart-edf5fb4c-6e92-4396-ab24-b3056e83afe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170705185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3170705185
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3684869125
Short name T710
Test name
Test status
Simulation time 1045611689 ps
CPU time 7 seconds
Started Jul 24 07:00:26 PM PDT 24
Finished Jul 24 07:00:33 PM PDT 24
Peak memory 217756 kb
Host smart-3c4a95f0-dd00-4784-a7ad-cd508e7839e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684869125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3684869125
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3258696433
Short name T223
Test name
Test status
Simulation time 51817916 ps
CPU time 2.42 seconds
Started Jul 24 07:00:18 PM PDT 24
Finished Jul 24 07:00:21 PM PDT 24
Peak memory 218276 kb
Host smart-3454e3d3-bee9-4b3e-8d1e-a7b7dbefe896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258696433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3258696433
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.188170358
Short name T228
Test name
Test status
Simulation time 1555344812 ps
CPU time 17.77 seconds
Started Jul 24 07:00:25 PM PDT 24
Finished Jul 24 07:00:43 PM PDT 24
Peak memory 226188 kb
Host smart-967bf5dc-b3c4-4e86-ac2e-110e0086f662
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188170358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.188170358
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2017452489
Short name T824
Test name
Test status
Simulation time 279975405 ps
CPU time 8.93 seconds
Started Jul 24 07:00:31 PM PDT 24
Finished Jul 24 07:00:40 PM PDT 24
Peak memory 226140 kb
Host smart-273b32be-f1e4-4aff-be57-851c9ce68d7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017452489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2017452489
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.730016287
Short name T517
Test name
Test status
Simulation time 1039709669 ps
CPU time 7.92 seconds
Started Jul 24 07:00:25 PM PDT 24
Finished Jul 24 07:00:33 PM PDT 24
Peak memory 225084 kb
Host smart-18c10791-d805-4457-ad72-577d94f5aaf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730016287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.730016287
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.988546606
Short name T697
Test name
Test status
Simulation time 1647507510 ps
CPU time 12.15 seconds
Started Jul 24 07:00:27 PM PDT 24
Finished Jul 24 07:00:39 PM PDT 24
Peak memory 218316 kb
Host smart-e22bdfaa-56e1-43a0-8cc1-3defabb4b263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988546606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.988546606
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.4004624864
Short name T529
Test name
Test status
Simulation time 15255577 ps
CPU time 1.24 seconds
Started Jul 24 07:00:21 PM PDT 24
Finished Jul 24 07:00:23 PM PDT 24
Peak memory 212072 kb
Host smart-565e6402-debc-4b08-beb2-0216ed75c9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004624864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.4004624864
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.376572439
Short name T474
Test name
Test status
Simulation time 403915581 ps
CPU time 26.05 seconds
Started Jul 24 07:00:17 PM PDT 24
Finished Jul 24 07:00:43 PM PDT 24
Peak memory 250936 kb
Host smart-dfff59b8-909d-48bb-a1d8-0d60685176d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376572439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.376572439
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1965136992
Short name T240
Test name
Test status
Simulation time 57194293 ps
CPU time 7.08 seconds
Started Jul 24 07:00:20 PM PDT 24
Finished Jul 24 07:00:27 PM PDT 24
Peak memory 246792 kb
Host smart-8fe4ce81-30f5-4863-a6ce-eaa9e6609f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965136992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1965136992
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2702856952
Short name T452
Test name
Test status
Simulation time 18841404122 ps
CPU time 326.26 seconds
Started Jul 24 07:00:28 PM PDT 24
Finished Jul 24 07:05:55 PM PDT 24
Peak memory 267328 kb
Host smart-f282a0ba-e01d-47f0-ba04-0a8453f4d711
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702856952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2702856952
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1945058322
Short name T141
Test name
Test status
Simulation time 700392833196 ps
CPU time 1492.34 seconds
Started Jul 24 07:00:26 PM PDT 24
Finished Jul 24 07:25:19 PM PDT 24
Peak memory 774788 kb
Host smart-c7c9dc53-2ee4-48e8-ac22-28acb716006e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1945058322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.1945058322
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3398387356
Short name T699
Test name
Test status
Simulation time 39292994 ps
CPU time 0.9 seconds
Started Jul 24 07:00:18 PM PDT 24
Finished Jul 24 07:00:19 PM PDT 24
Peak memory 209196 kb
Host smart-77ba8d72-2f90-4a28-b0a5-97ab12de5b3c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398387356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3398387356
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.108095922
Short name T514
Test name
Test status
Simulation time 24560294 ps
CPU time 1.14 seconds
Started Jul 24 07:00:33 PM PDT 24
Finished Jul 24 07:00:35 PM PDT 24
Peak memory 209260 kb
Host smart-8b6c8039-a656-45f0-9bfb-1ee0cf9eb214
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108095922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.108095922
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3769246980
Short name T645
Test name
Test status
Simulation time 523690204 ps
CPU time 12.64 seconds
Started Jul 24 07:00:25 PM PDT 24
Finished Jul 24 07:00:38 PM PDT 24
Peak memory 226124 kb
Host smart-18f7a619-43fc-48ef-bf32-8eb6abeadd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769246980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3769246980
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1410021133
Short name T7
Test name
Test status
Simulation time 768535030 ps
CPU time 5.54 seconds
Started Jul 24 07:00:26 PM PDT 24
Finished Jul 24 07:00:32 PM PDT 24
Peak memory 217332 kb
Host smart-d8ff8471-a6c1-44c6-a3c7-13723f5cee18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410021133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1410021133
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2522965993
Short name T714
Test name
Test status
Simulation time 28705575 ps
CPU time 1.88 seconds
Started Jul 24 07:00:25 PM PDT 24
Finished Jul 24 07:00:27 PM PDT 24
Peak memory 222236 kb
Host smart-9de9a1a8-1965-4e04-9122-b223e5fae919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522965993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2522965993
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3104487498
Short name T739
Test name
Test status
Simulation time 418848330 ps
CPU time 11.09 seconds
Started Jul 24 07:00:26 PM PDT 24
Finished Jul 24 07:00:37 PM PDT 24
Peak memory 219080 kb
Host smart-321c5770-165a-42b4-a422-b3847972e3ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104487498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3104487498
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.708673641
Short name T595
Test name
Test status
Simulation time 718837554 ps
CPU time 8.88 seconds
Started Jul 24 07:00:30 PM PDT 24
Finished Jul 24 07:00:39 PM PDT 24
Peak memory 226132 kb
Host smart-80a0f09c-5362-4c8c-9572-1acb08a35d4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708673641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.708673641
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.197418842
Short name T686
Test name
Test status
Simulation time 483014713 ps
CPU time 7.74 seconds
Started Jul 24 07:00:31 PM PDT 24
Finished Jul 24 07:00:39 PM PDT 24
Peak memory 218320 kb
Host smart-4e13a4a4-6d83-4051-833a-19a7ad379d8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197418842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.197418842
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2363750715
Short name T61
Test name
Test status
Simulation time 449300666 ps
CPU time 9.09 seconds
Started Jul 24 07:00:25 PM PDT 24
Finished Jul 24 07:00:34 PM PDT 24
Peak memory 218424 kb
Host smart-1620a9fc-6153-4073-88d1-8379f0a9bf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363750715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2363750715
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3797372263
Short name T212
Test name
Test status
Simulation time 74384161 ps
CPU time 1.43 seconds
Started Jul 24 07:00:27 PM PDT 24
Finished Jul 24 07:00:29 PM PDT 24
Peak memory 217728 kb
Host smart-5d1d820c-a7cd-4ef7-9533-d5b840db8cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797372263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3797372263
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.604660214
Short name T713
Test name
Test status
Simulation time 997276293 ps
CPU time 31.17 seconds
Started Jul 24 07:00:25 PM PDT 24
Finished Jul 24 07:00:56 PM PDT 24
Peak memory 251052 kb
Host smart-bc57482b-56f5-4009-a407-0a5c36c312a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604660214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.604660214
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2985632446
Short name T421
Test name
Test status
Simulation time 44129350 ps
CPU time 3.21 seconds
Started Jul 24 07:00:37 PM PDT 24
Finished Jul 24 07:00:41 PM PDT 24
Peak memory 221584 kb
Host smart-55954273-4340-4872-bfff-c4a5afb9007e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985632446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2985632446
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2088474809
Short name T678
Test name
Test status
Simulation time 6156815143 ps
CPU time 47.55 seconds
Started Jul 24 07:00:27 PM PDT 24
Finished Jul 24 07:01:15 PM PDT 24
Peak memory 221440 kb
Host smart-197991b3-0c65-4435-83cc-a6b2e580f481
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088474809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2088474809
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2640430395
Short name T341
Test name
Test status
Simulation time 24144196 ps
CPU time 0.83 seconds
Started Jul 24 07:00:25 PM PDT 24
Finished Jul 24 07:00:26 PM PDT 24
Peak memory 209016 kb
Host smart-9499939c-4991-44ab-a18e-9a4578e0ce75
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640430395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2640430395
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1548016888
Short name T232
Test name
Test status
Simulation time 19068514 ps
CPU time 0.95 seconds
Started Jul 24 06:57:47 PM PDT 24
Finished Jul 24 06:57:48 PM PDT 24
Peak memory 208996 kb
Host smart-ae060852-c52d-4f8d-a8d2-d17671ea8544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548016888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1548016888
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2485976220
Short name T543
Test name
Test status
Simulation time 612130100 ps
CPU time 12.81 seconds
Started Jul 24 06:57:39 PM PDT 24
Finished Jul 24 06:57:51 PM PDT 24
Peak memory 218360 kb
Host smart-661487fd-b4e8-48e6-88ae-6dc9192b3557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485976220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2485976220
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2286026840
Short name T865
Test name
Test status
Simulation time 1047264938 ps
CPU time 7.91 seconds
Started Jul 24 06:57:51 PM PDT 24
Finished Jul 24 06:57:59 PM PDT 24
Peak memory 217776 kb
Host smart-1b352619-0ca6-418f-b582-a9a0a2687ed6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286026840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2286026840
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2310466784
Short name T312
Test name
Test status
Simulation time 1607794135 ps
CPU time 47.55 seconds
Started Jul 24 06:57:48 PM PDT 24
Finished Jul 24 06:58:36 PM PDT 24
Peak memory 218276 kb
Host smart-2477b0c2-3ea5-4955-9254-0a7b27bd2490
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310466784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2310466784
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3915466993
Short name T8
Test name
Test status
Simulation time 1129027026 ps
CPU time 18.67 seconds
Started Jul 24 06:57:46 PM PDT 24
Finished Jul 24 06:58:05 PM PDT 24
Peak memory 217840 kb
Host smart-3596d13d-1104-45b9-bd9a-3e31a1edb877
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915466993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
915466993
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2075571820
Short name T847
Test name
Test status
Simulation time 397946330 ps
CPU time 10.97 seconds
Started Jul 24 06:57:49 PM PDT 24
Finished Jul 24 06:58:00 PM PDT 24
Peak memory 223140 kb
Host smart-2596dac0-c5f8-4afe-856c-e2222deeb2da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075571820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2075571820
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.219936412
Short name T74
Test name
Test status
Simulation time 1581965986 ps
CPU time 16.57 seconds
Started Jul 24 06:57:46 PM PDT 24
Finished Jul 24 06:58:03 PM PDT 24
Peak memory 217644 kb
Host smart-9213ad9a-fb08-4948-8cf0-203517018194
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219936412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_regwen_during_op.219936412
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3136505261
Short name T348
Test name
Test status
Simulation time 1446069762 ps
CPU time 5.85 seconds
Started Jul 24 06:57:48 PM PDT 24
Finished Jul 24 06:57:54 PM PDT 24
Peak memory 217544 kb
Host smart-dcc761eb-f75b-42f3-83b4-3be6c171758f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136505261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3136505261
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3861375024
Short name T2
Test name
Test status
Simulation time 1193876271 ps
CPU time 35.82 seconds
Started Jul 24 06:57:45 PM PDT 24
Finished Jul 24 06:58:21 PM PDT 24
Peak memory 267936 kb
Host smart-c8cb3dfb-ed5d-450e-bf5c-df8eb988c378
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861375024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3861375024
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3494880774
Short name T349
Test name
Test status
Simulation time 472310670 ps
CPU time 16.59 seconds
Started Jul 24 06:57:47 PM PDT 24
Finished Jul 24 06:58:03 PM PDT 24
Peak memory 245936 kb
Host smart-2957bd87-8b2c-49db-bc8d-53cc20090801
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494880774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3494880774
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2173971686
Short name T476
Test name
Test status
Simulation time 661484707 ps
CPU time 3.91 seconds
Started Jul 24 06:57:40 PM PDT 24
Finished Jul 24 06:57:44 PM PDT 24
Peak memory 218352 kb
Host smart-f3c66a85-afd4-4343-8a22-0e88a21224dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173971686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2173971686
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1414890343
Short name T772
Test name
Test status
Simulation time 327332452 ps
CPU time 5.06 seconds
Started Jul 24 06:57:47 PM PDT 24
Finished Jul 24 06:57:52 PM PDT 24
Peak memory 214500 kb
Host smart-58c5aaa2-a8f6-43ed-bb0c-edebf388c64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414890343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1414890343
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2219121920
Short name T93
Test name
Test status
Simulation time 218244543 ps
CPU time 38.88 seconds
Started Jul 24 06:57:48 PM PDT 24
Finished Jul 24 06:58:27 PM PDT 24
Peak memory 270024 kb
Host smart-8c09d720-f645-4a71-a292-723b2725c3e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219121920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2219121920
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.3806425128
Short name T561
Test name
Test status
Simulation time 342096989 ps
CPU time 15.15 seconds
Started Jul 24 06:57:46 PM PDT 24
Finished Jul 24 06:58:01 PM PDT 24
Peak memory 225904 kb
Host smart-57f0776e-7cf7-4138-90f2-6723993bc8fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806425128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3806425128
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.313833275
Short name T684
Test name
Test status
Simulation time 1030179146 ps
CPU time 8.15 seconds
Started Jul 24 06:57:46 PM PDT 24
Finished Jul 24 06:57:55 PM PDT 24
Peak memory 226068 kb
Host smart-2675fb71-9cb6-4b15-a1cc-7a6b8a4ad5b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313833275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.313833275
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1142746563
Short name T608
Test name
Test status
Simulation time 198376682 ps
CPU time 7.17 seconds
Started Jul 24 06:57:45 PM PDT 24
Finished Jul 24 06:57:53 PM PDT 24
Peak memory 218208 kb
Host smart-56e93428-a0d2-4d8f-b7b4-506fb803bfe8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142746563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
142746563
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1465446979
Short name T740
Test name
Test status
Simulation time 396344285 ps
CPU time 10.76 seconds
Started Jul 24 06:57:41 PM PDT 24
Finished Jul 24 06:57:52 PM PDT 24
Peak memory 218360 kb
Host smart-c6bca819-2a28-4cfb-9933-5c75682e368a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465446979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1465446979
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3152212540
Short name T263
Test name
Test status
Simulation time 52743554 ps
CPU time 2.43 seconds
Started Jul 24 06:57:39 PM PDT 24
Finished Jul 24 06:57:42 PM PDT 24
Peak memory 217740 kb
Host smart-d1490aeb-7b7c-49bc-9a21-aefe5cc20468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152212540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3152212540
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2193692941
Short name T260
Test name
Test status
Simulation time 430952345 ps
CPU time 23.82 seconds
Started Jul 24 06:57:38 PM PDT 24
Finished Jul 24 06:58:02 PM PDT 24
Peak memory 245864 kb
Host smart-9f268edb-92e9-4652-96e2-24f5f4baaa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193692941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2193692941
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2159895530
Short name T845
Test name
Test status
Simulation time 178979114 ps
CPU time 7.24 seconds
Started Jul 24 06:57:40 PM PDT 24
Finished Jul 24 06:57:47 PM PDT 24
Peak memory 250604 kb
Host smart-6edbbac1-e1e8-4ab8-86b7-8f1b55bdd3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159895530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2159895530
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1150968148
Short name T337
Test name
Test status
Simulation time 105327826590 ps
CPU time 528.23 seconds
Started Jul 24 06:57:46 PM PDT 24
Finished Jul 24 07:06:35 PM PDT 24
Peak memory 283256 kb
Host smart-af7511f1-6de3-4ca2-8bd8-c0e445fc445e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150968148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1150968148
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2030775583
Short name T31
Test name
Test status
Simulation time 18403677 ps
CPU time 1.03 seconds
Started Jul 24 06:57:39 PM PDT 24
Finished Jul 24 06:57:41 PM PDT 24
Peak memory 217952 kb
Host smart-de24f494-60e4-4e21-bcf9-e649478b2daa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030775583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2030775583
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1631450666
Short name T622
Test name
Test status
Simulation time 63571738 ps
CPU time 0.98 seconds
Started Jul 24 07:00:32 PM PDT 24
Finished Jul 24 07:00:33 PM PDT 24
Peak memory 208972 kb
Host smart-2c7a9d4f-2d7e-48af-a0de-8d25e2311f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631450666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1631450666
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3873459211
Short name T402
Test name
Test status
Simulation time 1170680327 ps
CPU time 9.7 seconds
Started Jul 24 07:00:31 PM PDT 24
Finished Jul 24 07:00:41 PM PDT 24
Peak memory 226164 kb
Host smart-9724ff3b-5854-4107-928a-2520ddfd9ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873459211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3873459211
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2309261358
Short name T771
Test name
Test status
Simulation time 984401672 ps
CPU time 6.95 seconds
Started Jul 24 07:00:31 PM PDT 24
Finished Jul 24 07:00:38 PM PDT 24
Peak memory 217764 kb
Host smart-3211651e-54e2-447b-97a2-75252d3e30ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309261358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2309261358
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.468736767
Short name T479
Test name
Test status
Simulation time 47546747 ps
CPU time 1.55 seconds
Started Jul 24 07:00:31 PM PDT 24
Finished Jul 24 07:00:33 PM PDT 24
Peak memory 218364 kb
Host smart-323e4f9d-dc03-4de9-9d1e-799657fc8c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468736767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.468736767
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.2037825846
Short name T323
Test name
Test status
Simulation time 273308004 ps
CPU time 8.37 seconds
Started Jul 24 07:00:32 PM PDT 24
Finished Jul 24 07:00:41 PM PDT 24
Peak memory 226136 kb
Host smart-cd3f0e44-d26c-4c5f-8fdb-1ce32e57ef46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037825846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.2037825846
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3442492125
Short name T810
Test name
Test status
Simulation time 498033087 ps
CPU time 18.15 seconds
Started Jul 24 07:00:31 PM PDT 24
Finished Jul 24 07:00:49 PM PDT 24
Peak memory 226076 kb
Host smart-ed51af80-3472-4d14-b9db-f1a00eabd689
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442492125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3442492125
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.897561128
Short name T500
Test name
Test status
Simulation time 720224722 ps
CPU time 12.99 seconds
Started Jul 24 07:00:30 PM PDT 24
Finished Jul 24 07:00:43 PM PDT 24
Peak memory 226084 kb
Host smart-622a23f8-4e2b-425d-b141-7ae26cb49590
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897561128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.897561128
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1426066422
Short name T377
Test name
Test status
Simulation time 1044324703 ps
CPU time 10.15 seconds
Started Jul 24 07:00:34 PM PDT 24
Finished Jul 24 07:00:44 PM PDT 24
Peak memory 218472 kb
Host smart-05ce12bd-e488-4e72-bb79-bed6c1d5669e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426066422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1426066422
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2805093593
Short name T235
Test name
Test status
Simulation time 78155185 ps
CPU time 1.84 seconds
Started Jul 24 07:00:31 PM PDT 24
Finished Jul 24 07:00:33 PM PDT 24
Peak memory 223456 kb
Host smart-6a732054-0aed-4410-a1fb-920a0a28930a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805093593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2805093593
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.2228874494
Short name T766
Test name
Test status
Simulation time 516319663 ps
CPU time 27.57 seconds
Started Jul 24 07:00:30 PM PDT 24
Finished Jul 24 07:00:57 PM PDT 24
Peak memory 250956 kb
Host smart-e6ebf549-6996-454e-affa-491ae5e223b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228874494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2228874494
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3248038417
Short name T538
Test name
Test status
Simulation time 318048481 ps
CPU time 6.33 seconds
Started Jul 24 07:00:32 PM PDT 24
Finished Jul 24 07:00:39 PM PDT 24
Peak memory 247288 kb
Host smart-61e89c38-dcbd-45ec-9cef-759043b8a9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248038417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3248038417
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2875324698
Short name T354
Test name
Test status
Simulation time 1759097868 ps
CPU time 96.86 seconds
Started Jul 24 07:00:31 PM PDT 24
Finished Jul 24 07:02:08 PM PDT 24
Peak memory 269264 kb
Host smart-86c45f63-2ef5-4897-844d-46976286578d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875324698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2875324698
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1840983775
Short name T750
Test name
Test status
Simulation time 15047995 ps
CPU time 1.03 seconds
Started Jul 24 07:00:30 PM PDT 24
Finished Jul 24 07:00:31 PM PDT 24
Peak memory 209188 kb
Host smart-912875d6-0993-4ddb-84fb-5cdbceac3bb5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840983775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1840983775
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2967409418
Short name T759
Test name
Test status
Simulation time 13520414 ps
CPU time 0.89 seconds
Started Jul 24 07:00:38 PM PDT 24
Finished Jul 24 07:00:39 PM PDT 24
Peak memory 208844 kb
Host smart-bde15616-459c-425c-a491-24cb38d39013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967409418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2967409418
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1877308577
Short name T436
Test name
Test status
Simulation time 1597748713 ps
CPU time 17.6 seconds
Started Jul 24 07:00:33 PM PDT 24
Finished Jul 24 07:00:50 PM PDT 24
Peak memory 226164 kb
Host smart-b9c88164-46ca-47ec-8ef3-6ad012bd2892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877308577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1877308577
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3860708693
Short name T448
Test name
Test status
Simulation time 2667164666 ps
CPU time 4.44 seconds
Started Jul 24 07:00:37 PM PDT 24
Finished Jul 24 07:00:42 PM PDT 24
Peak memory 217832 kb
Host smart-c9eacf17-7176-47e2-9f8c-351289438e9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860708693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3860708693
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.4239201655
Short name T394
Test name
Test status
Simulation time 225825890 ps
CPU time 3.4 seconds
Started Jul 24 07:00:32 PM PDT 24
Finished Jul 24 07:00:35 PM PDT 24
Peak memory 218340 kb
Host smart-84af5acd-9c3e-47d0-aed6-0809863dddca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239201655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.4239201655
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1002514470
Short name T590
Test name
Test status
Simulation time 1076112778 ps
CPU time 11.08 seconds
Started Jul 24 07:00:38 PM PDT 24
Finished Jul 24 07:00:49 PM PDT 24
Peak memory 218452 kb
Host smart-11c36b19-341f-4ae8-84e1-03a309620987
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002514470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1002514470
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1492146942
Short name T841
Test name
Test status
Simulation time 434187297 ps
CPU time 14.31 seconds
Started Jul 24 07:00:37 PM PDT 24
Finished Jul 24 07:00:51 PM PDT 24
Peak memory 226108 kb
Host smart-eedf9581-a503-4526-9646-f7b8bb915c5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492146942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1492146942
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.959055896
Short name T153
Test name
Test status
Simulation time 2459391703 ps
CPU time 7.02 seconds
Started Jul 24 07:00:39 PM PDT 24
Finished Jul 24 07:00:46 PM PDT 24
Peak memory 226084 kb
Host smart-38b7d34f-11c0-4592-a64a-b4392340e683
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959055896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.959055896
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.777826773
Short name T584
Test name
Test status
Simulation time 209206091 ps
CPU time 8.14 seconds
Started Jul 24 07:00:30 PM PDT 24
Finished Jul 24 07:00:38 PM PDT 24
Peak memory 224988 kb
Host smart-a2d3472d-c4fa-4404-8b24-af3f056f8b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777826773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.777826773
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1717302382
Short name T306
Test name
Test status
Simulation time 47334548 ps
CPU time 2.29 seconds
Started Jul 24 07:00:30 PM PDT 24
Finished Jul 24 07:00:33 PM PDT 24
Peak memory 217840 kb
Host smart-bae33236-dbec-4151-a344-c4951aea1152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717302382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1717302382
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1014966489
Short name T252
Test name
Test status
Simulation time 439469205 ps
CPU time 35.18 seconds
Started Jul 24 07:00:31 PM PDT 24
Finished Jul 24 07:01:06 PM PDT 24
Peak memory 250992 kb
Host smart-4e5163df-065e-422e-8762-227a99b967e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014966489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1014966489
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2976062217
Short name T624
Test name
Test status
Simulation time 654619990 ps
CPU time 9.28 seconds
Started Jul 24 07:00:31 PM PDT 24
Finished Jul 24 07:00:40 PM PDT 24
Peak memory 250948 kb
Host smart-df86eca2-a6bd-4759-8394-f406d71d2613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976062217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2976062217
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1031133081
Short name T513
Test name
Test status
Simulation time 10746201718 ps
CPU time 366.75 seconds
Started Jul 24 07:00:38 PM PDT 24
Finished Jul 24 07:06:45 PM PDT 24
Peak memory 283728 kb
Host smart-0710f265-a411-432c-88c9-981b689e3295
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031133081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1031133081
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.204152299
Short name T542
Test name
Test status
Simulation time 13368479 ps
CPU time 0.85 seconds
Started Jul 24 07:00:33 PM PDT 24
Finished Jul 24 07:00:34 PM PDT 24
Peak memory 209000 kb
Host smart-31f0ad7d-524e-4bec-87cd-917bc325ba73
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204152299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ct
rl_volatile_unlock_smoke.204152299
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.4029740579
Short name T761
Test name
Test status
Simulation time 18383915 ps
CPU time 1.11 seconds
Started Jul 24 07:00:54 PM PDT 24
Finished Jul 24 07:00:56 PM PDT 24
Peak memory 209052 kb
Host smart-62950cea-6ff7-4077-86d8-f806d6153dea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029740579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.4029740579
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3030897597
Short name T838
Test name
Test status
Simulation time 2921317665 ps
CPU time 14.58 seconds
Started Jul 24 07:00:38 PM PDT 24
Finished Jul 24 07:00:53 PM PDT 24
Peak memory 218328 kb
Host smart-aa70f961-dac5-4099-80e2-632ebd1202c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030897597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3030897597
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2204566735
Short name T503
Test name
Test status
Simulation time 2427332862 ps
CPU time 6.99 seconds
Started Jul 24 07:00:37 PM PDT 24
Finished Jul 24 07:00:45 PM PDT 24
Peak memory 217912 kb
Host smart-66323f6e-91a5-4072-8b1a-5646327dea91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204566735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2204566735
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3447124989
Short name T457
Test name
Test status
Simulation time 133398840 ps
CPU time 2.13 seconds
Started Jul 24 07:00:43 PM PDT 24
Finished Jul 24 07:00:45 PM PDT 24
Peak memory 218332 kb
Host smart-d773f9ba-bb44-4386-8dcc-68aaffc0fa64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447124989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3447124989
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1511714735
Short name T213
Test name
Test status
Simulation time 413354420 ps
CPU time 13 seconds
Started Jul 24 07:00:54 PM PDT 24
Finished Jul 24 07:01:08 PM PDT 24
Peak memory 219028 kb
Host smart-3f459560-a733-4853-bc98-19ee68d1d556
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511714735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1511714735
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1766499239
Short name T427
Test name
Test status
Simulation time 1721729758 ps
CPU time 10.25 seconds
Started Jul 24 07:00:45 PM PDT 24
Finished Jul 24 07:00:56 PM PDT 24
Peak memory 226124 kb
Host smart-bdd13190-05ad-4356-8b73-7aff4e1d2729
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766499239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1766499239
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1852169648
Short name T518
Test name
Test status
Simulation time 394828145 ps
CPU time 10.03 seconds
Started Jul 24 07:00:46 PM PDT 24
Finished Jul 24 07:00:56 PM PDT 24
Peak memory 218424 kb
Host smart-1ebeef91-f7ad-4ad9-8702-fdd2f99210b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852169648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1852169648
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.576615088
Short name T414
Test name
Test status
Simulation time 77015154 ps
CPU time 3.91 seconds
Started Jul 24 07:00:38 PM PDT 24
Finished Jul 24 07:00:42 PM PDT 24
Peak memory 217712 kb
Host smart-725dfcfd-d969-4f54-984d-63f879d27899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576615088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.576615088
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1963915852
Short name T605
Test name
Test status
Simulation time 708091132 ps
CPU time 25.61 seconds
Started Jul 24 07:00:36 PM PDT 24
Finished Jul 24 07:01:02 PM PDT 24
Peak memory 250980 kb
Host smart-1459b29f-7ea4-444a-9bfd-fa81aaab6a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963915852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1963915852
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3846850119
Short name T827
Test name
Test status
Simulation time 162559667 ps
CPU time 9.09 seconds
Started Jul 24 07:00:37 PM PDT 24
Finished Jul 24 07:00:47 PM PDT 24
Peak memory 250988 kb
Host smart-ed242769-e329-4281-86c5-93ac9c15d0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846850119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3846850119
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1632986933
Short name T271
Test name
Test status
Simulation time 11854330467 ps
CPU time 196.05 seconds
Started Jul 24 07:00:46 PM PDT 24
Finished Jul 24 07:04:02 PM PDT 24
Peak memory 259180 kb
Host smart-f2604c6f-ab95-4b0d-ba28-be9c0fe6ca95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632986933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1632986933
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3983045608
Short name T763
Test name
Test status
Simulation time 15605468 ps
CPU time 0.99 seconds
Started Jul 24 07:00:37 PM PDT 24
Finished Jul 24 07:00:38 PM PDT 24
Peak memory 212020 kb
Host smart-42f9ea29-2536-4ba7-87b9-efc35cf29eab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983045608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3983045608
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2142964209
Short name T77
Test name
Test status
Simulation time 42367800 ps
CPU time 0.85 seconds
Started Jul 24 07:00:54 PM PDT 24
Finished Jul 24 07:00:55 PM PDT 24
Peak memory 208904 kb
Host smart-449418a0-1246-42ac-8366-2e27addda6d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142964209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2142964209
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3772504773
Short name T704
Test name
Test status
Simulation time 215789316 ps
CPU time 10.01 seconds
Started Jul 24 07:00:48 PM PDT 24
Finished Jul 24 07:00:58 PM PDT 24
Peak memory 218312 kb
Host smart-e9b10605-80b7-41f5-bf50-04d99700fc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772504773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3772504773
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1789949317
Short name T24
Test name
Test status
Simulation time 1263891219 ps
CPU time 8.23 seconds
Started Jul 24 07:00:49 PM PDT 24
Finished Jul 24 07:00:57 PM PDT 24
Peak memory 217856 kb
Host smart-5694ec29-61f2-4ec7-9515-44a716c1bf15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789949317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1789949317
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2465074252
Short name T578
Test name
Test status
Simulation time 108040351 ps
CPU time 2.18 seconds
Started Jul 24 07:00:44 PM PDT 24
Finished Jul 24 07:00:47 PM PDT 24
Peak memory 218336 kb
Host smart-b053e5ee-a59b-4bb3-8072-db09e2c9cc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465074252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2465074252
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.4089908021
Short name T669
Test name
Test status
Simulation time 903252881 ps
CPU time 10.31 seconds
Started Jul 24 07:00:54 PM PDT 24
Finished Jul 24 07:01:05 PM PDT 24
Peak memory 226152 kb
Host smart-976ef079-7a80-47c7-8d8a-6fd7ec49f6b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089908021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.4089908021
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2174605360
Short name T198
Test name
Test status
Simulation time 2685690949 ps
CPU time 8.26 seconds
Started Jul 24 07:00:50 PM PDT 24
Finished Jul 24 07:00:58 PM PDT 24
Peak memory 226164 kb
Host smart-15e95abd-5545-403c-ab42-f6f4af3f61f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174605360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2174605360
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3009168526
Short name T734
Test name
Test status
Simulation time 298416858 ps
CPU time 8.07 seconds
Started Jul 24 07:00:54 PM PDT 24
Finished Jul 24 07:01:03 PM PDT 24
Peak memory 218308 kb
Host smart-86c9910b-a436-4d43-9344-619954f5076b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009168526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3009168526
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3316783969
Short name T324
Test name
Test status
Simulation time 453160379 ps
CPU time 9.9 seconds
Started Jul 24 07:01:03 PM PDT 24
Finished Jul 24 07:01:13 PM PDT 24
Peak memory 218304 kb
Host smart-571fee02-5fb9-48d3-ac69-1a5b36b00f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316783969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3316783969
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.965398356
Short name T534
Test name
Test status
Simulation time 302676495 ps
CPU time 4.49 seconds
Started Jul 24 07:00:54 PM PDT 24
Finished Jul 24 07:00:59 PM PDT 24
Peak memory 217776 kb
Host smart-1749618c-a82b-4d1d-8d31-f31c2c01d4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965398356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.965398356
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.356797441
Short name T258
Test name
Test status
Simulation time 1308704157 ps
CPU time 34.91 seconds
Started Jul 24 07:00:44 PM PDT 24
Finished Jul 24 07:01:20 PM PDT 24
Peak memory 250980 kb
Host smart-b8b159e6-9442-4f19-8201-8b3a23dee4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356797441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.356797441
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1713683885
Short name T261
Test name
Test status
Simulation time 49583515 ps
CPU time 3.42 seconds
Started Jul 24 07:00:45 PM PDT 24
Finished Jul 24 07:00:49 PM PDT 24
Peak memory 226468 kb
Host smart-1b77948d-7e79-4f96-bec6-3239d68ed3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713683885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1713683885
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2981611063
Short name T651
Test name
Test status
Simulation time 18450646325 ps
CPU time 195.17 seconds
Started Jul 24 07:00:46 PM PDT 24
Finished Jul 24 07:04:01 PM PDT 24
Peak memory 283820 kb
Host smart-20b8ac63-d48a-4c49-96e4-04dcbb0172e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981611063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2981611063
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.2064210762
Short name T664
Test name
Test status
Simulation time 37649753887 ps
CPU time 868.32 seconds
Started Jul 24 07:00:49 PM PDT 24
Finished Jul 24 07:15:18 PM PDT 24
Peak memory 497072 kb
Host smart-6671b8d8-8af5-4c58-a771-1d647aa4bb31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2064210762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.2064210762
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2877242011
Short name T711
Test name
Test status
Simulation time 123204901 ps
CPU time 1.41 seconds
Started Jul 24 07:01:00 PM PDT 24
Finished Jul 24 07:01:01 PM PDT 24
Peak memory 209164 kb
Host smart-e6b2005b-51b5-44af-afaf-b62b5d28d86f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877242011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2877242011
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1374267294
Short name T804
Test name
Test status
Simulation time 1354716085 ps
CPU time 7.93 seconds
Started Jul 24 07:00:54 PM PDT 24
Finished Jul 24 07:01:02 PM PDT 24
Peak memory 226280 kb
Host smart-c143f9e8-3b4f-4264-b4ba-d70ff23df6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374267294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1374267294
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.702283380
Short name T547
Test name
Test status
Simulation time 376522785 ps
CPU time 1.83 seconds
Started Jul 24 07:00:55 PM PDT 24
Finished Jul 24 07:00:57 PM PDT 24
Peak memory 217204 kb
Host smart-39ce8234-a128-4d4c-98fc-652444bdde2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702283380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.702283380
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.66412271
Short name T701
Test name
Test status
Simulation time 41218722 ps
CPU time 2.09 seconds
Started Jul 24 07:00:56 PM PDT 24
Finished Jul 24 07:00:58 PM PDT 24
Peak memory 218356 kb
Host smart-a4b25324-2af2-4b98-91d0-531c091c87a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66412271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.66412271
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.4245004811
Short name T333
Test name
Test status
Simulation time 690923431 ps
CPU time 13.2 seconds
Started Jul 24 07:00:55 PM PDT 24
Finished Jul 24 07:01:09 PM PDT 24
Peak memory 218452 kb
Host smart-c8d531d0-db04-40e5-85c8-896d186af876
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245004811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.4245004811
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.4163566999
Short name T374
Test name
Test status
Simulation time 609806347 ps
CPU time 10.19 seconds
Started Jul 24 07:00:56 PM PDT 24
Finished Jul 24 07:01:06 PM PDT 24
Peak memory 218300 kb
Host smart-418fc502-9a4f-41bf-b976-18607c673d59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163566999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.4163566999
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3035583265
Short name T366
Test name
Test status
Simulation time 1333228314 ps
CPU time 8.85 seconds
Started Jul 24 07:00:53 PM PDT 24
Finished Jul 24 07:01:02 PM PDT 24
Peak memory 218268 kb
Host smart-cf0093a2-41af-44ea-8fd9-049931d17030
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035583265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3035583265
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.2432262523
Short name T798
Test name
Test status
Simulation time 263279758 ps
CPU time 10.96 seconds
Started Jul 24 07:00:51 PM PDT 24
Finished Jul 24 07:01:02 PM PDT 24
Peak memory 218412 kb
Host smart-29dfc2d4-427a-4050-ab5e-454ae616a17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432262523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.2432262523
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.515130264
Short name T692
Test name
Test status
Simulation time 105214699 ps
CPU time 2.66 seconds
Started Jul 24 07:00:44 PM PDT 24
Finished Jul 24 07:00:47 PM PDT 24
Peak memory 214428 kb
Host smart-9c9e4fee-673b-4fe9-98cb-d66df94c2afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515130264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.515130264
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1067383893
Short name T760
Test name
Test status
Simulation time 256183065 ps
CPU time 23.2 seconds
Started Jul 24 07:00:52 PM PDT 24
Finished Jul 24 07:01:15 PM PDT 24
Peak memory 251024 kb
Host smart-ca2045dc-67f6-495a-9c54-29b7611e1152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067383893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1067383893
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1719635847
Short name T564
Test name
Test status
Simulation time 206377596 ps
CPU time 3.57 seconds
Started Jul 24 07:00:50 PM PDT 24
Finished Jul 24 07:00:54 PM PDT 24
Peak memory 226412 kb
Host smart-9542372d-b7ca-4a4d-8c60-d90896965e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719635847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1719635847
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2355275589
Short name T716
Test name
Test status
Simulation time 2789436558 ps
CPU time 37.38 seconds
Started Jul 24 07:00:56 PM PDT 24
Finished Jul 24 07:01:34 PM PDT 24
Peak memory 226104 kb
Host smart-36a775af-7e5e-46ab-a82d-59a00f8d4178
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355275589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2355275589
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2042492893
Short name T254
Test name
Test status
Simulation time 14709240 ps
CPU time 0.93 seconds
Started Jul 24 07:00:44 PM PDT 24
Finished Jul 24 07:00:45 PM PDT 24
Peak memory 209108 kb
Host smart-729e5b80-07e4-4a18-bfa1-e8b77a7b9f5c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042492893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2042492893
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.414021937
Short name T581
Test name
Test status
Simulation time 34214832 ps
CPU time 1.14 seconds
Started Jul 24 07:00:58 PM PDT 24
Finished Jul 24 07:01:00 PM PDT 24
Peak memory 209024 kb
Host smart-6f6b1d9e-7583-484c-b3d8-90e7aecf93c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414021937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.414021937
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1067836999
Short name T784
Test name
Test status
Simulation time 5488748625 ps
CPU time 12.53 seconds
Started Jul 24 07:00:55 PM PDT 24
Finished Jul 24 07:01:08 PM PDT 24
Peak memory 218428 kb
Host smart-cc5bc293-e520-40ff-80a7-b25417d114f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067836999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1067836999
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3296234051
Short name T717
Test name
Test status
Simulation time 543679927 ps
CPU time 7.07 seconds
Started Jul 24 07:00:50 PM PDT 24
Finished Jul 24 07:00:57 PM PDT 24
Peak memory 217252 kb
Host smart-40c07979-6000-4c9f-86e8-1028e21d231f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296234051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3296234051
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1663979499
Short name T516
Test name
Test status
Simulation time 123999857 ps
CPU time 3.75 seconds
Started Jul 24 07:00:56 PM PDT 24
Finished Jul 24 07:01:00 PM PDT 24
Peak memory 218300 kb
Host smart-7a3ef721-d8a5-4de7-9160-2139ba3cd34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663979499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1663979499
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2153272511
Short name T46
Test name
Test status
Simulation time 1713318656 ps
CPU time 18.76 seconds
Started Jul 24 07:00:58 PM PDT 24
Finished Jul 24 07:01:17 PM PDT 24
Peak memory 220016 kb
Host smart-b1d750d5-c9a7-434c-ac6b-4ac0966ec673
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153272511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2153272511
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.75179824
Short name T623
Test name
Test status
Simulation time 782636061 ps
CPU time 12.08 seconds
Started Jul 24 07:01:02 PM PDT 24
Finished Jul 24 07:01:14 PM PDT 24
Peak memory 226132 kb
Host smart-39b37280-417a-4f2c-a6d2-119a8ec00e23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75179824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_dig
est.75179824
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.977690425
Short name T633
Test name
Test status
Simulation time 5397712538 ps
CPU time 10.34 seconds
Started Jul 24 07:00:59 PM PDT 24
Finished Jul 24 07:01:10 PM PDT 24
Peak memory 218348 kb
Host smart-36ff3d8f-c56d-4e4e-84d5-1be32d491319
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977690425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.977690425
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1669913081
Short name T294
Test name
Test status
Simulation time 318076502 ps
CPU time 12 seconds
Started Jul 24 07:00:55 PM PDT 24
Finished Jul 24 07:01:07 PM PDT 24
Peak memory 218368 kb
Host smart-6c2370db-0345-4af4-a086-750200e3536a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669913081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1669913081
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2479863199
Short name T600
Test name
Test status
Simulation time 62956182 ps
CPU time 2.96 seconds
Started Jul 24 07:00:55 PM PDT 24
Finished Jul 24 07:00:58 PM PDT 24
Peak memory 214948 kb
Host smart-745d942c-56ee-4f10-a889-892390c376a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479863199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2479863199
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1614297415
Short name T749
Test name
Test status
Simulation time 766995404 ps
CPU time 19.7 seconds
Started Jul 24 07:00:55 PM PDT 24
Finished Jul 24 07:01:15 PM PDT 24
Peak memory 250896 kb
Host smart-af771d43-2390-48a4-a66a-a702f13ec65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614297415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1614297415
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.732616262
Short name T325
Test name
Test status
Simulation time 217479429 ps
CPU time 7.17 seconds
Started Jul 24 07:00:53 PM PDT 24
Finished Jul 24 07:01:00 PM PDT 24
Peak memory 250928 kb
Host smart-d5a6fd18-3f59-4688-8ff1-7789d4ca8c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732616262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.732616262
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3347732395
Short name T831
Test name
Test status
Simulation time 10473894839 ps
CPU time 151.61 seconds
Started Jul 24 07:00:58 PM PDT 24
Finished Jul 24 07:03:29 PM PDT 24
Peak memory 278636 kb
Host smart-80da8c1b-bea5-40aa-aa48-e157057eb854
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347732395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3347732395
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2513720734
Short name T244
Test name
Test status
Simulation time 11415540 ps
CPU time 0.86 seconds
Started Jul 24 07:00:50 PM PDT 24
Finished Jul 24 07:00:51 PM PDT 24
Peak memory 208312 kb
Host smart-e322cda9-6c1e-4c22-b2b4-f093e41562c6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513720734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2513720734
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2807166504
Short name T796
Test name
Test status
Simulation time 297540430 ps
CPU time 1.05 seconds
Started Jul 24 07:00:57 PM PDT 24
Finished Jul 24 07:00:58 PM PDT 24
Peak memory 209200 kb
Host smart-a7280521-40f2-4503-ad04-e10d446573ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807166504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2807166504
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3474823349
Short name T296
Test name
Test status
Simulation time 980766134 ps
CPU time 10.92 seconds
Started Jul 24 07:01:00 PM PDT 24
Finished Jul 24 07:01:11 PM PDT 24
Peak memory 218396 kb
Host smart-6870b84b-e1bc-475f-bda1-3e32d26369f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474823349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3474823349
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1007159743
Short name T71
Test name
Test status
Simulation time 639027670 ps
CPU time 1.74 seconds
Started Jul 24 07:00:59 PM PDT 24
Finished Jul 24 07:01:01 PM PDT 24
Peak memory 217872 kb
Host smart-232648a2-0a08-41af-a563-9965c2634336
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007159743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1007159743
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1659155768
Short name T449
Test name
Test status
Simulation time 68569919 ps
CPU time 2.42 seconds
Started Jul 24 07:01:00 PM PDT 24
Finished Jul 24 07:01:02 PM PDT 24
Peak memory 218316 kb
Host smart-35a41ce3-dd70-4e24-8702-4bf787f9fce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659155768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1659155768
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.480616478
Short name T276
Test name
Test status
Simulation time 865010249 ps
CPU time 17.5 seconds
Started Jul 24 07:00:59 PM PDT 24
Finished Jul 24 07:01:16 PM PDT 24
Peak memory 218356 kb
Host smart-2c91f5b9-650d-49d8-b52c-f29c95a1c7dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480616478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.480616478
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1728731701
Short name T319
Test name
Test status
Simulation time 2502881986 ps
CPU time 10.05 seconds
Started Jul 24 07:01:01 PM PDT 24
Finished Jul 24 07:01:11 PM PDT 24
Peak memory 226124 kb
Host smart-af29cd08-d7ac-451a-8f7f-2590faf71142
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728731701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1728731701
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.4102010384
Short name T459
Test name
Test status
Simulation time 3409482425 ps
CPU time 13.14 seconds
Started Jul 24 07:00:59 PM PDT 24
Finished Jul 24 07:01:12 PM PDT 24
Peak memory 218316 kb
Host smart-2ad4a7ab-dc1d-4e4b-8976-b4c78bcf07c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102010384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
4102010384
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3969632964
Short name T328
Test name
Test status
Simulation time 308977517 ps
CPU time 12.43 seconds
Started Jul 24 07:01:01 PM PDT 24
Finished Jul 24 07:01:13 PM PDT 24
Peak memory 218408 kb
Host smart-4b06a761-58a0-44ac-85f8-99b2f30b997f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969632964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3969632964
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2495838802
Short name T317
Test name
Test status
Simulation time 37727809 ps
CPU time 2.51 seconds
Started Jul 24 07:01:01 PM PDT 24
Finished Jul 24 07:01:04 PM PDT 24
Peak memory 217816 kb
Host smart-7a4927d2-13f5-4254-9f88-8de83e7a1168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495838802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2495838802
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3558537016
Short name T295
Test name
Test status
Simulation time 1212023386 ps
CPU time 27.19 seconds
Started Jul 24 07:00:59 PM PDT 24
Finished Jul 24 07:01:26 PM PDT 24
Peak memory 251008 kb
Host smart-cd5eb43c-5cb7-4466-b955-358c3dbfab11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558537016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3558537016
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.996864926
Short name T201
Test name
Test status
Simulation time 644900430 ps
CPU time 9.68 seconds
Started Jul 24 07:01:00 PM PDT 24
Finished Jul 24 07:01:10 PM PDT 24
Peak memory 251016 kb
Host smart-ddf37cb0-d6fb-498e-9bbd-74c0961129e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996864926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.996864926
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2664333208
Short name T758
Test name
Test status
Simulation time 3017864105 ps
CPU time 72.15 seconds
Started Jul 24 07:01:01 PM PDT 24
Finished Jul 24 07:02:13 PM PDT 24
Peak memory 280804 kb
Host smart-296459aa-cdfa-428e-8050-8d159c60de5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664333208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2664333208
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.2813693340
Short name T37
Test name
Test status
Simulation time 33885852564 ps
CPU time 189.61 seconds
Started Jul 24 07:00:59 PM PDT 24
Finished Jul 24 07:04:09 PM PDT 24
Peak memory 251136 kb
Host smart-9959dc2d-3963-49f1-9477-308f85350f27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2813693340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.2813693340
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1006623866
Short name T419
Test name
Test status
Simulation time 43825322 ps
CPU time 1.37 seconds
Started Jul 24 07:00:57 PM PDT 24
Finished Jul 24 07:00:59 PM PDT 24
Peak memory 217844 kb
Host smart-225f7ef1-c917-4f5a-80a9-561d2702be3e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006623866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1006623866
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3606092340
Short name T832
Test name
Test status
Simulation time 17288919 ps
CPU time 1.19 seconds
Started Jul 24 07:01:07 PM PDT 24
Finished Jul 24 07:01:08 PM PDT 24
Peak memory 209132 kb
Host smart-02d4d045-8192-4567-915e-68762dd36888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606092340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3606092340
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1064963922
Short name T671
Test name
Test status
Simulation time 406781767 ps
CPU time 17.23 seconds
Started Jul 24 07:01:00 PM PDT 24
Finished Jul 24 07:01:18 PM PDT 24
Peak memory 218324 kb
Host smart-33b41cac-15ef-491e-912d-5a8f569d5fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064963922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1064963922
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2718139802
Short name T162
Test name
Test status
Simulation time 1695684520 ps
CPU time 10 seconds
Started Jul 24 07:01:02 PM PDT 24
Finished Jul 24 07:01:12 PM PDT 24
Peak memory 217760 kb
Host smart-1ee5417e-e32f-429b-b99a-ee9d2879cb6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718139802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2718139802
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2177885649
Short name T392
Test name
Test status
Simulation time 33716170 ps
CPU time 1.49 seconds
Started Jul 24 07:00:59 PM PDT 24
Finished Jul 24 07:01:01 PM PDT 24
Peak memory 218312 kb
Host smart-0b0e33be-f6c8-4431-8f93-46123f37ca0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177885649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2177885649
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.910476873
Short name T36
Test name
Test status
Simulation time 549494298 ps
CPU time 14.24 seconds
Started Jul 24 07:00:59 PM PDT 24
Finished Jul 24 07:01:13 PM PDT 24
Peak memory 220004 kb
Host smart-049b4394-d004-4af8-b0e0-e60f9a424cab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910476873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.910476873
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.523996156
Short name T397
Test name
Test status
Simulation time 1863996792 ps
CPU time 12.56 seconds
Started Jul 24 07:01:00 PM PDT 24
Finished Jul 24 07:01:12 PM PDT 24
Peak memory 226060 kb
Host smart-849a1680-070a-4113-91ff-31bf8f78c523
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523996156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.523996156
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2737317085
Short name T289
Test name
Test status
Simulation time 1143658889 ps
CPU time 12.1 seconds
Started Jul 24 07:00:58 PM PDT 24
Finished Jul 24 07:01:10 PM PDT 24
Peak memory 218296 kb
Host smart-116cbad1-2be2-4428-b4a5-e8bc75cc2703
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737317085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2737317085
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2405499480
Short name T603
Test name
Test status
Simulation time 698016587 ps
CPU time 8.65 seconds
Started Jul 24 07:00:58 PM PDT 24
Finished Jul 24 07:01:06 PM PDT 24
Peak memory 218348 kb
Host smart-1db2f1ff-7134-4469-817c-c692768fdaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405499480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2405499480
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3697129907
Short name T730
Test name
Test status
Simulation time 27235164 ps
CPU time 1.85 seconds
Started Jul 24 07:00:58 PM PDT 24
Finished Jul 24 07:01:00 PM PDT 24
Peak memory 214008 kb
Host smart-a1023e0a-12e4-44cd-baa2-ecf828918939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697129907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3697129907
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3497178722
Short name T673
Test name
Test status
Simulation time 2543078068 ps
CPU time 29.2 seconds
Started Jul 24 07:00:58 PM PDT 24
Finished Jul 24 07:01:28 PM PDT 24
Peak memory 251044 kb
Host smart-c6a4cc37-9f5f-4a86-9a42-8030cecf0943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497178722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3497178722
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1378614091
Short name T282
Test name
Test status
Simulation time 761452475 ps
CPU time 6.72 seconds
Started Jul 24 07:00:58 PM PDT 24
Finished Jul 24 07:01:05 PM PDT 24
Peak memory 250448 kb
Host smart-fd652226-fa7c-4647-803d-ada035e79e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378614091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1378614091
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3859458675
Short name T477
Test name
Test status
Simulation time 15905310553 ps
CPU time 160.77 seconds
Started Jul 24 07:00:59 PM PDT 24
Finished Jul 24 07:03:40 PM PDT 24
Peak memory 283900 kb
Host smart-3c633ef1-c443-481f-b2a6-310ca5eba457
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859458675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3859458675
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1423548357
Short name T637
Test name
Test status
Simulation time 29974486 ps
CPU time 0.91 seconds
Started Jul 24 07:01:00 PM PDT 24
Finished Jul 24 07:01:02 PM PDT 24
Peak memory 209024 kb
Host smart-f1f40df2-a2f7-4fd9-b936-447df794af55
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423548357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1423548357
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.4291671444
Short name T565
Test name
Test status
Simulation time 17633846 ps
CPU time 1.13 seconds
Started Jul 24 07:01:07 PM PDT 24
Finished Jul 24 07:01:08 PM PDT 24
Peak memory 209040 kb
Host smart-799558aa-5fa9-4f63-a637-f1454862d028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291671444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.4291671444
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2069489975
Short name T398
Test name
Test status
Simulation time 2855527246 ps
CPU time 15.72 seconds
Started Jul 24 07:01:05 PM PDT 24
Finished Jul 24 07:01:21 PM PDT 24
Peak memory 218428 kb
Host smart-71a48f6e-b8f3-4ca1-aded-5c8b2587b5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069489975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2069489975
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.938661308
Short name T821
Test name
Test status
Simulation time 732248099 ps
CPU time 5.52 seconds
Started Jul 24 07:01:07 PM PDT 24
Finished Jul 24 07:01:13 PM PDT 24
Peak memory 217400 kb
Host smart-aa158f38-7047-4209-b14d-407838730b2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938661308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.938661308
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1340695013
Short name T233
Test name
Test status
Simulation time 114911722 ps
CPU time 3.19 seconds
Started Jul 24 07:01:07 PM PDT 24
Finished Jul 24 07:01:10 PM PDT 24
Peak memory 218324 kb
Host smart-93e9030b-9206-4c0d-b2b1-e0b26ee64317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340695013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1340695013
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3285228440
Short name T619
Test name
Test status
Simulation time 1534822142 ps
CPU time 13.09 seconds
Started Jul 24 07:01:10 PM PDT 24
Finished Jul 24 07:01:24 PM PDT 24
Peak memory 219004 kb
Host smart-421a4b81-15fb-4f39-9954-7ff366443afe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285228440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3285228440
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2258080636
Short name T411
Test name
Test status
Simulation time 592672211 ps
CPU time 8.14 seconds
Started Jul 24 07:01:10 PM PDT 24
Finished Jul 24 07:01:18 PM PDT 24
Peak memory 226068 kb
Host smart-02f6c1f2-e0b8-496b-8f25-e6d47307375f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258080636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2258080636
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2059218962
Short name T698
Test name
Test status
Simulation time 598818422 ps
CPU time 7.85 seconds
Started Jul 24 07:01:11 PM PDT 24
Finished Jul 24 07:01:19 PM PDT 24
Peak memory 218232 kb
Host smart-cfe8b6eb-382d-4824-af92-e9d7905cced0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059218962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2059218962
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3553228001
Short name T634
Test name
Test status
Simulation time 6791927090 ps
CPU time 12.29 seconds
Started Jul 24 07:01:07 PM PDT 24
Finished Jul 24 07:01:19 PM PDT 24
Peak memory 226208 kb
Host smart-94fa6747-0c3d-4f13-bba5-0e3b525378b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553228001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3553228001
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1269362097
Short name T257
Test name
Test status
Simulation time 63026285 ps
CPU time 1.37 seconds
Started Jul 24 07:01:16 PM PDT 24
Finished Jul 24 07:01:18 PM PDT 24
Peak memory 217748 kb
Host smart-4bb42b1b-7905-4fe7-bff1-56c6d108156e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269362097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1269362097
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1985924163
Short name T504
Test name
Test status
Simulation time 850629685 ps
CPU time 18.5 seconds
Started Jul 24 07:01:11 PM PDT 24
Finished Jul 24 07:01:29 PM PDT 24
Peak memory 250984 kb
Host smart-15cb7d30-5beb-4b93-b0ae-4a1b1715e468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985924163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1985924163
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1586965141
Short name T520
Test name
Test status
Simulation time 274151439 ps
CPU time 7.36 seconds
Started Jul 24 07:01:07 PM PDT 24
Finished Jul 24 07:01:14 PM PDT 24
Peak memory 247252 kb
Host smart-bcbbb02a-2deb-4a3c-97c7-8c7c4e0661d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586965141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1586965141
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.218257926
Short name T35
Test name
Test status
Simulation time 11290610 ps
CPU time 0.9 seconds
Started Jul 24 07:01:10 PM PDT 24
Finished Jul 24 07:01:12 PM PDT 24
Peak memory 209052 kb
Host smart-eb23c742-a91a-4e69-84a9-b0981adde574
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218257926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.218257926
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1200013691
Short name T95
Test name
Test status
Simulation time 52404224 ps
CPU time 0.9 seconds
Started Jul 24 07:01:05 PM PDT 24
Finished Jul 24 07:01:06 PM PDT 24
Peak memory 208964 kb
Host smart-f7b15b75-10b4-44c9-a259-e9af2fcf25b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200013691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1200013691
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3521738474
Short name T53
Test name
Test status
Simulation time 446997363 ps
CPU time 12.49 seconds
Started Jul 24 07:01:10 PM PDT 24
Finished Jul 24 07:01:22 PM PDT 24
Peak memory 226136 kb
Host smart-17ed12b0-8fd9-44f4-8ac3-a4bc0deccaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521738474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3521738474
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2543606053
Short name T426
Test name
Test status
Simulation time 401750896 ps
CPU time 5.59 seconds
Started Jul 24 07:01:06 PM PDT 24
Finished Jul 24 07:01:12 PM PDT 24
Peak memory 217772 kb
Host smart-ae9f44aa-548f-4017-8c05-380e36e3d4e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543606053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2543606053
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2567508281
Short name T98
Test name
Test status
Simulation time 140399812 ps
CPU time 1.82 seconds
Started Jul 24 07:01:09 PM PDT 24
Finished Jul 24 07:01:11 PM PDT 24
Peak memory 222180 kb
Host smart-30770b0b-afe5-4e28-9b18-4b48bf8a2ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567508281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2567508281
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2320986867
Short name T593
Test name
Test status
Simulation time 330799515 ps
CPU time 11.32 seconds
Started Jul 24 07:01:08 PM PDT 24
Finished Jul 24 07:01:19 PM PDT 24
Peak memory 218436 kb
Host smart-c0aafe75-4bc2-49f1-8b7d-107f0878b616
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320986867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2320986867
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1905116807
Short name T559
Test name
Test status
Simulation time 1427009544 ps
CPU time 11.09 seconds
Started Jul 24 07:01:06 PM PDT 24
Finished Jul 24 07:01:18 PM PDT 24
Peak memory 226068 kb
Host smart-846a674a-2d35-468a-ad29-240aaf2544c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905116807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1905116807
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2397775352
Short name T391
Test name
Test status
Simulation time 269236148 ps
CPU time 6.71 seconds
Started Jul 24 07:01:09 PM PDT 24
Finished Jul 24 07:01:15 PM PDT 24
Peak memory 226068 kb
Host smart-75d21c4b-e2f9-4395-8559-7428a67abbd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397775352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2397775352
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.108261619
Short name T446
Test name
Test status
Simulation time 865449041 ps
CPU time 8.64 seconds
Started Jul 24 07:01:07 PM PDT 24
Finished Jul 24 07:01:16 PM PDT 24
Peak memory 226160 kb
Host smart-212e0db8-2a95-4310-9816-e056f5ebb3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108261619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.108261619
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1528297064
Short name T708
Test name
Test status
Simulation time 69056350 ps
CPU time 2.85 seconds
Started Jul 24 07:01:10 PM PDT 24
Finished Jul 24 07:01:13 PM PDT 24
Peak memory 214780 kb
Host smart-37d15f63-deb0-4963-ab0a-bc5a18da156f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528297064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1528297064
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3828327814
Short name T464
Test name
Test status
Simulation time 988584992 ps
CPU time 33.53 seconds
Started Jul 24 07:01:06 PM PDT 24
Finished Jul 24 07:01:40 PM PDT 24
Peak memory 250912 kb
Host smart-4e1a7329-631f-4b6f-9dc8-8d0e8d4f26f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828327814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3828327814
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2849452202
Short name T410
Test name
Test status
Simulation time 46783696 ps
CPU time 7.59 seconds
Started Jul 24 07:01:05 PM PDT 24
Finished Jul 24 07:01:13 PM PDT 24
Peak memory 243356 kb
Host smart-f628cc67-36f5-41b2-8609-b2a738731d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849452202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2849452202
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2102442653
Short name T693
Test name
Test status
Simulation time 6506875742 ps
CPU time 104.59 seconds
Started Jul 24 07:01:10 PM PDT 24
Finished Jul 24 07:02:55 PM PDT 24
Peak memory 251024 kb
Host smart-70b15897-33cf-4a1d-b8bf-ae1e5ccce860
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102442653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2102442653
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.2982384476
Short name T159
Test name
Test status
Simulation time 158349574059 ps
CPU time 1002.77 seconds
Started Jul 24 07:01:06 PM PDT 24
Finished Jul 24 07:17:49 PM PDT 24
Peak memory 495228 kb
Host smart-22f5261d-1900-4550-86eb-9ea2c1ecd237
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2982384476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.2982384476
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2003351847
Short name T866
Test name
Test status
Simulation time 46550942 ps
CPU time 0.9 seconds
Started Jul 24 07:01:07 PM PDT 24
Finished Jul 24 07:01:08 PM PDT 24
Peak memory 212048 kb
Host smart-8c62603e-874e-4478-96de-5229b450499b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003351847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2003351847
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.197164695
Short name T627
Test name
Test status
Simulation time 27346525 ps
CPU time 1.05 seconds
Started Jul 24 06:58:02 PM PDT 24
Finished Jul 24 06:58:03 PM PDT 24
Peak memory 208988 kb
Host smart-9a63533a-5542-431b-ab2e-b930496a5fb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197164695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.197164695
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3678950867
Short name T147
Test name
Test status
Simulation time 38557856 ps
CPU time 0.96 seconds
Started Jul 24 06:57:53 PM PDT 24
Finished Jul 24 06:57:54 PM PDT 24
Peak memory 208800 kb
Host smart-ea7ce59e-e6b2-48c6-80d7-12a40b229deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678950867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3678950867
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3185841235
Short name T616
Test name
Test status
Simulation time 894607567 ps
CPU time 12.01 seconds
Started Jul 24 06:58:04 PM PDT 24
Finished Jul 24 06:58:16 PM PDT 24
Peak memory 218320 kb
Host smart-5dee549e-8f05-40eb-b658-b51af3ce2f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185841235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3185841235
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.628391014
Short name T491
Test name
Test status
Simulation time 1626954145 ps
CPU time 11.42 seconds
Started Jul 24 06:57:55 PM PDT 24
Finished Jul 24 06:58:06 PM PDT 24
Peak memory 217824 kb
Host smart-e79b27ca-b436-4a49-a263-c81d52e4dae3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628391014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.628391014
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2956598444
Short name T57
Test name
Test status
Simulation time 8561358596 ps
CPU time 62.88 seconds
Started Jul 24 06:57:54 PM PDT 24
Finished Jul 24 06:58:57 PM PDT 24
Peak memory 218908 kb
Host smart-b077856f-f8a2-4f46-a395-8710de465ed8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956598444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2956598444
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2014524282
Short name T412
Test name
Test status
Simulation time 404450339 ps
CPU time 11.46 seconds
Started Jul 24 06:57:53 PM PDT 24
Finished Jul 24 06:58:05 PM PDT 24
Peak memory 217636 kb
Host smart-8d970b42-09ca-46f8-811d-135f93440078
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014524282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
014524282
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1890320967
Short name T418
Test name
Test status
Simulation time 603917520 ps
CPU time 16.08 seconds
Started Jul 24 06:57:53 PM PDT 24
Finished Jul 24 06:58:10 PM PDT 24
Peak memory 224688 kb
Host smart-5808968c-7a22-4049-80a1-234e301b0bd8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890320967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1890320967
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3038271135
Short name T451
Test name
Test status
Simulation time 1191964476 ps
CPU time 36.27 seconds
Started Jul 24 06:57:54 PM PDT 24
Finished Jul 24 06:58:30 PM PDT 24
Peak memory 217712 kb
Host smart-b4b8f429-f777-4722-bd94-3f017b3de1a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038271135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3038271135
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2843529943
Short name T640
Test name
Test status
Simulation time 900701875 ps
CPU time 4.91 seconds
Started Jul 24 06:57:53 PM PDT 24
Finished Jul 24 06:57:58 PM PDT 24
Peak memory 217684 kb
Host smart-7d4d8c17-317e-49db-a07c-db06353937a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843529943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2843529943
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1467354561
Short name T470
Test name
Test status
Simulation time 4620905867 ps
CPU time 64.94 seconds
Started Jul 24 06:57:53 PM PDT 24
Finished Jul 24 06:58:58 PM PDT 24
Peak memory 267616 kb
Host smart-81dc936e-dc27-498b-913b-027da641a017
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467354561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1467354561
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1813265872
Short name T691
Test name
Test status
Simulation time 2064301507 ps
CPU time 15.81 seconds
Started Jul 24 06:57:54 PM PDT 24
Finished Jul 24 06:58:10 PM PDT 24
Peak memory 224008 kb
Host smart-5f96181e-8c44-4aa4-9245-d559b41ac865
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813265872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1813265872
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2369809654
Short name T860
Test name
Test status
Simulation time 278463428 ps
CPU time 2.82 seconds
Started Jul 24 06:57:51 PM PDT 24
Finished Jul 24 06:57:54 PM PDT 24
Peak memory 218328 kb
Host smart-c35de005-a3b0-43c9-b692-172b027468c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369809654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2369809654
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2155618863
Short name T820
Test name
Test status
Simulation time 397316946 ps
CPU time 7.84 seconds
Started Jul 24 06:57:56 PM PDT 24
Finished Jul 24 06:58:04 PM PDT 24
Peak memory 217752 kb
Host smart-a8f876d9-067e-4360-9bff-085da4309a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155618863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2155618863
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.720159287
Short name T833
Test name
Test status
Simulation time 2379790669 ps
CPU time 17.33 seconds
Started Jul 24 06:58:03 PM PDT 24
Finished Jul 24 06:58:21 PM PDT 24
Peak memory 226168 kb
Host smart-72f16929-cf0d-446a-88ae-9ae82cc4b3bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720159287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.720159287
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2802357556
Short name T811
Test name
Test status
Simulation time 367129028 ps
CPU time 12.7 seconds
Started Jul 24 06:58:02 PM PDT 24
Finished Jul 24 06:58:14 PM PDT 24
Peak memory 226060 kb
Host smart-f5209375-3059-4b0b-a2f2-08c44ded0fcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802357556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2802357556
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1328892638
Short name T509
Test name
Test status
Simulation time 1205673653 ps
CPU time 10.1 seconds
Started Jul 24 06:57:55 PM PDT 24
Finished Jul 24 06:58:05 PM PDT 24
Peak memory 226104 kb
Host smart-40c82952-2b14-4a21-a867-841f8ac6e798
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328892638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
328892638
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2247393273
Short name T737
Test name
Test status
Simulation time 452390481 ps
CPU time 10.9 seconds
Started Jul 24 06:57:52 PM PDT 24
Finished Jul 24 06:58:03 PM PDT 24
Peak memory 218428 kb
Host smart-05b2ac0f-b5a3-49fe-bd78-c3a9c979fbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247393273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2247393273
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.4211643769
Short name T661
Test name
Test status
Simulation time 146837911 ps
CPU time 2.65 seconds
Started Jul 24 06:57:47 PM PDT 24
Finished Jul 24 06:57:49 PM PDT 24
Peak memory 214496 kb
Host smart-c223f0f2-6a13-419c-b850-525e95020738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211643769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.4211643769
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.440610308
Short name T606
Test name
Test status
Simulation time 6289425814 ps
CPU time 31.99 seconds
Started Jul 24 06:57:48 PM PDT 24
Finished Jul 24 06:58:21 PM PDT 24
Peak memory 251040 kb
Host smart-9d1dbe37-4f1b-4f61-b3ef-cc56fc7e9dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440610308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.440610308
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2484450444
Short name T556
Test name
Test status
Simulation time 107210594 ps
CPU time 6.47 seconds
Started Jul 24 06:57:51 PM PDT 24
Finished Jul 24 06:57:57 PM PDT 24
Peak memory 244844 kb
Host smart-dfbdcd8a-f860-46c7-b604-6fa374d77237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484450444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2484450444
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1899690118
Short name T378
Test name
Test status
Simulation time 2163460237 ps
CPU time 94.44 seconds
Started Jul 24 06:58:00 PM PDT 24
Finished Jul 24 06:59:35 PM PDT 24
Peak memory 248160 kb
Host smart-a91199bd-1b1e-4f4f-a841-df176e7ed3a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899690118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1899690118
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.2791272704
Short name T140
Test name
Test status
Simulation time 33871206279 ps
CPU time 472.87 seconds
Started Jul 24 06:57:59 PM PDT 24
Finished Jul 24 07:05:52 PM PDT 24
Peak memory 316696 kb
Host smart-a566be21-13c6-4c51-8ab6-4d1b09a9e199
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2791272704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.2791272704
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3569941199
Short name T404
Test name
Test status
Simulation time 91682542 ps
CPU time 0.79 seconds
Started Jul 24 06:57:49 PM PDT 24
Finished Jul 24 06:57:50 PM PDT 24
Peak memory 209052 kb
Host smart-f57b2ca8-1edd-4444-b695-e662c3cbebcb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569941199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.3569941199
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1076042323
Short name T488
Test name
Test status
Simulation time 52408454 ps
CPU time 0.91 seconds
Started Jul 24 07:01:18 PM PDT 24
Finished Jul 24 07:01:19 PM PDT 24
Peak memory 209016 kb
Host smart-eca3afbb-d0a5-4e15-b4b4-77d843604ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076042323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1076042323
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2766757323
Short name T249
Test name
Test status
Simulation time 1271763464 ps
CPU time 10.7 seconds
Started Jul 24 07:01:14 PM PDT 24
Finished Jul 24 07:01:24 PM PDT 24
Peak memory 218320 kb
Host smart-76d88511-f8ed-4307-b514-ed8d5f4040bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766757323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2766757323
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1583128597
Short name T553
Test name
Test status
Simulation time 3746210678 ps
CPU time 8.59 seconds
Started Jul 24 07:01:15 PM PDT 24
Finished Jul 24 07:01:24 PM PDT 24
Peak memory 217748 kb
Host smart-7522ab46-dd95-4188-a983-5c600a90d0f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583128597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1583128597
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.4284786292
Short name T270
Test name
Test status
Simulation time 219743902 ps
CPU time 3.03 seconds
Started Jul 24 07:01:14 PM PDT 24
Finished Jul 24 07:01:17 PM PDT 24
Peak memory 218352 kb
Host smart-80e7639c-8a07-4f9d-846f-78f70a9eb600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284786292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.4284786292
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1604909401
Short name T769
Test name
Test status
Simulation time 479043157 ps
CPU time 19.53 seconds
Started Jul 24 07:01:14 PM PDT 24
Finished Jul 24 07:01:34 PM PDT 24
Peak memory 226156 kb
Host smart-b493e4cd-affc-4ad3-b87f-7a35c38af6e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604909401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1604909401
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.571118650
Short name T580
Test name
Test status
Simulation time 902769476 ps
CPU time 11.26 seconds
Started Jul 24 07:01:14 PM PDT 24
Finished Jul 24 07:01:25 PM PDT 24
Peak memory 226096 kb
Host smart-83eeca7e-9a97-46a0-a726-8abde78acddb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571118650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_di
gest.571118650
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1820591504
Short name T805
Test name
Test status
Simulation time 1203449877 ps
CPU time 8.85 seconds
Started Jul 24 07:01:16 PM PDT 24
Finished Jul 24 07:01:25 PM PDT 24
Peak memory 218344 kb
Host smart-4a789b50-01c5-4d66-bf48-67c7a853b75b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820591504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1820591504
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.675372128
Short name T406
Test name
Test status
Simulation time 398847710 ps
CPU time 13.29 seconds
Started Jul 24 07:01:16 PM PDT 24
Finished Jul 24 07:01:30 PM PDT 24
Peak memory 218404 kb
Host smart-24a759ab-3838-4600-9b50-f7ba895d815a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675372128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.675372128
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1734437512
Short name T703
Test name
Test status
Simulation time 299698762 ps
CPU time 2.99 seconds
Started Jul 24 07:01:09 PM PDT 24
Finished Jul 24 07:01:12 PM PDT 24
Peak memory 217764 kb
Host smart-554907cd-339a-45fa-89e3-9cbafa00b521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734437512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1734437512
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1270021725
Short name T458
Test name
Test status
Simulation time 290568160 ps
CPU time 26.56 seconds
Started Jul 24 07:01:19 PM PDT 24
Finished Jul 24 07:01:45 PM PDT 24
Peak memory 250964 kb
Host smart-aa5da140-8535-4a9c-b95c-f61525b273b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270021725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1270021725
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1836255382
Short name T313
Test name
Test status
Simulation time 435852558 ps
CPU time 7.88 seconds
Started Jul 24 07:01:16 PM PDT 24
Finished Jul 24 07:01:24 PM PDT 24
Peak memory 246948 kb
Host smart-fdac410c-cdb1-4450-876d-fcb4931e663f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836255382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1836255382
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3875433965
Short name T85
Test name
Test status
Simulation time 11611289498 ps
CPU time 107.51 seconds
Started Jul 24 07:01:17 PM PDT 24
Finished Jul 24 07:03:05 PM PDT 24
Peak memory 278000 kb
Host smart-7d666e38-43cc-42df-8e44-46267ae444c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875433965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3875433965
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2053919940
Short name T269
Test name
Test status
Simulation time 40273230 ps
CPU time 0.82 seconds
Started Jul 24 07:01:16 PM PDT 24
Finished Jul 24 07:01:17 PM PDT 24
Peak memory 209008 kb
Host smart-df01a730-1caf-4548-bf94-6afa7689bd1d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053919940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2053919940
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2293997057
Short name T742
Test name
Test status
Simulation time 29884121 ps
CPU time 0.95 seconds
Started Jul 24 07:01:26 PM PDT 24
Finished Jul 24 07:01:27 PM PDT 24
Peak memory 209048 kb
Host smart-3604f1be-6242-4315-b6cc-85645e92f45f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293997057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2293997057
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.854264843
Short name T718
Test name
Test status
Simulation time 453396933 ps
CPU time 11.82 seconds
Started Jul 24 07:01:16 PM PDT 24
Finished Jul 24 07:01:28 PM PDT 24
Peak memory 218264 kb
Host smart-2303dfd2-2ef3-427f-a428-01a0302ab6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854264843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.854264843
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.883891909
Short name T660
Test name
Test status
Simulation time 273128741 ps
CPU time 7.32 seconds
Started Jul 24 07:01:21 PM PDT 24
Finished Jul 24 07:01:28 PM PDT 24
Peak memory 217160 kb
Host smart-88778372-123d-423c-9d25-24fa46dbaa34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883891909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.883891909
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3510088055
Short name T483
Test name
Test status
Simulation time 45406548 ps
CPU time 2.44 seconds
Started Jul 24 07:01:17 PM PDT 24
Finished Jul 24 07:01:20 PM PDT 24
Peak memory 218364 kb
Host smart-14660ed5-2b0f-4ff8-981e-d50eab64eca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510088055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3510088055
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1211261794
Short name T869
Test name
Test status
Simulation time 1374947016 ps
CPU time 14.02 seconds
Started Jul 24 07:01:21 PM PDT 24
Finished Jul 24 07:01:35 PM PDT 24
Peak memory 218980 kb
Host smart-f8f1e990-801b-4a99-ae06-cb3cd84b1eb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211261794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1211261794
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1104360223
Short name T42
Test name
Test status
Simulation time 1672967202 ps
CPU time 12.15 seconds
Started Jul 24 07:01:22 PM PDT 24
Finished Jul 24 07:01:34 PM PDT 24
Peak memory 226124 kb
Host smart-26f491cb-e071-459b-904b-6a131d45edad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104360223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1104360223
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1534722786
Short name T382
Test name
Test status
Simulation time 1357890524 ps
CPU time 7.63 seconds
Started Jul 24 07:01:29 PM PDT 24
Finished Jul 24 07:01:37 PM PDT 24
Peak memory 226020 kb
Host smart-5c385e07-9d39-43c2-8daa-7fb6db1a0d34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534722786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1534722786
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3323437719
Short name T445
Test name
Test status
Simulation time 814858635 ps
CPU time 7.45 seconds
Started Jul 24 07:01:14 PM PDT 24
Finished Jul 24 07:01:22 PM PDT 24
Peak memory 218420 kb
Host smart-5f350aac-003c-4115-af29-1d38f04af3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323437719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3323437719
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2522922078
Short name T280
Test name
Test status
Simulation time 268654402 ps
CPU time 1.66 seconds
Started Jul 24 07:01:15 PM PDT 24
Finished Jul 24 07:01:17 PM PDT 24
Peak memory 217736 kb
Host smart-de880bd3-1e5d-40d7-8a72-9d22e51a39a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522922078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2522922078
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.357688113
Short name T102
Test name
Test status
Simulation time 3199765406 ps
CPU time 32.85 seconds
Started Jul 24 07:01:15 PM PDT 24
Finished Jul 24 07:01:48 PM PDT 24
Peak memory 250948 kb
Host smart-880a656b-5d9b-412f-8eb6-c5c35b4c3f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357688113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.357688113
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1857963222
Short name T346
Test name
Test status
Simulation time 61895186 ps
CPU time 3.21 seconds
Started Jul 24 07:01:15 PM PDT 24
Finished Jul 24 07:01:19 PM PDT 24
Peak memory 222580 kb
Host smart-f76aef76-fb51-469d-8558-c61979f1a01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857963222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1857963222
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.3709003606
Short name T815
Test name
Test status
Simulation time 19607022448 ps
CPU time 140.34 seconds
Started Jul 24 07:01:24 PM PDT 24
Finished Jul 24 07:03:44 PM PDT 24
Peak memory 277468 kb
Host smart-01da68ad-0361-4cb0-80b2-28c6d6e02e46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709003606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.3709003606
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.497263677
Short name T143
Test name
Test status
Simulation time 15446462669 ps
CPU time 492.13 seconds
Started Jul 24 07:01:24 PM PDT 24
Finished Jul 24 07:09:36 PM PDT 24
Peak memory 267544 kb
Host smart-41e2ee9a-5496-4aad-8c7b-31bd49d95e34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=497263677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.497263677
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.911043348
Short name T463
Test name
Test status
Simulation time 14032429 ps
CPU time 1 seconds
Started Jul 24 07:01:15 PM PDT 24
Finished Jul 24 07:01:17 PM PDT 24
Peak memory 209096 kb
Host smart-be246024-7dc5-4a3b-922d-7473d1b72254
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911043348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.911043348
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3446326942
Short name T482
Test name
Test status
Simulation time 53544667 ps
CPU time 0.95 seconds
Started Jul 24 07:01:21 PM PDT 24
Finished Jul 24 07:01:22 PM PDT 24
Peak memory 208780 kb
Host smart-82479a3e-7c9c-4a36-801d-fd731b383e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446326942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3446326942
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3256679796
Short name T632
Test name
Test status
Simulation time 534396864 ps
CPU time 11.82 seconds
Started Jul 24 07:01:21 PM PDT 24
Finished Jul 24 07:01:33 PM PDT 24
Peak memory 226148 kb
Host smart-51727770-f428-4545-99b2-24d18431dec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256679796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3256679796
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3065352819
Short name T508
Test name
Test status
Simulation time 266496462 ps
CPU time 7.69 seconds
Started Jul 24 07:01:24 PM PDT 24
Finished Jul 24 07:01:32 PM PDT 24
Peak memory 217432 kb
Host smart-6e90aa9e-7fa9-4704-9acb-8519527c1844
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065352819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3065352819
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.391567084
Short name T793
Test name
Test status
Simulation time 113791861 ps
CPU time 3.06 seconds
Started Jul 24 07:01:21 PM PDT 24
Finished Jul 24 07:01:25 PM PDT 24
Peak memory 218324 kb
Host smart-3b8dc024-765d-4f09-8d5b-ceb40f46d687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391567084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.391567084
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1953002152
Short name T789
Test name
Test status
Simulation time 237429593 ps
CPU time 12.62 seconds
Started Jul 24 07:01:24 PM PDT 24
Finished Jul 24 07:01:37 PM PDT 24
Peak memory 218356 kb
Host smart-014cfcaa-737c-440e-9bb2-b59c63b1363e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953002152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1953002152
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.862468547
Short name T781
Test name
Test status
Simulation time 1664186815 ps
CPU time 12.66 seconds
Started Jul 24 07:01:20 PM PDT 24
Finished Jul 24 07:01:33 PM PDT 24
Peak memory 226060 kb
Host smart-bb6ce70d-cd88-4f6f-a578-3ef3687c092e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862468547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.862468547
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1065689365
Short name T47
Test name
Test status
Simulation time 1450958842 ps
CPU time 9.11 seconds
Started Jul 24 07:01:22 PM PDT 24
Finished Jul 24 07:01:32 PM PDT 24
Peak memory 218260 kb
Host smart-02fda757-aec0-4af6-b89f-29a9f5e66e31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065689365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1065689365
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.870361022
Short name T330
Test name
Test status
Simulation time 1051369306 ps
CPU time 6.75 seconds
Started Jul 24 07:01:23 PM PDT 24
Finished Jul 24 07:01:30 PM PDT 24
Peak memory 218428 kb
Host smart-c56c7183-f2f5-4554-9ad3-b6e565ff7b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870361022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.870361022
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1840972975
Short name T800
Test name
Test status
Simulation time 63255091 ps
CPU time 3.97 seconds
Started Jul 24 07:01:27 PM PDT 24
Finished Jul 24 07:01:32 PM PDT 24
Peak memory 217788 kb
Host smart-1d5ee8aa-0202-48fd-846b-d87fb4cf7c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840972975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1840972975
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.421543413
Short name T316
Test name
Test status
Simulation time 177474686 ps
CPU time 19.49 seconds
Started Jul 24 07:01:24 PM PDT 24
Finished Jul 24 07:01:44 PM PDT 24
Peak memory 245168 kb
Host smart-f0752cb1-64fb-4508-a3b5-714cb9da5961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421543413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.421543413
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2844770429
Short name T746
Test name
Test status
Simulation time 70068673 ps
CPU time 7.33 seconds
Started Jul 24 07:01:21 PM PDT 24
Finished Jul 24 07:01:29 PM PDT 24
Peak memory 243628 kb
Host smart-30d92aee-c636-47cb-809c-2e209eede7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844770429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2844770429
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.119395820
Short name T667
Test name
Test status
Simulation time 4835100674 ps
CPU time 203.01 seconds
Started Jul 24 07:01:21 PM PDT 24
Finished Jul 24 07:04:45 PM PDT 24
Peak memory 251052 kb
Host smart-45fd90fa-30a9-4cbb-8c20-533ae954e62b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119395820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.119395820
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3139056337
Short name T851
Test name
Test status
Simulation time 54778322 ps
CPU time 1.08 seconds
Started Jul 24 07:01:27 PM PDT 24
Finished Jul 24 07:01:29 PM PDT 24
Peak memory 217800 kb
Host smart-129f608d-07bf-4861-9719-2e640b278343
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139056337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3139056337
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.364507714
Short name T32
Test name
Test status
Simulation time 32706442 ps
CPU time 1.5 seconds
Started Jul 24 07:01:23 PM PDT 24
Finished Jul 24 07:01:24 PM PDT 24
Peak memory 208832 kb
Host smart-b822a8e3-e3fe-4901-9ec8-fa76b7c8f1e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364507714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.364507714
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1877693950
Short name T658
Test name
Test status
Simulation time 2077240336 ps
CPU time 13.71 seconds
Started Jul 24 07:01:24 PM PDT 24
Finished Jul 24 07:01:38 PM PDT 24
Peak memory 218352 kb
Host smart-965033d6-f8ea-4afb-916c-de3c700e05a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877693950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1877693950
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3408484162
Short name T396
Test name
Test status
Simulation time 101793700 ps
CPU time 2.01 seconds
Started Jul 24 07:01:24 PM PDT 24
Finished Jul 24 07:01:26 PM PDT 24
Peak memory 222240 kb
Host smart-df11b704-f56e-420c-b5a6-7c1601058931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408484162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3408484162
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2212609280
Short name T537
Test name
Test status
Simulation time 659706173 ps
CPU time 18.42 seconds
Started Jul 24 07:01:29 PM PDT 24
Finished Jul 24 07:01:47 PM PDT 24
Peak memory 218992 kb
Host smart-ff5b1177-80db-4aa7-a99e-eb4c80b78a29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212609280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2212609280
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.516244227
Short name T628
Test name
Test status
Simulation time 2066624392 ps
CPU time 15.22 seconds
Started Jul 24 07:01:22 PM PDT 24
Finished Jul 24 07:01:37 PM PDT 24
Peak memory 218272 kb
Host smart-e6037db9-459c-4ab2-97eb-02a68548448c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516244227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di
gest.516244227
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1209378337
Short name T643
Test name
Test status
Simulation time 1134704882 ps
CPU time 10.65 seconds
Started Jul 24 07:01:21 PM PDT 24
Finished Jul 24 07:01:32 PM PDT 24
Peak memory 218260 kb
Host smart-0df2e08b-fb67-4341-8f2a-683bb1c4ddda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209378337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1209378337
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1737037912
Short name T310
Test name
Test status
Simulation time 848388082 ps
CPU time 9.05 seconds
Started Jul 24 07:01:22 PM PDT 24
Finished Jul 24 07:01:31 PM PDT 24
Peak memory 226168 kb
Host smart-2e105e42-b767-4fc4-a125-2d18b6be1383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737037912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1737037912
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.57882255
Short name T202
Test name
Test status
Simulation time 42677999 ps
CPU time 1.04 seconds
Started Jul 24 07:01:21 PM PDT 24
Finished Jul 24 07:01:22 PM PDT 24
Peak memory 212260 kb
Host smart-883c621a-55e9-46b5-b8eb-c9d8c395abd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57882255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.57882255
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.508109903
Short name T225
Test name
Test status
Simulation time 582675372 ps
CPU time 36.11 seconds
Started Jul 24 07:01:27 PM PDT 24
Finished Jul 24 07:02:03 PM PDT 24
Peak memory 250976 kb
Host smart-e9afee19-cdb4-47a4-8c7e-2836112085e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508109903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.508109903
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3471584278
Short name T662
Test name
Test status
Simulation time 141540796 ps
CPU time 7.41 seconds
Started Jul 24 07:01:25 PM PDT 24
Finished Jul 24 07:01:32 PM PDT 24
Peak memory 242788 kb
Host smart-ed63ebbb-005b-45bf-a629-55693f1051d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471584278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3471584278
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2965343981
Short name T388
Test name
Test status
Simulation time 5737349689 ps
CPU time 114.79 seconds
Started Jul 24 07:01:24 PM PDT 24
Finished Jul 24 07:03:19 PM PDT 24
Peak memory 277164 kb
Host smart-db1d34a6-a679-43da-add4-ea2c8c34a9c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965343981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2965343981
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.2663883693
Short name T156
Test name
Test status
Simulation time 54265354035 ps
CPU time 281.07 seconds
Started Jul 24 07:01:22 PM PDT 24
Finished Jul 24 07:06:03 PM PDT 24
Peak memory 319896 kb
Host smart-a67a838b-ee24-43c5-b749-146d2ab05002
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2663883693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.2663883693
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1385940956
Short name T582
Test name
Test status
Simulation time 43872145 ps
CPU time 1.08 seconds
Started Jul 24 07:01:23 PM PDT 24
Finished Jul 24 07:01:24 PM PDT 24
Peak memory 211796 kb
Host smart-579a87c2-afa4-4ded-8938-7801937911f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385940956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1385940956
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3173350708
Short name T864
Test name
Test status
Simulation time 85492201 ps
CPU time 0.93 seconds
Started Jul 24 07:01:28 PM PDT 24
Finished Jul 24 07:01:30 PM PDT 24
Peak memory 209024 kb
Host smart-9aa978f7-e99c-4283-ae5b-8b2aa1cb2605
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173350708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3173350708
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.503757147
Short name T15
Test name
Test status
Simulation time 494687033 ps
CPU time 8.7 seconds
Started Jul 24 07:01:30 PM PDT 24
Finished Jul 24 07:01:39 PM PDT 24
Peak memory 218380 kb
Host smart-66b697eb-7e8b-4012-90d9-6fcaac8be115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503757147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.503757147
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.346102598
Short name T30
Test name
Test status
Simulation time 274223163 ps
CPU time 7.96 seconds
Started Jul 24 07:01:30 PM PDT 24
Finished Jul 24 07:01:38 PM PDT 24
Peak memory 217780 kb
Host smart-72a07e06-1cf8-4b54-b455-061b55f1400a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346102598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.346102598
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.987442127
Short name T689
Test name
Test status
Simulation time 163859536 ps
CPU time 2.15 seconds
Started Jul 24 07:01:34 PM PDT 24
Finished Jul 24 07:01:37 PM PDT 24
Peak memory 218412 kb
Host smart-ae9e0de3-395a-4120-a4c1-b8148ac995aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987442127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.987442127
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.4191979231
Short name T617
Test name
Test status
Simulation time 591672068 ps
CPU time 13.21 seconds
Started Jul 24 07:01:34 PM PDT 24
Finished Jul 24 07:01:47 PM PDT 24
Peak memory 219136 kb
Host smart-9435c273-1bbe-4a99-be52-9a4e0559af5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191979231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.4191979231
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1659979446
Short name T259
Test name
Test status
Simulation time 409505349 ps
CPU time 12.53 seconds
Started Jul 24 07:01:30 PM PDT 24
Finished Jul 24 07:01:43 PM PDT 24
Peak memory 226112 kb
Host smart-9f50267d-3ad0-4873-b1ae-4a5e3f364319
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659979446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1659979446
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.636359791
Short name T732
Test name
Test status
Simulation time 373511488 ps
CPU time 14.04 seconds
Started Jul 24 07:01:29 PM PDT 24
Finished Jul 24 07:01:43 PM PDT 24
Peak memory 218324 kb
Host smart-00ff3543-ead2-44b0-88cd-6cef0aed7d3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636359791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.636359791
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1513627507
Short name T193
Test name
Test status
Simulation time 421689238 ps
CPU time 8.83 seconds
Started Jul 24 07:01:29 PM PDT 24
Finished Jul 24 07:01:38 PM PDT 24
Peak memory 218416 kb
Host smart-f5b7b85d-ad15-4d4d-907e-487025db3b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513627507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1513627507
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2487193855
Short name T243
Test name
Test status
Simulation time 86296682 ps
CPU time 2.12 seconds
Started Jul 24 07:01:27 PM PDT 24
Finished Jul 24 07:01:30 PM PDT 24
Peak memory 223512 kb
Host smart-967795b8-6181-4203-b1c7-1aefc066f182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487193855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2487193855
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.786298179
Short name T230
Test name
Test status
Simulation time 158872306 ps
CPU time 16.56 seconds
Started Jul 24 07:01:30 PM PDT 24
Finished Jul 24 07:01:47 PM PDT 24
Peak memory 250920 kb
Host smart-78ce8e03-c3dd-492c-af38-929a441d642a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786298179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.786298179
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.4264927563
Short name T395
Test name
Test status
Simulation time 115863219 ps
CPU time 7.49 seconds
Started Jul 24 07:01:29 PM PDT 24
Finished Jul 24 07:01:37 PM PDT 24
Peak memory 250876 kb
Host smart-7576c810-87d0-4be3-bd65-1b9c234cde38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264927563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.4264927563
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.1378406927
Short name T441
Test name
Test status
Simulation time 8707851979 ps
CPU time 75.02 seconds
Started Jul 24 07:01:30 PM PDT 24
Finished Jul 24 07:02:45 PM PDT 24
Peak memory 250964 kb
Host smart-b0c7a3c0-18ba-4e21-9125-634a464ce600
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378406927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.1378406927
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.685271464
Short name T41
Test name
Test status
Simulation time 16098621 ps
CPU time 0.78 seconds
Started Jul 24 07:01:31 PM PDT 24
Finished Jul 24 07:01:32 PM PDT 24
Peak memory 208960 kb
Host smart-4a82fcc2-ea82-4276-a9d7-a9fa407593ad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685271464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.685271464
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.574003182
Short name T867
Test name
Test status
Simulation time 159128817 ps
CPU time 1.17 seconds
Started Jul 24 07:01:34 PM PDT 24
Finished Jul 24 07:01:36 PM PDT 24
Peak memory 209124 kb
Host smart-5055d829-ad86-4db9-8a82-1c67258b5f1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574003182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.574003182
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2457662773
Short name T707
Test name
Test status
Simulation time 800229329 ps
CPU time 16.91 seconds
Started Jul 24 07:01:34 PM PDT 24
Finished Jul 24 07:01:51 PM PDT 24
Peak memory 226160 kb
Host smart-b88541a1-7f2c-4632-9adc-e83e1490c35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457662773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2457662773
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1486660962
Short name T383
Test name
Test status
Simulation time 342800103 ps
CPU time 4.49 seconds
Started Jul 24 07:01:36 PM PDT 24
Finished Jul 24 07:01:41 PM PDT 24
Peak memory 217768 kb
Host smart-294c4228-0f46-4ecb-8c4f-974e9ec4891e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486660962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1486660962
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2878542743
Short name T370
Test name
Test status
Simulation time 57785649 ps
CPU time 3.43 seconds
Started Jul 24 07:01:38 PM PDT 24
Finished Jul 24 07:01:42 PM PDT 24
Peak memory 222656 kb
Host smart-2e42dfdf-af58-42ae-908c-c64a88159267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878542743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2878542743
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.273077848
Short name T432
Test name
Test status
Simulation time 2503078026 ps
CPU time 19.16 seconds
Started Jul 24 07:01:36 PM PDT 24
Finished Jul 24 07:01:55 PM PDT 24
Peak memory 219248 kb
Host smart-05571b51-a8a6-44a4-9bdb-deacc59939c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273077848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.273077848
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3037913560
Short name T562
Test name
Test status
Simulation time 1464642495 ps
CPU time 7.65 seconds
Started Jul 24 07:01:37 PM PDT 24
Finished Jul 24 07:01:45 PM PDT 24
Peak memory 226100 kb
Host smart-41251e4d-22dd-4a9a-b34a-a48f46f6f9f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037913560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3037913560
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3751453697
Short name T868
Test name
Test status
Simulation time 338990309 ps
CPU time 13.24 seconds
Started Jul 24 07:01:34 PM PDT 24
Finished Jul 24 07:01:47 PM PDT 24
Peak memory 218276 kb
Host smart-cfc30630-ca97-4ff1-80a5-b16b5d2a4105
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751453697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3751453697
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3952440691
Short name T726
Test name
Test status
Simulation time 1837144103 ps
CPU time 13.33 seconds
Started Jul 24 07:01:38 PM PDT 24
Finished Jul 24 07:01:52 PM PDT 24
Peak memory 218428 kb
Host smart-a47c96a7-1000-4968-8c11-2835f04c7134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952440691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3952440691
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.4092649750
Short name T362
Test name
Test status
Simulation time 41819609 ps
CPU time 2.48 seconds
Started Jul 24 07:01:34 PM PDT 24
Finished Jul 24 07:01:36 PM PDT 24
Peak memory 214544 kb
Host smart-d1747133-4a98-4217-be38-d3295ebb208a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092649750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.4092649750
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3497769321
Short name T300
Test name
Test status
Simulation time 327996486 ps
CPU time 24.87 seconds
Started Jul 24 07:01:37 PM PDT 24
Finished Jul 24 07:02:02 PM PDT 24
Peak memory 250992 kb
Host smart-2bd40469-1c78-4179-8d5f-56fff8300a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497769321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3497769321
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.737170863
Short name T206
Test name
Test status
Simulation time 67381394 ps
CPU time 8.11 seconds
Started Jul 24 07:01:35 PM PDT 24
Finished Jul 24 07:01:44 PM PDT 24
Peak memory 250980 kb
Host smart-5ecc015e-c99c-455e-8f77-70fd3405aac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737170863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.737170863
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3768159165
Short name T34
Test name
Test status
Simulation time 20287572911 ps
CPU time 144.47 seconds
Started Jul 24 07:01:34 PM PDT 24
Finished Jul 24 07:03:59 PM PDT 24
Peak memory 219796 kb
Host smart-b9334509-b0b3-48eb-8d24-0feb4dcbccad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768159165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3768159165
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1929997641
Short name T515
Test name
Test status
Simulation time 46104579 ps
CPU time 0.94 seconds
Started Jul 24 07:02:03 PM PDT 24
Finished Jul 24 07:02:04 PM PDT 24
Peak memory 212060 kb
Host smart-3a8ad358-ec0a-48c9-8423-8a85bf0150b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929997641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1929997641
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3791726316
Short name T79
Test name
Test status
Simulation time 21072390 ps
CPU time 1.08 seconds
Started Jul 24 07:01:41 PM PDT 24
Finished Jul 24 07:01:42 PM PDT 24
Peak memory 209068 kb
Host smart-85bbb94a-54ed-4eac-9d7f-3e1bb122f062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791726316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3791726316
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.100570430
Short name T568
Test name
Test status
Simulation time 1791278336 ps
CPU time 8.53 seconds
Started Jul 24 07:01:36 PM PDT 24
Finished Jul 24 07:01:45 PM PDT 24
Peak memory 218324 kb
Host smart-6b354c69-b818-4ee4-8f83-2e45c3e7c951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100570430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.100570430
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.4144161432
Short name T852
Test name
Test status
Simulation time 124665084 ps
CPU time 1.19 seconds
Started Jul 24 07:01:35 PM PDT 24
Finished Jul 24 07:01:36 PM PDT 24
Peak memory 217264 kb
Host smart-c3d5f563-e19b-4f74-a562-6325a5b17f0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144161432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.4144161432
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2787379104
Short name T715
Test name
Test status
Simulation time 52109878 ps
CPU time 3.23 seconds
Started Jul 24 07:01:35 PM PDT 24
Finished Jul 24 07:01:38 PM PDT 24
Peak memory 218240 kb
Host smart-6769ac63-f717-475e-a75c-6909bea5016a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787379104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2787379104
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3196306989
Short name T551
Test name
Test status
Simulation time 387968625 ps
CPU time 18.22 seconds
Started Jul 24 07:01:34 PM PDT 24
Finished Jul 24 07:01:52 PM PDT 24
Peak memory 219024 kb
Host smart-a8fa5d2c-5707-4632-9441-81d03f8e3eaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196306989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3196306989
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1171615117
Short name T493
Test name
Test status
Simulation time 1313270626 ps
CPU time 10.09 seconds
Started Jul 24 07:01:41 PM PDT 24
Finished Jul 24 07:01:51 PM PDT 24
Peak memory 226088 kb
Host smart-752cc5ca-95dd-424a-a787-51ea2f122309
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171615117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1171615117
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3096019080
Short name T597
Test name
Test status
Simulation time 477464502 ps
CPU time 7.49 seconds
Started Jul 24 07:01:36 PM PDT 24
Finished Jul 24 07:01:44 PM PDT 24
Peak memory 226088 kb
Host smart-5f13cfcb-db25-41ba-9104-c4c7b61ab228
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096019080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3096019080
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3926319683
Short name T460
Test name
Test status
Simulation time 263326611 ps
CPU time 11.13 seconds
Started Jul 24 07:01:48 PM PDT 24
Finished Jul 24 07:01:59 PM PDT 24
Peak memory 218400 kb
Host smart-de5637fe-064b-4d28-9a01-0a3d88642573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926319683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3926319683
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2972624319
Short name T372
Test name
Test status
Simulation time 44781205 ps
CPU time 2.93 seconds
Started Jul 24 07:01:39 PM PDT 24
Finished Jul 24 07:01:42 PM PDT 24
Peak memory 217780 kb
Host smart-c2103dff-216a-43b8-affb-122ae494488e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972624319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2972624319
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3600030313
Short name T682
Test name
Test status
Simulation time 246895207 ps
CPU time 28.87 seconds
Started Jul 24 07:01:34 PM PDT 24
Finished Jul 24 07:02:03 PM PDT 24
Peak memory 247552 kb
Host smart-ac8cbfa4-12ce-4596-915f-4983bba8e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600030313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3600030313
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.4239644288
Short name T610
Test name
Test status
Simulation time 381261602 ps
CPU time 7.03 seconds
Started Jul 24 07:01:36 PM PDT 24
Finished Jul 24 07:01:43 PM PDT 24
Peak memory 250988 kb
Host smart-c9b1a852-1ce0-419b-b7d9-e8b8138f8dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239644288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.4239644288
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1731813982
Short name T87
Test name
Test status
Simulation time 27999541624 ps
CPU time 94.4 seconds
Started Jul 24 07:01:41 PM PDT 24
Finished Jul 24 07:03:16 PM PDT 24
Peak memory 226176 kb
Host smart-75fe7671-7f68-40fb-93ea-ea8015769215
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731813982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1731813982
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.1678876981
Short name T853
Test name
Test status
Simulation time 135993572781 ps
CPU time 351.89 seconds
Started Jul 24 07:01:40 PM PDT 24
Finished Jul 24 07:07:33 PM PDT 24
Peak memory 282544 kb
Host smart-32a74935-b309-4d37-9b49-1839962643ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1678876981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.1678876981
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3284191415
Short name T549
Test name
Test status
Simulation time 38683313 ps
CPU time 0.8 seconds
Started Jul 24 07:01:42 PM PDT 24
Finished Jul 24 07:01:44 PM PDT 24
Peak memory 207264 kb
Host smart-4a075894-63a5-4307-847f-4f7ba63ed325
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284191415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3284191415
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2630075361
Short name T364
Test name
Test status
Simulation time 20902143 ps
CPU time 0.94 seconds
Started Jul 24 07:01:40 PM PDT 24
Finished Jul 24 07:01:42 PM PDT 24
Peak memory 208968 kb
Host smart-3ecc3944-facb-4094-a5ce-990e4a0e5173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630075361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2630075361
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.309661770
Short name T375
Test name
Test status
Simulation time 426778771 ps
CPU time 13.25 seconds
Started Jul 24 07:01:48 PM PDT 24
Finished Jul 24 07:02:01 PM PDT 24
Peak memory 218332 kb
Host smart-d283754b-5b0a-4a1f-ae62-1076b1543a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309661770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.309661770
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1161151267
Short name T809
Test name
Test status
Simulation time 135519879 ps
CPU time 2.67 seconds
Started Jul 24 07:01:40 PM PDT 24
Finished Jul 24 07:01:42 PM PDT 24
Peak memory 217768 kb
Host smart-fcc8c23f-5718-427d-97a3-ba8e50802ad9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161151267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.1161151267
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.276389991
Short name T195
Test name
Test status
Simulation time 141833779 ps
CPU time 3.63 seconds
Started Jul 24 07:01:39 PM PDT 24
Finished Jul 24 07:01:42 PM PDT 24
Peak memory 218296 kb
Host smart-c06d1fbf-565a-4488-97aa-48cecb76c034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276389991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.276389991
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.355647990
Short name T100
Test name
Test status
Simulation time 222586543 ps
CPU time 8.74 seconds
Started Jul 24 07:01:44 PM PDT 24
Finished Jul 24 07:01:53 PM PDT 24
Peak memory 218568 kb
Host smart-95029dfd-9ec3-44cc-b15f-65dbc28c061a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355647990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.355647990
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2893224732
Short name T768
Test name
Test status
Simulation time 1055856295 ps
CPU time 10.27 seconds
Started Jul 24 07:01:41 PM PDT 24
Finished Jul 24 07:01:51 PM PDT 24
Peak memory 226088 kb
Host smart-cb8c6ed9-ae14-4632-8e8e-8a91da1cd33a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893224732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2893224732
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1944723608
Short name T642
Test name
Test status
Simulation time 333249896 ps
CPU time 10.94 seconds
Started Jul 24 07:01:42 PM PDT 24
Finished Jul 24 07:01:54 PM PDT 24
Peak memory 218404 kb
Host smart-300d9eca-eeff-4e33-a9c2-0e581b05a0bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944723608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1944723608
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.841067420
Short name T681
Test name
Test status
Simulation time 723023732 ps
CPU time 10.92 seconds
Started Jul 24 07:01:43 PM PDT 24
Finished Jul 24 07:01:54 PM PDT 24
Peak memory 225348 kb
Host smart-5b91ed5f-2df9-431c-beda-5dd21cd308e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841067420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.841067420
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2654836930
Short name T495
Test name
Test status
Simulation time 41999215 ps
CPU time 1.57 seconds
Started Jul 24 07:01:41 PM PDT 24
Finished Jul 24 07:01:43 PM PDT 24
Peak memory 217752 kb
Host smart-f5c6a3fe-9e36-4cd0-8af0-f6ac8e3edcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654836930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2654836930
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2938401955
Short name T499
Test name
Test status
Simulation time 341954291 ps
CPU time 44.64 seconds
Started Jul 24 07:01:42 PM PDT 24
Finished Jul 24 07:02:27 PM PDT 24
Peak memory 249720 kb
Host smart-a6d3bafc-c185-48e4-826c-cb319210ed58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938401955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2938401955
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2073772827
Short name T855
Test name
Test status
Simulation time 93196557 ps
CPU time 3.2 seconds
Started Jul 24 07:01:41 PM PDT 24
Finished Jul 24 07:01:45 PM PDT 24
Peak memory 222524 kb
Host smart-a0260325-25fb-4151-a056-c1bd80982c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073772827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2073772827
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3842280050
Short name T469
Test name
Test status
Simulation time 30273472901 ps
CPU time 156.29 seconds
Started Jul 24 07:01:41 PM PDT 24
Finished Jul 24 07:04:18 PM PDT 24
Peak memory 268016 kb
Host smart-981c65d5-e519-41e8-b518-ae3637a78e8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842280050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3842280050
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1873127018
Short name T218
Test name
Test status
Simulation time 35287004 ps
CPU time 1.15 seconds
Started Jul 24 07:01:41 PM PDT 24
Finished Jul 24 07:01:43 PM PDT 24
Peak memory 217960 kb
Host smart-b3b88c00-f99b-4469-8092-b5063b937972
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873127018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1873127018
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3607996640
Short name T309
Test name
Test status
Simulation time 24595181 ps
CPU time 0.98 seconds
Started Jul 24 07:01:52 PM PDT 24
Finished Jul 24 07:01:53 PM PDT 24
Peak memory 209044 kb
Host smart-022e5edc-1551-4e73-ad11-52406a2ebf81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607996640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3607996640
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3763986749
Short name T615
Test name
Test status
Simulation time 2771357875 ps
CPU time 18.24 seconds
Started Jul 24 07:01:43 PM PDT 24
Finished Jul 24 07:02:01 PM PDT 24
Peak memory 226208 kb
Host smart-4fcac6cd-5728-46ab-a373-382dccb0c831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763986749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3763986749
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2568063510
Short name T373
Test name
Test status
Simulation time 39618500 ps
CPU time 1.21 seconds
Started Jul 24 07:01:49 PM PDT 24
Finished Jul 24 07:01:50 PM PDT 24
Peak memory 217240 kb
Host smart-edfdb45e-3cba-425a-a75b-5e732f8293b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568063510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2568063510
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.600718741
Short name T99
Test name
Test status
Simulation time 124443769 ps
CPU time 3.58 seconds
Started Jul 24 07:01:41 PM PDT 24
Finished Jul 24 07:01:45 PM PDT 24
Peak memory 222612 kb
Host smart-f5bc38b0-f408-4811-a29e-6a61672bc0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600718741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.600718741
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3667990292
Short name T293
Test name
Test status
Simulation time 279116184 ps
CPU time 10.21 seconds
Started Jul 24 07:01:53 PM PDT 24
Finished Jul 24 07:02:03 PM PDT 24
Peak memory 225652 kb
Host smart-ce60452d-e59e-42a9-be7d-9c6c8a3f7cdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667990292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3667990292
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3753434331
Short name T194
Test name
Test status
Simulation time 324269505 ps
CPU time 14.09 seconds
Started Jul 24 07:02:07 PM PDT 24
Finished Jul 24 07:02:21 PM PDT 24
Peak memory 226048 kb
Host smart-3b6b9558-fced-4a6d-a8ef-6c42ad389a25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753434331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3753434331
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3033318410
Short name T735
Test name
Test status
Simulation time 695996068 ps
CPU time 12.99 seconds
Started Jul 24 07:02:07 PM PDT 24
Finished Jul 24 07:02:20 PM PDT 24
Peak memory 226048 kb
Host smart-0c3b45fc-5776-4e83-808e-9b3fd464e98f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033318410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3033318410
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.170274000
Short name T721
Test name
Test status
Simulation time 303674205 ps
CPU time 10.06 seconds
Started Jul 24 07:01:47 PM PDT 24
Finished Jul 24 07:01:58 PM PDT 24
Peak memory 218420 kb
Host smart-e041bfd6-5242-4057-8ede-15d2e64f3102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170274000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.170274000
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2949222877
Short name T89
Test name
Test status
Simulation time 24529546 ps
CPU time 2.02 seconds
Started Jul 24 07:01:42 PM PDT 24
Finished Jul 24 07:01:44 PM PDT 24
Peak memory 214128 kb
Host smart-11549b63-a172-4a52-96dc-3e3166299b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949222877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2949222877
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.4242653597
Short name T812
Test name
Test status
Simulation time 660024727 ps
CPU time 19.71 seconds
Started Jul 24 07:01:40 PM PDT 24
Finished Jul 24 07:02:00 PM PDT 24
Peak memory 251060 kb
Host smart-5395fcb4-2333-4700-b03e-8231a1e58045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242653597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.4242653597
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.494016868
Short name T315
Test name
Test status
Simulation time 76951414 ps
CPU time 10 seconds
Started Jul 24 07:01:40 PM PDT 24
Finished Jul 24 07:01:51 PM PDT 24
Peak memory 250884 kb
Host smart-75e03e35-33d1-4412-9aa1-fe1caca5791e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494016868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.494016868
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.124557970
Short name T443
Test name
Test status
Simulation time 1328302476 ps
CPU time 47.32 seconds
Started Jul 24 07:01:50 PM PDT 24
Finished Jul 24 07:02:38 PM PDT 24
Peak memory 250896 kb
Host smart-5d5e46be-f3a9-44d3-8ba0-ad39b0bb96d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124557970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.124557970
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1180291415
Short name T358
Test name
Test status
Simulation time 14238399 ps
CPU time 0.81 seconds
Started Jul 24 07:01:41 PM PDT 24
Finished Jul 24 07:01:42 PM PDT 24
Peak memory 209148 kb
Host smart-bf286874-be15-466f-b8b8-1052fdc824e4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180291415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1180291415
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3459138176
Short name T94
Test name
Test status
Simulation time 29587071 ps
CPU time 0.86 seconds
Started Jul 24 07:01:53 PM PDT 24
Finished Jul 24 07:01:54 PM PDT 24
Peak memory 208992 kb
Host smart-d29a0ab4-8b11-407a-98fd-cc08544edec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459138176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3459138176
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1320439267
Short name T467
Test name
Test status
Simulation time 2249188495 ps
CPU time 10.78 seconds
Started Jul 24 07:01:49 PM PDT 24
Finished Jul 24 07:02:00 PM PDT 24
Peak memory 218376 kb
Host smart-c0e53b7a-7123-4bdf-a359-54fc0b38e915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320439267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1320439267
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2063044252
Short name T437
Test name
Test status
Simulation time 6737809622 ps
CPU time 7.43 seconds
Started Jul 24 07:01:46 PM PDT 24
Finished Jul 24 07:01:54 PM PDT 24
Peak memory 217832 kb
Host smart-7449ec6a-e34e-461b-b378-82b4118f9b1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063044252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2063044252
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.305501254
Short name T152
Test name
Test status
Simulation time 215310907 ps
CPU time 3.3 seconds
Started Jul 24 07:01:51 PM PDT 24
Finished Jul 24 07:01:55 PM PDT 24
Peak memory 218312 kb
Host smart-c9c13d65-1232-45a9-a7a3-2e519397a455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305501254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.305501254
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.221222889
Short name T570
Test name
Test status
Simulation time 639175489 ps
CPU time 13.54 seconds
Started Jul 24 07:01:48 PM PDT 24
Finished Jul 24 07:02:02 PM PDT 24
Peak memory 226092 kb
Host smart-c69a2f60-9e34-4362-9658-604062d1d941
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221222889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.221222889
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3019826547
Short name T45
Test name
Test status
Simulation time 1911807424 ps
CPU time 15.72 seconds
Started Jul 24 07:01:50 PM PDT 24
Finished Jul 24 07:02:06 PM PDT 24
Peak memory 218400 kb
Host smart-4362b48d-7cc3-4018-ba1a-849f3eb4f780
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019826547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.3019826547
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.287701346
Short name T675
Test name
Test status
Simulation time 670064384 ps
CPU time 20.19 seconds
Started Jul 24 07:01:46 PM PDT 24
Finished Jul 24 07:02:07 PM PDT 24
Peak memory 226080 kb
Host smart-27af7b73-a8ce-4368-97aa-c6a51e187918
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287701346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.287701346
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.57157993
Short name T587
Test name
Test status
Simulation time 284273398 ps
CPU time 8.13 seconds
Started Jul 24 07:01:49 PM PDT 24
Finished Jul 24 07:01:58 PM PDT 24
Peak memory 218444 kb
Host smart-19ddfb80-86f5-4973-b811-07701c638ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57157993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.57157993
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3761801177
Short name T828
Test name
Test status
Simulation time 52536450 ps
CPU time 2.59 seconds
Started Jul 24 07:01:48 PM PDT 24
Finished Jul 24 07:01:50 PM PDT 24
Peak memory 214556 kb
Host smart-6685c84b-3965-4127-a121-93ddc751576d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761801177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3761801177
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.678401782
Short name T825
Test name
Test status
Simulation time 742587381 ps
CPU time 25.35 seconds
Started Jul 24 07:02:00 PM PDT 24
Finished Jul 24 07:02:26 PM PDT 24
Peak memory 247200 kb
Host smart-c7ae10da-e5c5-474f-9102-087c8e7b52cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678401782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.678401782
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3559055346
Short name T571
Test name
Test status
Simulation time 270456711 ps
CPU time 6.33 seconds
Started Jul 24 07:01:47 PM PDT 24
Finished Jul 24 07:01:54 PM PDT 24
Peak memory 250564 kb
Host smart-612f9c0a-72f5-4320-800f-f4b41b739091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559055346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3559055346
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2764475376
Short name T802
Test name
Test status
Simulation time 39773510301 ps
CPU time 267.73 seconds
Started Jul 24 07:01:54 PM PDT 24
Finished Jul 24 07:06:21 PM PDT 24
Peak memory 251036 kb
Host smart-0c6185d6-3258-40c0-95e2-aaa6ff0831ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764475376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2764475376
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3689574650
Short name T208
Test name
Test status
Simulation time 37378139 ps
CPU time 0.9 seconds
Started Jul 24 07:01:47 PM PDT 24
Finished Jul 24 07:01:48 PM PDT 24
Peak memory 208964 kb
Host smart-01349f81-12c3-4317-abc3-3f90d891b15c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689574650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3689574650
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1904327240
Short name T745
Test name
Test status
Simulation time 47172760 ps
CPU time 1.34 seconds
Started Jul 24 06:58:08 PM PDT 24
Finished Jul 24 06:58:09 PM PDT 24
Peak memory 209100 kb
Host smart-ab774447-4028-4429-a34a-940cca227685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904327240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1904327240
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.916259794
Short name T638
Test name
Test status
Simulation time 243820880 ps
CPU time 11.04 seconds
Started Jul 24 06:58:01 PM PDT 24
Finished Jul 24 06:58:12 PM PDT 24
Peak memory 218320 kb
Host smart-97793cb0-3e71-4b34-bcd9-1fed52ccd240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916259794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.916259794
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2638767734
Short name T371
Test name
Test status
Simulation time 445528713 ps
CPU time 6.09 seconds
Started Jul 24 06:58:10 PM PDT 24
Finished Jul 24 06:58:16 PM PDT 24
Peak memory 217752 kb
Host smart-5edb2dab-3253-46c9-8da8-f17d9ba37c88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638767734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2638767734
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.3837785848
Short name T843
Test name
Test status
Simulation time 7035213696 ps
CPU time 55.58 seconds
Started Jul 24 06:58:03 PM PDT 24
Finished Jul 24 06:58:58 PM PDT 24
Peak memory 219008 kb
Host smart-86b1414b-4614-4334-9a5a-f565900aa1d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837785848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.3837785848
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3489927634
Short name T367
Test name
Test status
Simulation time 3104027216 ps
CPU time 15.33 seconds
Started Jul 24 06:57:59 PM PDT 24
Finished Jul 24 06:58:15 PM PDT 24
Peak memory 217900 kb
Host smart-e6548a2b-c42b-4a5a-920d-abeb6277ed69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489927634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
489927634
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2350835418
Short name T725
Test name
Test status
Simulation time 245233154 ps
CPU time 1.97 seconds
Started Jul 24 06:58:00 PM PDT 24
Finished Jul 24 06:58:02 PM PDT 24
Peak memory 218292 kb
Host smart-869105c6-80d6-4a71-a176-4ae80fbea675
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350835418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2350835418
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.4082256225
Short name T4
Test name
Test status
Simulation time 1448095439 ps
CPU time 23.8 seconds
Started Jul 24 06:58:07 PM PDT 24
Finished Jul 24 06:58:31 PM PDT 24
Peak memory 217708 kb
Host smart-091dbfeb-cda9-4237-b4a8-4ab12b74d704
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082256225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.4082256225
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.2495525992
Short name T33
Test name
Test status
Simulation time 2025001746 ps
CPU time 13.6 seconds
Started Jul 24 06:57:59 PM PDT 24
Finished Jul 24 06:58:13 PM PDT 24
Peak memory 217656 kb
Host smart-c1301cd8-29e9-4e72-9a0b-5a6018ac4359
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495525992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
2495525992
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1618920192
Short name T626
Test name
Test status
Simulation time 7020638462 ps
CPU time 40.41 seconds
Started Jul 24 06:58:00 PM PDT 24
Finished Jul 24 06:58:40 PM PDT 24
Peak memory 251008 kb
Host smart-75762868-a632-42c6-8d34-db86b79ad81b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618920192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1618920192
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3438357592
Short name T646
Test name
Test status
Simulation time 987556578 ps
CPU time 21.27 seconds
Started Jul 24 06:57:59 PM PDT 24
Finished Jul 24 06:58:21 PM PDT 24
Peak memory 250912 kb
Host smart-f5ff2058-d372-49f2-be0b-58a5a7d86686
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438357592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3438357592
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1204568624
Short name T69
Test name
Test status
Simulation time 63058567 ps
CPU time 2.96 seconds
Started Jul 24 06:58:03 PM PDT 24
Finished Jul 24 06:58:06 PM PDT 24
Peak memory 222412 kb
Host smart-e7ed09e0-8125-4817-8759-d56f3d7bbc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204568624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1204568624
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1767607531
Short name T286
Test name
Test status
Simulation time 1029114305 ps
CPU time 17.03 seconds
Started Jul 24 06:58:06 PM PDT 24
Finished Jul 24 06:58:24 PM PDT 24
Peak memory 226160 kb
Host smart-65e77159-c543-4576-a9ad-c46aa4b44bdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767607531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1767607531
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3267265779
Short name T755
Test name
Test status
Simulation time 764823285 ps
CPU time 15.8 seconds
Started Jul 24 06:58:07 PM PDT 24
Finished Jul 24 06:58:23 PM PDT 24
Peak memory 226036 kb
Host smart-5e5a18b1-cce9-479a-b7be-da88acbc1cb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267265779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3267265779
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3027777100
Short name T158
Test name
Test status
Simulation time 1219185954 ps
CPU time 21.73 seconds
Started Jul 24 06:58:07 PM PDT 24
Finished Jul 24 06:58:29 PM PDT 24
Peak memory 226040 kb
Host smart-d025e5be-6fc7-4642-aee3-256cec4390a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027777100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
027777100
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1590654676
Short name T484
Test name
Test status
Simulation time 1065005857 ps
CPU time 6.8 seconds
Started Jul 24 06:58:02 PM PDT 24
Finished Jul 24 06:58:09 PM PDT 24
Peak memory 218400 kb
Host smart-b88826d0-91e0-4c01-a167-06f1d7ea70d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590654676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1590654676
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.4059815117
Short name T380
Test name
Test status
Simulation time 62247236 ps
CPU time 2.49 seconds
Started Jul 24 06:58:03 PM PDT 24
Finished Jul 24 06:58:05 PM PDT 24
Peak memory 214572 kb
Host smart-9aba39b4-543e-4eed-b65b-860078420e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059815117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.4059815117
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.239985122
Short name T719
Test name
Test status
Simulation time 243331150 ps
CPU time 6.52 seconds
Started Jul 24 06:58:00 PM PDT 24
Finished Jul 24 06:58:07 PM PDT 24
Peak memory 246932 kb
Host smart-5a94b166-6fa4-4338-8f73-5134878bfd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239985122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.239985122
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3147095307
Short name T579
Test name
Test status
Simulation time 9858516031 ps
CPU time 201.62 seconds
Started Jul 24 06:58:09 PM PDT 24
Finished Jul 24 07:01:31 PM PDT 24
Peak memory 272700 kb
Host smart-9e4a78ed-504f-4426-bb78-d41ae0443206
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147095307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3147095307
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1467210378
Short name T519
Test name
Test status
Simulation time 181692816 ps
CPU time 0.79 seconds
Started Jul 24 06:57:59 PM PDT 24
Finished Jul 24 06:58:00 PM PDT 24
Peak memory 209116 kb
Host smart-d2a831ce-916d-40b5-8bc9-d4f2e232acb2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467210378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1467210378
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2583188306
Short name T352
Test name
Test status
Simulation time 53128650 ps
CPU time 1.04 seconds
Started Jul 24 06:58:12 PM PDT 24
Finished Jul 24 06:58:13 PM PDT 24
Peak memory 209048 kb
Host smart-40ffb4dd-be70-4180-8641-126fa193dcf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583188306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2583188306
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2994999306
Short name T773
Test name
Test status
Simulation time 856486677 ps
CPU time 9.54 seconds
Started Jul 24 06:58:06 PM PDT 24
Finished Jul 24 06:58:16 PM PDT 24
Peak memory 218448 kb
Host smart-ce411451-d0a2-4cfe-8002-72128c776fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994999306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2994999306
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2732294164
Short name T361
Test name
Test status
Simulation time 1069973846 ps
CPU time 14.47 seconds
Started Jul 24 06:58:21 PM PDT 24
Finished Jul 24 06:58:35 PM PDT 24
Peak memory 217752 kb
Host smart-fb5d7a8d-8720-4819-8308-8b7d142a9d83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732294164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2732294164
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3018531453
Short name T320
Test name
Test status
Simulation time 13859601768 ps
CPU time 101.5 seconds
Started Jul 24 06:58:10 PM PDT 24
Finished Jul 24 06:59:52 PM PDT 24
Peak memory 219008 kb
Host smart-9f8f1d02-0ef4-418d-b815-ec64ba3b96da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018531453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3018531453
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.996763980
Short name T709
Test name
Test status
Simulation time 909862541 ps
CPU time 5.61 seconds
Started Jul 24 06:58:12 PM PDT 24
Finished Jul 24 06:58:18 PM PDT 24
Peak memory 217784 kb
Host smart-e54b649f-68d6-44de-b05d-70177ca578e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996763980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.996763980
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1164111131
Short name T743
Test name
Test status
Simulation time 306708923 ps
CPU time 5.33 seconds
Started Jul 24 06:58:15 PM PDT 24
Finished Jul 24 06:58:20 PM PDT 24
Peak memory 218240 kb
Host smart-17324313-2c2a-4be2-b5a7-2b122a9e2e4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164111131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1164111131
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.4233976597
Short name T736
Test name
Test status
Simulation time 4737760060 ps
CPU time 26.22 seconds
Started Jul 24 06:58:12 PM PDT 24
Finished Jul 24 06:58:38 PM PDT 24
Peak memory 217748 kb
Host smart-ff6828bc-215f-427a-ac71-8c1c60aff12a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233976597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.4233976597
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3795801174
Short name T238
Test name
Test status
Simulation time 45051753 ps
CPU time 2.2 seconds
Started Jul 24 06:58:12 PM PDT 24
Finished Jul 24 06:58:14 PM PDT 24
Peak memory 217692 kb
Host smart-943ee7bc-a4cc-4ae9-9cfa-3228b873ec28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795801174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3795801174
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.4228184129
Short name T727
Test name
Test status
Simulation time 1036771878 ps
CPU time 42.38 seconds
Started Jul 24 06:58:13 PM PDT 24
Finished Jul 24 06:58:55 PM PDT 24
Peak memory 250904 kb
Host smart-f5fa8374-007a-40b1-8ef7-71fdcfd2e403
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228184129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.4228184129
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.4174432740
Short name T248
Test name
Test status
Simulation time 829595494 ps
CPU time 13.71 seconds
Started Jul 24 06:58:10 PM PDT 24
Finished Jul 24 06:58:24 PM PDT 24
Peak memory 223148 kb
Host smart-d9946944-75d3-4ef7-b2d4-2325b2855265
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174432740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.4174432740
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3038030930
Short name T203
Test name
Test status
Simulation time 95297137 ps
CPU time 3.28 seconds
Started Jul 24 06:58:06 PM PDT 24
Finished Jul 24 06:58:10 PM PDT 24
Peak memory 222692 kb
Host smart-f936098b-911a-44c3-9028-6c1bbc2876f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038030930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3038030930
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2933893882
Short name T347
Test name
Test status
Simulation time 812485351 ps
CPU time 10.87 seconds
Started Jul 24 06:58:12 PM PDT 24
Finished Jul 24 06:58:23 PM PDT 24
Peak memory 217932 kb
Host smart-8d322e1e-2b56-45a8-9052-f3e996b6cc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933893882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2933893882
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1796483464
Short name T602
Test name
Test status
Simulation time 944748223 ps
CPU time 12.75 seconds
Started Jul 24 06:58:13 PM PDT 24
Finished Jul 24 06:58:25 PM PDT 24
Peak memory 218892 kb
Host smart-5fac5da1-bc5e-4917-9b8a-c82064de01c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796483464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1796483464
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3737772217
Short name T285
Test name
Test status
Simulation time 492857099 ps
CPU time 15.4 seconds
Started Jul 24 06:58:15 PM PDT 24
Finished Jul 24 06:58:30 PM PDT 24
Peak memory 226036 kb
Host smart-8e9fb4c5-4757-4220-962c-ed65be99ff48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737772217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3737772217
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.4189829698
Short name T521
Test name
Test status
Simulation time 3403220019 ps
CPU time 12.56 seconds
Started Jul 24 06:58:11 PM PDT 24
Finished Jul 24 06:58:23 PM PDT 24
Peak memory 219024 kb
Host smart-72310377-7bb9-4017-9495-915a290b8c55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189829698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.4
189829698
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2974322418
Short name T505
Test name
Test status
Simulation time 1320413487 ps
CPU time 13.38 seconds
Started Jul 24 06:58:08 PM PDT 24
Finished Jul 24 06:58:21 PM PDT 24
Peak memory 218408 kb
Host smart-3b7c2aa5-34f2-4664-a806-6bee243fd1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974322418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2974322418
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.97847360
Short name T724
Test name
Test status
Simulation time 30368877 ps
CPU time 1.49 seconds
Started Jul 24 06:58:09 PM PDT 24
Finished Jul 24 06:58:10 PM PDT 24
Peak memory 213880 kb
Host smart-a94e8f03-3911-4725-8bc3-ebe078cfa892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97847360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.97847360
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.4085025785
Short name T585
Test name
Test status
Simulation time 225856439 ps
CPU time 20.76 seconds
Started Jul 24 06:58:18 PM PDT 24
Finished Jul 24 06:58:39 PM PDT 24
Peak memory 250964 kb
Host smart-9bd6faf3-af36-4bd5-8b56-b0e6d0ad32ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085025785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.4085025785
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3310399977
Short name T618
Test name
Test status
Simulation time 166931107 ps
CPU time 6.94 seconds
Started Jul 24 06:58:07 PM PDT 24
Finished Jul 24 06:58:14 PM PDT 24
Peak memory 247008 kb
Host smart-ff814aa3-6398-4e6a-a738-313f43dfdf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310399977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3310399977
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1582993357
Short name T846
Test name
Test status
Simulation time 14768909 ps
CPU time 1.05 seconds
Started Jul 24 06:58:07 PM PDT 24
Finished Jul 24 06:58:08 PM PDT 24
Peak memory 209136 kb
Host smart-16a1f921-72b1-4895-8124-8378866fcb39
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582993357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1582993357
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1136555551
Short name T219
Test name
Test status
Simulation time 87218787 ps
CPU time 1.31 seconds
Started Jul 24 06:58:25 PM PDT 24
Finished Jul 24 06:58:27 PM PDT 24
Peak memory 209148 kb
Host smart-6b926be7-2565-45a0-89bf-55afe14fd3b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136555551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1136555551
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1711093764
Short name T188
Test name
Test status
Simulation time 60237089 ps
CPU time 0.76 seconds
Started Jul 24 06:58:23 PM PDT 24
Finished Jul 24 06:58:24 PM PDT 24
Peak memory 209080 kb
Host smart-c284a6e8-2f37-42b3-b754-6c02e8fc9dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711093764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1711093764
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3303184100
Short name T80
Test name
Test status
Simulation time 561920754 ps
CPU time 10 seconds
Started Jul 24 06:58:22 PM PDT 24
Finished Jul 24 06:58:33 PM PDT 24
Peak memory 226104 kb
Host smart-8a80d414-4c5f-4ff6-b789-73209a5aba87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303184100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3303184100
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1884637189
Short name T25
Test name
Test status
Simulation time 658619085 ps
CPU time 4.12 seconds
Started Jul 24 06:58:21 PM PDT 24
Finished Jul 24 06:58:25 PM PDT 24
Peak memory 217768 kb
Host smart-7629e116-b38e-449e-991c-96ba9e4f38be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884637189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1884637189
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.4179104769
Short name T541
Test name
Test status
Simulation time 2332118958 ps
CPU time 20.87 seconds
Started Jul 24 06:58:21 PM PDT 24
Finished Jul 24 06:58:42 PM PDT 24
Peak memory 218456 kb
Host smart-80292567-69f2-43da-a6a0-c3e2c43bc769
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179104769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.4179104769
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2166849515
Short name T683
Test name
Test status
Simulation time 216277344 ps
CPU time 6.59 seconds
Started Jul 24 06:58:18 PM PDT 24
Finished Jul 24 06:58:25 PM PDT 24
Peak memory 217856 kb
Host smart-97c0b191-fdf3-425a-8a79-edcd7778f173
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166849515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
166849515
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2092957660
Short name T197
Test name
Test status
Simulation time 992549528 ps
CPU time 4.54 seconds
Started Jul 24 06:58:20 PM PDT 24
Finished Jul 24 06:58:25 PM PDT 24
Peak memory 218292 kb
Host smart-9bd90cbb-1aea-42d9-83da-53fdc70a570a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092957660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2092957660
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.564791761
Short name T70
Test name
Test status
Simulation time 3957287452 ps
CPU time 26.74 seconds
Started Jul 24 06:58:20 PM PDT 24
Finished Jul 24 06:58:47 PM PDT 24
Peak memory 217716 kb
Host smart-c563f84e-9818-4963-bc02-4a2921830d2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564791761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.564791761
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1327563464
Short name T816
Test name
Test status
Simulation time 446155118 ps
CPU time 7.33 seconds
Started Jul 24 06:58:24 PM PDT 24
Finished Jul 24 06:58:32 PM PDT 24
Peak memory 217676 kb
Host smart-dd096202-6576-4a79-a615-fdb3b0227d23
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327563464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1327563464
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3816854086
Short name T274
Test name
Test status
Simulation time 13549953434 ps
CPU time 41.4 seconds
Started Jul 24 06:58:19 PM PDT 24
Finished Jul 24 06:59:01 PM PDT 24
Peak memory 268472 kb
Host smart-b1d4f2d0-6597-43ab-b32b-d6cb7b541e43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816854086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.3816854086
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2104521040
Short name T471
Test name
Test status
Simulation time 2330650674 ps
CPU time 18.88 seconds
Started Jul 24 06:58:20 PM PDT 24
Finished Jul 24 06:58:39 PM PDT 24
Peak memory 250968 kb
Host smart-4921b662-63f9-4def-8448-9ba6e54f2f3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104521040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2104521040
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.221027815
Short name T654
Test name
Test status
Simulation time 23753677 ps
CPU time 1.88 seconds
Started Jul 24 06:58:19 PM PDT 24
Finished Jul 24 06:58:21 PM PDT 24
Peak memory 222080 kb
Host smart-af65f5cf-1a6a-4fb2-89ee-73c347ba995e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221027815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.221027815
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.580031795
Short name T183
Test name
Test status
Simulation time 2531187172 ps
CPU time 14.69 seconds
Started Jul 24 06:58:23 PM PDT 24
Finished Jul 24 06:58:38 PM PDT 24
Peak memory 214692 kb
Host smart-47fc7e2c-8149-4632-ab21-730273c47374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580031795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.580031795
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3655098151
Short name T357
Test name
Test status
Simulation time 3483371020 ps
CPU time 13.92 seconds
Started Jul 24 06:58:19 PM PDT 24
Finished Jul 24 06:58:33 PM PDT 24
Peak memory 219080 kb
Host smart-48e72fe0-b93e-4fcd-bdd1-91cfe1c02dcd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655098151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3655098151
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.1414908602
Short name T344
Test name
Test status
Simulation time 432885938 ps
CPU time 8.67 seconds
Started Jul 24 06:58:18 PM PDT 24
Finished Jul 24 06:58:27 PM PDT 24
Peak memory 226096 kb
Host smart-84fb8a9f-a495-4a4b-a5b4-4544220a33d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414908602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.1414908602
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3618209956
Short name T326
Test name
Test status
Simulation time 200524560 ps
CPU time 8.29 seconds
Started Jul 24 06:58:22 PM PDT 24
Finished Jul 24 06:58:31 PM PDT 24
Peak memory 218256 kb
Host smart-6679cea5-3bc4-4f83-a6ee-4403fd5ea9ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618209956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
618209956
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.502571207
Short name T794
Test name
Test status
Simulation time 1649259914 ps
CPU time 11.13 seconds
Started Jul 24 06:58:25 PM PDT 24
Finished Jul 24 06:58:36 PM PDT 24
Peak memory 222808 kb
Host smart-e096f007-7a8a-4d8b-9bb8-9f835003216c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502571207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.502571207
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3985705011
Short name T611
Test name
Test status
Simulation time 269606450 ps
CPU time 33 seconds
Started Jul 24 06:58:19 PM PDT 24
Finished Jul 24 06:58:52 PM PDT 24
Peak memory 250916 kb
Host smart-8a6e4272-dacb-45a8-b832-617de07775c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985705011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3985705011
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3004386164
Short name T507
Test name
Test status
Simulation time 227645708 ps
CPU time 6.83 seconds
Started Jul 24 06:58:20 PM PDT 24
Finished Jul 24 06:58:27 PM PDT 24
Peak memory 250440 kb
Host smart-956497f2-ee10-4342-b5fd-4ef20b56847e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004386164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3004386164
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3131883243
Short name T299
Test name
Test status
Simulation time 15364708382 ps
CPU time 147.18 seconds
Started Jul 24 06:58:27 PM PDT 24
Finished Jul 24 07:00:54 PM PDT 24
Peak memory 230296 kb
Host smart-160c24df-1504-4a0f-9b6d-62843cef9d2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131883243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3131883243
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.441412030
Short name T155
Test name
Test status
Simulation time 27294819912 ps
CPU time 364.62 seconds
Started Jul 24 06:58:24 PM PDT 24
Finished Jul 24 07:04:29 PM PDT 24
Peak memory 283564 kb
Host smart-eae21868-89c2-42b5-9dd4-d56a6291d93a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=441412030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.441412030
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1654331601
Short name T52
Test name
Test status
Simulation time 13625125 ps
CPU time 0.97 seconds
Started Jul 24 06:58:20 PM PDT 24
Finished Jul 24 06:58:21 PM PDT 24
Peak memory 211976 kb
Host smart-95ef7b59-38f2-4f5e-9f0b-7d73a3eb1594
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654331601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1654331601
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1182856734
Short name T630
Test name
Test status
Simulation time 22330518 ps
CPU time 1.32 seconds
Started Jul 24 06:58:38 PM PDT 24
Finished Jul 24 06:58:40 PM PDT 24
Peak memory 209092 kb
Host smart-58d4a397-3e37-47b4-bbe3-1ab820401baf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182856734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1182856734
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2907609813
Short name T186
Test name
Test status
Simulation time 17827752 ps
CPU time 0.86 seconds
Started Jul 24 06:58:31 PM PDT 24
Finished Jul 24 06:58:32 PM PDT 24
Peak memory 208796 kb
Host smart-1165a08e-e2c4-41bb-833a-93fe79e7cd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907609813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2907609813
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3293066813
Short name T277
Test name
Test status
Simulation time 354199724 ps
CPU time 13.46 seconds
Started Jul 24 06:58:27 PM PDT 24
Finished Jul 24 06:58:40 PM PDT 24
Peak memory 218348 kb
Host smart-dc1e20f1-8177-4905-86d3-c6ef829929d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293066813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3293066813
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1823584679
Short name T283
Test name
Test status
Simulation time 358072147 ps
CPU time 2.32 seconds
Started Jul 24 06:58:33 PM PDT 24
Finished Jul 24 06:58:35 PM PDT 24
Peak memory 217576 kb
Host smart-a1995093-40e0-4bdb-aa7e-a1b06ff1ed62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823584679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1823584679
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1830444706
Short name T465
Test name
Test status
Simulation time 7424851598 ps
CPU time 64.62 seconds
Started Jul 24 06:58:32 PM PDT 24
Finished Jul 24 06:59:37 PM PDT 24
Peak memory 219128 kb
Host smart-374dc957-1f0d-4022-a7d1-8ad26c20e055
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830444706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1830444706
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2096378415
Short name T245
Test name
Test status
Simulation time 15146815298 ps
CPU time 8 seconds
Started Jul 24 06:58:31 PM PDT 24
Finished Jul 24 06:58:39 PM PDT 24
Peak memory 217832 kb
Host smart-8171ba33-4216-49d9-9ceb-ebbe41a0e403
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096378415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
096378415
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3430045899
Short name T858
Test name
Test status
Simulation time 3844226695 ps
CPU time 25.03 seconds
Started Jul 24 06:58:34 PM PDT 24
Finished Jul 24 06:58:59 PM PDT 24
Peak memory 218360 kb
Host smart-5f9337b1-5e7c-4a21-b28b-d984121f4e25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430045899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3430045899
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3856843191
Short name T302
Test name
Test status
Simulation time 1044694891 ps
CPU time 29.8 seconds
Started Jul 24 06:58:31 PM PDT 24
Finished Jul 24 06:59:00 PM PDT 24
Peak memory 217600 kb
Host smart-9be54fe8-bc33-4c25-bf41-776ca89479de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856843191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3856843191
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2307580787
Short name T390
Test name
Test status
Simulation time 591520030 ps
CPU time 2.62 seconds
Started Jul 24 06:58:32 PM PDT 24
Finished Jul 24 06:58:35 PM PDT 24
Peak memory 217732 kb
Host smart-0f4a78ff-1da8-41d5-8011-555e0df1000b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307580787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2307580787
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1318483660
Short name T20
Test name
Test status
Simulation time 3590696884 ps
CPU time 71.05 seconds
Started Jul 24 06:58:31 PM PDT 24
Finished Jul 24 06:59:43 PM PDT 24
Peak memory 283624 kb
Host smart-e0924d59-cd12-4432-9c67-820d14b2766c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318483660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1318483660
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1585027172
Short name T762
Test name
Test status
Simulation time 366094686 ps
CPU time 12.51 seconds
Started Jul 24 06:58:32 PM PDT 24
Finished Jul 24 06:58:45 PM PDT 24
Peak memory 250912 kb
Host smart-9a85c05a-24b0-4223-84dd-e8195726bf27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585027172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1585027172
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3368413981
Short name T196
Test name
Test status
Simulation time 92096757 ps
CPU time 4.25 seconds
Started Jul 24 06:58:26 PM PDT 24
Finished Jul 24 06:58:30 PM PDT 24
Peak memory 218320 kb
Host smart-92dd1aa6-2d35-498c-a672-8432f005aebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368413981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3368413981
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1140354508
Short name T757
Test name
Test status
Simulation time 591528510 ps
CPU time 10.61 seconds
Started Jul 24 06:58:31 PM PDT 24
Finished Jul 24 06:58:42 PM PDT 24
Peak memory 214868 kb
Host smart-a284ee38-71d6-4df0-befe-62adf16d0349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140354508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1140354508
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3996564276
Short name T574
Test name
Test status
Simulation time 560456044 ps
CPU time 12.41 seconds
Started Jul 24 06:58:34 PM PDT 24
Finished Jul 24 06:58:46 PM PDT 24
Peak memory 226180 kb
Host smart-40a9e806-e6d8-41dd-8242-ca10a29943c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996564276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3996564276
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.840453760
Short name T641
Test name
Test status
Simulation time 1049557083 ps
CPU time 8.31 seconds
Started Jul 24 06:58:34 PM PDT 24
Finished Jul 24 06:58:43 PM PDT 24
Peak memory 226080 kb
Host smart-9866d7d7-f309-448a-bc33-b425c8004e4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840453760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig
est.840453760
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1426027125
Short name T599
Test name
Test status
Simulation time 362131392 ps
CPU time 10.22 seconds
Started Jul 24 06:58:32 PM PDT 24
Finished Jul 24 06:58:43 PM PDT 24
Peak memory 218336 kb
Host smart-838502d6-fc00-420c-b987-43dbfe47e92b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426027125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
426027125
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.342235608
Short name T275
Test name
Test status
Simulation time 1412348031 ps
CPU time 14.93 seconds
Started Jul 24 06:58:26 PM PDT 24
Finished Jul 24 06:58:41 PM PDT 24
Peak memory 226136 kb
Host smart-44c211c2-0936-4cf6-9013-be3b1771d9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342235608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.342235608
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1562515805
Short name T68
Test name
Test status
Simulation time 381204543 ps
CPU time 2.98 seconds
Started Jul 24 06:58:26 PM PDT 24
Finished Jul 24 06:58:29 PM PDT 24
Peak memory 217768 kb
Host smart-c0d7280f-4df5-47cd-aea5-fc8a3ec0f981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562515805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1562515805
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1258953876
Short name T840
Test name
Test status
Simulation time 195416284 ps
CPU time 18.88 seconds
Started Jul 24 06:58:26 PM PDT 24
Finished Jul 24 06:58:45 PM PDT 24
Peak memory 251000 kb
Host smart-aa9de033-2e3b-4112-850b-b33dac6633cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258953876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1258953876
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3518250452
Short name T399
Test name
Test status
Simulation time 228349454 ps
CPU time 8.12 seconds
Started Jul 24 06:58:24 PM PDT 24
Finished Jul 24 06:58:33 PM PDT 24
Peak memory 250980 kb
Host smart-04d88729-b026-4758-9341-4fc66a0a727a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518250452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3518250452
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2952831088
Short name T444
Test name
Test status
Simulation time 5199077575 ps
CPU time 71.99 seconds
Started Jul 24 06:58:32 PM PDT 24
Finished Jul 24 06:59:44 PM PDT 24
Peak memory 251068 kb
Host smart-624776e0-22dd-4624-974a-05dd3d9202bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952831088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2952831088
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2588480566
Short name T572
Test name
Test status
Simulation time 43189295 ps
CPU time 0.83 seconds
Started Jul 24 06:58:26 PM PDT 24
Finished Jul 24 06:58:27 PM PDT 24
Peak memory 208908 kb
Host smart-d18a6cbf-965b-4ded-88a0-34c463a15ab5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588480566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2588480566
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2974021269
Short name T431
Test name
Test status
Simulation time 23894305 ps
CPU time 1.02 seconds
Started Jul 24 06:58:44 PM PDT 24
Finished Jul 24 06:58:45 PM PDT 24
Peak memory 208932 kb
Host smart-9a812bb6-dba0-41df-b003-c277f15a9a52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974021269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2974021269
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2698544727
Short name T76
Test name
Test status
Simulation time 52154205 ps
CPU time 0.87 seconds
Started Jul 24 06:58:40 PM PDT 24
Finished Jul 24 06:58:41 PM PDT 24
Peak memory 208724 kb
Host smart-a0f6fa03-7366-4f19-827a-460983749beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698544727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2698544727
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1604140028
Short name T489
Test name
Test status
Simulation time 432193223 ps
CPU time 17.53 seconds
Started Jul 24 06:58:38 PM PDT 24
Finished Jul 24 06:58:56 PM PDT 24
Peak memory 218336 kb
Host smart-9276ad0f-a2a0-4413-81c9-d6a00c266cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604140028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1604140028
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2695109238
Short name T644
Test name
Test status
Simulation time 4194109755 ps
CPU time 13.99 seconds
Started Jul 24 06:58:41 PM PDT 24
Finished Jul 24 06:58:56 PM PDT 24
Peak memory 217844 kb
Host smart-0f991fa7-7eb2-432c-a559-caabeb230b7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695109238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2695109238
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.198174830
Short name T647
Test name
Test status
Simulation time 8078934272 ps
CPU time 57.6 seconds
Started Jul 24 06:58:39 PM PDT 24
Finished Jul 24 06:59:37 PM PDT 24
Peak memory 218892 kb
Host smart-ccd1e057-3e49-4603-8f98-fe5624a0c77a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198174830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.198174830
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3937281410
Short name T720
Test name
Test status
Simulation time 5287229472 ps
CPU time 46.26 seconds
Started Jul 24 06:58:39 PM PDT 24
Finished Jul 24 06:59:25 PM PDT 24
Peak memory 217808 kb
Host smart-669d4a08-531c-4cec-a840-4be7d187298b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937281410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
937281410
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2927051965
Short name T767
Test name
Test status
Simulation time 105609180 ps
CPU time 1.9 seconds
Started Jul 24 06:58:38 PM PDT 24
Finished Jul 24 06:58:40 PM PDT 24
Peak memory 221604 kb
Host smart-ea050c43-0b91-4130-9182-0d8a83ee4b0f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927051965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2927051965
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3287916712
Short name T848
Test name
Test status
Simulation time 1106507750 ps
CPU time 16.8 seconds
Started Jul 24 06:58:38 PM PDT 24
Finished Jul 24 06:58:55 PM PDT 24
Peak memory 217668 kb
Host smart-06aa9151-8e1b-4dc4-803b-a009d486c3bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287916712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3287916712
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2615765156
Short name T573
Test name
Test status
Simulation time 305027643 ps
CPU time 4.99 seconds
Started Jul 24 06:58:38 PM PDT 24
Finished Jul 24 06:58:44 PM PDT 24
Peak memory 217780 kb
Host smart-d752a316-7620-4376-8765-b775fbed7ace
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615765156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2615765156
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3952070230
Short name T655
Test name
Test status
Simulation time 9461235111 ps
CPU time 55.86 seconds
Started Jul 24 06:58:38 PM PDT 24
Finished Jul 24 06:59:34 PM PDT 24
Peak memory 267372 kb
Host smart-0f787d1f-3004-4793-93dc-9029030d9138
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952070230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3952070230
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2672368409
Short name T340
Test name
Test status
Simulation time 426514115 ps
CPU time 9.1 seconds
Started Jul 24 06:58:38 PM PDT 24
Finished Jul 24 06:58:48 PM PDT 24
Peak memory 223036 kb
Host smart-3339976a-9890-42ed-a7dd-14c129f95fb8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672368409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2672368409
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3356294599
Short name T791
Test name
Test status
Simulation time 156323462 ps
CPU time 2.19 seconds
Started Jul 24 06:58:39 PM PDT 24
Finished Jul 24 06:58:42 PM PDT 24
Peak memory 222160 kb
Host smart-a8c1df5a-b1d0-4b13-83bb-ae85ea3591db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356294599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3356294599
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.392976374
Short name T50
Test name
Test status
Simulation time 948158288 ps
CPU time 15.92 seconds
Started Jul 24 06:58:37 PM PDT 24
Finished Jul 24 06:58:53 PM PDT 24
Peak memory 214108 kb
Host smart-5a38d9f1-77b6-41a6-9af3-7ce54fe12490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392976374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.392976374
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1098442219
Short name T226
Test name
Test status
Simulation time 3821395903 ps
CPU time 9.68 seconds
Started Jul 24 06:58:37 PM PDT 24
Finished Jul 24 06:58:47 PM PDT 24
Peak memory 219272 kb
Host smart-8dc70069-aa50-471f-abcc-56f4d3908d16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098442219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1098442219
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.743060078
Short name T199
Test name
Test status
Simulation time 251094256 ps
CPU time 10.5 seconds
Started Jul 24 06:58:39 PM PDT 24
Finished Jul 24 06:58:50 PM PDT 24
Peak memory 226104 kb
Host smart-f265feea-d290-46ac-8ca5-56a8b2b9d13d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743060078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.743060078
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2018890508
Short name T539
Test name
Test status
Simulation time 439547568 ps
CPU time 14.69 seconds
Started Jul 24 06:58:42 PM PDT 24
Finished Jul 24 06:58:57 PM PDT 24
Peak memory 226096 kb
Host smart-b07344db-6fb2-4e56-a7d1-0e8c46e36810
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018890508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
018890508
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.4260334722
Short name T797
Test name
Test status
Simulation time 1654378436 ps
CPU time 10.76 seconds
Started Jul 24 06:58:38 PM PDT 24
Finished Jul 24 06:58:49 PM PDT 24
Peak memory 218452 kb
Host smart-d6dc59e5-7489-4227-abd5-1828f1037b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260334722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.4260334722
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2015708886
Short name T82
Test name
Test status
Simulation time 224197965 ps
CPU time 3.39 seconds
Started Jul 24 06:58:38 PM PDT 24
Finished Jul 24 06:58:42 PM PDT 24
Peak memory 217788 kb
Host smart-061c16c4-84d9-4ccc-95b7-52d01472964b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015708886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2015708886
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1076184019
Short name T423
Test name
Test status
Simulation time 749129671 ps
CPU time 24.8 seconds
Started Jul 24 06:58:39 PM PDT 24
Finished Jul 24 06:59:04 PM PDT 24
Peak memory 245784 kb
Host smart-73867a7f-24b6-4909-a6b2-faa92fb63b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076184019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1076184019
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3755449808
Short name T566
Test name
Test status
Simulation time 86509387 ps
CPU time 7.12 seconds
Started Jul 24 06:58:42 PM PDT 24
Finished Jul 24 06:58:49 PM PDT 24
Peak memory 250408 kb
Host smart-20f98059-8c04-4fb5-8edb-15129c36bef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755449808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3755449808
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.133182021
Short name T834
Test name
Test status
Simulation time 21689801239 ps
CPU time 380.45 seconds
Started Jul 24 06:58:41 PM PDT 24
Finished Jul 24 07:05:02 PM PDT 24
Peak memory 221064 kb
Host smart-e6890fb2-d3e5-4146-b043-628b6ca1e81d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133182021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.133182021
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3515982929
Short name T40
Test name
Test status
Simulation time 14119571 ps
CPU time 0.94 seconds
Started Jul 24 06:58:39 PM PDT 24
Finished Jul 24 06:58:40 PM PDT 24
Peak memory 212004 kb
Host smart-19c54817-33b4-4023-8282-add546ddc07b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515982929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3515982929
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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