Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2322639	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2550806

1

T2

1095

T3

963

T8

906

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4525015	1			T2	1116		T3	599		T8	912
values[0x0]	174169	1			T2	319		T3	384		T8	278
values[0x1]	174261	1			T2	289		T3	408		T8	266

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1847788	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3025657

1

T2

1244

T3

1070

T8

1020

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15982	1			T2	2		T8	1		T4	1
valid_sources[0x01]	18157	1			T2	7		T3	4		T8	6
valid_sources[0x02]	15857	1			T2	8		T3	4		T4	1
valid_sources[0x03]	15826	1			T2	13		T8	4		T13	5
valid_sources[0x04]	17311	1			T2	5		T8	11		T4	1
valid_sources[0x05]	16218	1			T2	9		T3	2		T8	2
valid_sources[0x06]	15675	1			T2	2		T3	17		T12	1
valid_sources[0x07]	17127	1			T2	2		T13	12		T28	9
valid_sources[0x08]	17010	1			T2	5		T3	10		T8	2
valid_sources[0x09]	15632	1			T2	5		T3	20		T8	7
valid_sources[0x0a]	16312	1			T2	20		T8	6		T13	9
valid_sources[0x0b]	15883	1			T2	3		T8	2		T4	1
valid_sources[0x0c]	17005	1			T2	8		T3	13		T8	2
valid_sources[0x0d]	15724	1			T2	2		T4	3		T13	1
valid_sources[0x0e]	15813	1			T2	17		T3	2		T8	3
valid_sources[0x0f]	16041	1			T2	9		T3	12		T8	8
valid_sources[0x10]	19916	1			T2	6		T8	1		T13	6
valid_sources[0x11]	15977	1			T2	5		T8	10		T4	4
valid_sources[0x12]	16033	1			T2	6		T8	6		T13	2
valid_sources[0x13]	15181	1			T2	5		T8	1		T13	8
valid_sources[0x14]	16304	1			T2	11		T3	33		T8	4
valid_sources[0x15]	15926	1			T2	13		T3	14		T4	1
valid_sources[0x16]	16330	1			T2	14		T8	12		T13	6
valid_sources[0x17]	159521	1			T2	5		T8	5		T4	2
valid_sources[0x18]	15957	1			T2	6		T3	4		T8	2
valid_sources[0x19]	16170	1			T2	3		T8	1		T4	2
valid_sources[0x1a]	16294	1			T2	11		T4	1		T13	5
valid_sources[0x1b]	16781	1			T2	3		T3	4		T8	5
valid_sources[0x1c]	17476	1			T2	16		T8	3		T13	6
valid_sources[0x1d]	16875	1			T2	6		T3	28		T8	16
valid_sources[0x1e]	15906	1			T2	9		T13	1		T28	3
valid_sources[0x1f]	15830	1			T2	10		T3	23		T8	20
valid_sources[0x20]	16245	1			T2	2		T3	12		T8	7
valid_sources[0x21]	25227	1			T2	8		T8	5		T12	1
valid_sources[0x22]	15855	1			T2	5		T13	9		T28	3
valid_sources[0x23]	16382	1			T2	3		T8	8		T13	7
valid_sources[0x24]	15933	1			T2	11		T8	8		T13	1
valid_sources[0x25]	17317	1			T3	23		T8	3		T4	2
valid_sources[0x26]	15857	1			T2	8		T8	19		T13	7
valid_sources[0x27]	15888	1			T2	3		T8	4		T4	1
valid_sources[0x28]	17920	1			T2	3		T3	15		T8	6
valid_sources[0x29]	16839	1			T2	8		T8	13		T4	2
valid_sources[0x2a]	16295	1			T2	9		T3	4		T13	2
valid_sources[0x2b]	15611	1			T2	11		T4	1		T13	7
valid_sources[0x2c]	18037	1			T2	13		T13	3		T28	2
valid_sources[0x2d]	16488	1			T8	4		T13	1		T38	18
valid_sources[0x2e]	16211	1			T3	3		T8	10		T4	2
valid_sources[0x2f]	71379	1			T2	2		T8	9		T4	1
valid_sources[0x30]	16782	1			T2	4		T12	1		T13	6
valid_sources[0x31]	16643	1			T2	2		T8	9		T4	2
valid_sources[0x32]	16490	1			T2	11		T8	10		T4	1
valid_sources[0x33]	15693	1			T2	5		T8	4		T13	6
valid_sources[0x34]	16241	1			T2	7		T8	37		T12	2
valid_sources[0x35]	17101	1			T2	12		T8	5		T13	10
valid_sources[0x36]	15673	1			T2	11		T3	13		T8	1
valid_sources[0x37]	15508	1			T2	2		T13	5		T28	1
valid_sources[0x38]	16109	1			T2	2		T3	11		T8	8
valid_sources[0x39]	15809	1			T2	8		T8	6		T12	1
valid_sources[0x3a]	15571	1			T2	5		T8	7		T4	1
valid_sources[0x3b]	16336	1			T2	6		T3	9		T8	4
valid_sources[0x3c]	17150	1			T2	10		T3	19		T8	14
valid_sources[0x3d]	16773	1			T2	11		T8	2		T4	1
valid_sources[0x3e]	15957	1			T2	1		T8	19		T12	1
valid_sources[0x3f]	15277	1			T2	9		T13	5		T15	220
valid_sources[0x40]	17141	1			T2	6		T8	7		T13	3
valid_sources[0x41]	16101	1			T2	6		T8	11		T13	4
valid_sources[0x42]	18597	1			T2	6		T3	9		T13	6
valid_sources[0x43]	15834	1			T2	9		T8	2		T13	6
valid_sources[0x44]	17743	1			T2	7		T8	5		T4	1
valid_sources[0x45]	66711	1			T2	10		T12	2		T13	6
valid_sources[0x46]	15611	1			T2	5		T13	3		T28	4
valid_sources[0x47]	17324	1			T2	6		T4	1		T13	2
valid_sources[0x48]	15723	1			T2	5		T13	5		T28	6
valid_sources[0x49]	17362	1			T2	9		T3	23		T8	7
valid_sources[0x4a]	16016	1			T2	7		T4	1		T13	9
valid_sources[0x4b]	16837	1			T2	4		T8	2		T4	3
valid_sources[0x4c]	15876	1			T2	18		T13	4		T28	5
valid_sources[0x4d]	16485	1			T2	11		T3	7		T8	4
valid_sources[0x4e]	15868	1			T2	13		T3	14		T8	1
valid_sources[0x4f]	16011	1			T2	3		T8	12		T4	1
valid_sources[0x50]	61694	1			T2	12		T3	8		T8	2
valid_sources[0x51]	17411	1			T2	4		T8	13		T13	4
valid_sources[0x52]	19526	1			T2	5		T13	6		T28	1
valid_sources[0x53]	15630	1			T2	3		T8	5		T13	4
valid_sources[0x54]	15733	1			T2	10		T3	81		T8	3
valid_sources[0x55]	15741	1			T2	4		T8	6		T13	2
valid_sources[0x56]	15677	1			T2	2		T3	4		T8	21
valid_sources[0x57]	17455	1			T2	6		T3	37		T8	1
valid_sources[0x58]	26856	1			T2	6		T8	15		T4	5
valid_sources[0x59]	15763	1			T2	6		T3	2		T4	2
valid_sources[0x5a]	20084	1			T2	2		T8	4		T4	1
valid_sources[0x5b]	44859	1			T2	8		T13	11		T28	4
valid_sources[0x5c]	16871	1			T2	7		T13	13		T28	4
valid_sources[0x5d]	16163	1			T2	1		T8	2		T4	3
valid_sources[0x5e]	32985	1			T2	10		T3	23		T12	3
valid_sources[0x5f]	16248	1			T2	3		T13	6		T28	5
valid_sources[0x60]	16104	1			T2	1		T8	16		T13	7
valid_sources[0x61]	18024	1			T2	6		T8	6		T13	5
valid_sources[0x62]	16123	1			T2	7		T13	5		T28	5
valid_sources[0x63]	15540	1			T2	9		T12	5		T13	5
valid_sources[0x64]	15982	1			T2	7		T3	11		T8	8
valid_sources[0x65]	15280	1			T2	14		T3	50		T8	4
valid_sources[0x66]	21701	1			T2	21		T8	14		T13	5
valid_sources[0x67]	16321	1			T2	10		T3	22		T4	3
valid_sources[0x68]	15836	1			T2	1		T13	6		T28	2
valid_sources[0x69]	19276	1			T2	4		T3	9		T8	19
valid_sources[0x6a]	16018	1			T2	2		T3	2		T13	2
valid_sources[0x6b]	16073	1			T2	16		T8	9		T13	10
valid_sources[0x6c]	15770	1			T2	6		T13	10		T28	2
valid_sources[0x6d]	19443	1			T2	2		T3	4		T4	1
valid_sources[0x6e]	18880	1			T2	4		T8	6		T4	1
valid_sources[0x6f]	26512	1			T2	7		T8	12		T4	2
valid_sources[0x70]	16066	1			T2	11		T4	1		T28	7
valid_sources[0x71]	17113	1			T2	7		T3	4		T13	9
valid_sources[0x72]	16199	1			T2	7		T3	10		T8	17
valid_sources[0x73]	22546	1			T2	3		T8	11		T4	3
valid_sources[0x74]	16253	1			T2	11		T8	3		T4	2
valid_sources[0x75]	15928	1			T2	3		T3	36		T4	1
valid_sources[0x76]	15987	1			T2	7		T3	8		T13	4
valid_sources[0x77]	16202	1			T2	4		T3	30		T8	7
valid_sources[0x78]	16999	1			T2	5		T8	3		T12	2
valid_sources[0x79]	15893	1			T2	4		T8	3		T13	8
valid_sources[0x7a]	17160	1			T2	4		T4	1		T13	5
valid_sources[0x7b]	15728	1			T2	7		T8	3		T13	12
valid_sources[0x7c]	18387	1			T2	1		T3	1		T8	13
valid_sources[0x7d]	29349	1			T2	12		T8	11		T13	7
valid_sources[0x7e]	21604	1			T2	11		T3	5		T8	4
valid_sources[0x7f]	15683	1			T2	7		T3	31		T8	2
valid_sources[0x80]	16405	1			T2	1		T8	8		T13	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2250065

1

T2

565

T3

279

T8

435

values[0x0]

all_enables

biggest_size

151294

1

T2

275

T3

344

T8

243

values[0x1]

all_enables

biggest_size

149447

1

T2

255

T3

340

T8

228