Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	112214411	16828	0	0
claim_transition_if_regwen_rd_A	112214411	2033	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112214411	16828	0	0
T7	49699	0	0	0
T18	201031	2	0	0
T44	23235	0	0	0
T47	0	2	0	0
T49	25056	0	0	0
T50	44163	0	0	0
T62	0	7	0	0
T65	64646	0	0	0
T68	71801	0	0	0
T90	89267	0	0	0
T91	1595	0	0	0
T92	0	1	0	0
T106	0	6	0	0
T108	0	5	0	0
T145	0	4	0	0
T146	0	10	0	0
T147	0	1	0	0
T148	0	2	0	0
T149	74263	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112214411	2033	0	0
T92	123956	9	0	0
T109	0	41	0	0
T112	0	2	0	0
T147	0	3	0	0
T150	0	41	0	0
T151	0	6	0	0
T152	0	16	0	0
T153	0	107	0	0
T154	0	40	0	0
T155	0	52	0	0
T156	30034	0	0	0
T157	26043	0	0	0
T158	367161	0	0	0
T159	44203	0	0	0
T160	1945	0	0	0
T161	4744	0	0	0
T162	2095	0	0	0
T163	3402	0	0	0
T164	1515	0	0	0