Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1531521	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1754471

1

T1

12

T2

668

T3

934

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2940906	1			T1	11		T2	574		T3	1121
values[0x0]	171940	1			T1	10		T2	251		T3	236
values[0x1]	173146	1			T1	6		T2	269		T3	228

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1215577	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2070415

1

T1

15

T2

775

T3

1069

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14527	1			T2	3		T3	11		T4	1
valid_sources[0x01]	11518	1			T2	1		T3	7		T4	4
valid_sources[0x02]	13972	1			T2	10		T4	4		T5	4
valid_sources[0x03]	16965	1			T2	2		T3	5		T4	9
valid_sources[0x04]	19472	1			T2	8		T3	2		T4	8
valid_sources[0x05]	11292	1			T2	6		T3	10		T4	17
valid_sources[0x06]	11451	1			T2	4		T3	2		T4	7
valid_sources[0x07]	11047	1			T2	5		T3	3		T4	7
valid_sources[0x08]	11353	1			T2	6		T3	4		T4	3
valid_sources[0x09]	11299	1			T2	3		T3	6		T4	4
valid_sources[0x0a]	31882	1			T2	2		T3	11		T4	1
valid_sources[0x0b]	11909	1			T3	8		T4	10		T5	1
valid_sources[0x0c]	11142	1			T2	7		T3	1		T4	6
valid_sources[0x0d]	12649	1			T2	5		T3	2		T4	5
valid_sources[0x0e]	21665	1			T2	6		T3	13		T4	5
valid_sources[0x0f]	11277	1			T2	11		T3	14		T4	1
valid_sources[0x10]	12140	1			T2	1		T5	2		T12	4
valid_sources[0x11]	12732	1			T2	10		T3	2		T4	4
valid_sources[0x12]	11809	1			T2	2		T3	5		T5	1
valid_sources[0x13]	11314	1			T1	1		T2	2		T3	6
valid_sources[0x14]	10987	1			T2	2		T3	9		T4	10
valid_sources[0x15]	12460	1			T2	1		T3	10		T4	6
valid_sources[0x16]	11695	1			T2	2		T3	10		T4	10
valid_sources[0x17]	10956	1			T2	8		T3	5		T5	2
valid_sources[0x18]	13704	1			T2	3		T3	12		T4	2
valid_sources[0x19]	13672	1			T2	1		T3	16		T5	2
valid_sources[0x1a]	12148	1			T2	3		T3	17		T4	1
valid_sources[0x1b]	11244	1			T1	10		T2	11		T3	1
valid_sources[0x1c]	14410	1			T2	5		T3	10		T12	2
valid_sources[0x1d]	11307	1			T2	1		T3	5		T4	12
valid_sources[0x1e]	11062	1			T2	4		T4	6		T5	4
valid_sources[0x1f]	11069	1			T2	1		T3	10		T4	4
valid_sources[0x20]	12683	1			T2	5		T3	24		T4	3
valid_sources[0x21]	11281	1			T2	4		T3	6		T4	2
valid_sources[0x22]	11975	1			T2	3		T3	5		T4	6
valid_sources[0x23]	13714	1			T2	8		T3	1		T4	3
valid_sources[0x24]	11245	1			T2	3		T3	1		T4	4
valid_sources[0x25]	13571	1			T2	3		T3	2		T12	2
valid_sources[0x26]	11118	1			T2	1		T3	7		T4	4
valid_sources[0x27]	15273	1			T2	1		T3	19		T4	5
valid_sources[0x28]	11622	1			T3	4		T4	8		T5	2
valid_sources[0x29]	13094	1			T2	4		T4	1		T12	1
valid_sources[0x2a]	11885	1			T2	1		T3	9		T4	12
valid_sources[0x2b]	12668	1			T2	1		T3	8		T4	8
valid_sources[0x2c]	11351	1			T2	5		T3	6		T4	16
valid_sources[0x2d]	12151	1			T2	10		T3	9		T4	1
valid_sources[0x2e]	11828	1			T2	8		T3	6		T4	7
valid_sources[0x2f]	11475	1			T2	3		T3	3		T4	4
valid_sources[0x30]	14895	1			T2	4		T3	4		T4	4
valid_sources[0x31]	19127	1			T2	5		T3	3		T4	9
valid_sources[0x32]	11540	1			T2	5		T3	6		T4	2
valid_sources[0x33]	12173	1			T2	3		T3	2		T5	1
valid_sources[0x34]	15276	1			T2	2		T3	21		T4	1
valid_sources[0x35]	11341	1			T2	5		T3	5		T4	10
valid_sources[0x36]	11132	1			T3	3		T4	3		T12	1
valid_sources[0x37]	10957	1			T1	3		T2	6		T3	6
valid_sources[0x38]	11493	1			T2	3		T3	7		T4	1
valid_sources[0x39]	11454	1			T2	6		T3	5		T4	3
valid_sources[0x3a]	11503	1			T2	1		T3	21		T4	4
valid_sources[0x3b]	12534	1			T2	4		T3	7		T4	9
valid_sources[0x3c]	12602	1			T2	5		T3	15		T4	3
valid_sources[0x3d]	11139	1			T2	3		T3	4		T4	1
valid_sources[0x3e]	11575	1			T2	4		T4	2		T5	2
valid_sources[0x3f]	10869	1			T2	4		T3	7		T4	14
valid_sources[0x40]	11137	1			T2	10		T3	9		T4	6
valid_sources[0x41]	12439	1			T2	2		T3	1		T4	8
valid_sources[0x42]	13555	1			T2	6		T3	4		T5	1
valid_sources[0x43]	27265	1			T2	3		T3	3		T4	4
valid_sources[0x44]	12008	1			T2	6		T3	2		T4	2
valid_sources[0x45]	11307	1			T2	3		T3	16		T5	1
valid_sources[0x46]	12394	1			T2	5		T3	7		T4	9
valid_sources[0x47]	11880	1			T2	6		T3	4		T4	6
valid_sources[0x48]	11953	1			T2	3		T3	2		T12	4
valid_sources[0x49]	14056	1			T2	3		T3	5		T4	4
valid_sources[0x4a]	12728	1			T2	1		T3	3		T4	1
valid_sources[0x4b]	11764	1			T2	10		T3	9		T4	1
valid_sources[0x4c]	11799	1			T2	10		T3	7		T4	8
valid_sources[0x4d]	11198	1			T3	7		T4	3		T5	1
valid_sources[0x4e]	12098	1			T2	6		T3	11		T5	2
valid_sources[0x4f]	11925	1			T2	1		T3	2		T4	6
valid_sources[0x50]	11476	1			T2	2		T3	8		T4	4
valid_sources[0x51]	12377	1			T2	1		T3	15		T5	1
valid_sources[0x52]	11943	1			T2	4		T3	5		T4	9
valid_sources[0x53]	11812	1			T2	2		T3	8		T4	4
valid_sources[0x54]	19076	1			T2	6		T3	1		T4	15
valid_sources[0x55]	11709	1			T2	13		T3	12		T5	2
valid_sources[0x56]	11478	1			T2	2		T3	9		T4	3
valid_sources[0x57]	11551	1			T2	1		T3	4		T4	1
valid_sources[0x58]	11329	1			T2	1		T3	3		T4	5
valid_sources[0x59]	11757	1			T2	8		T3	5		T4	6
valid_sources[0x5a]	11426	1			T2	4		T3	11		T4	4
valid_sources[0x5b]	13298	1			T2	5		T3	1		T4	4
valid_sources[0x5c]	10900	1			T1	3		T2	9		T3	9
valid_sources[0x5d]	11687	1			T3	10		T5	3		T12	3
valid_sources[0x5e]	11762	1			T2	2		T3	2		T4	3
valid_sources[0x5f]	11992	1			T2	4		T3	2		T4	10
valid_sources[0x60]	11303	1			T2	6		T3	7		T4	3
valid_sources[0x61]	11959	1			T2	6		T3	9		T5	1
valid_sources[0x62]	11532	1			T2	1		T3	4		T4	3
valid_sources[0x63]	11897	1			T2	6		T4	2		T12	3
valid_sources[0x64]	11039	1			T2	3		T3	5		T4	4
valid_sources[0x65]	12622	1			T2	1		T3	4		T4	1
valid_sources[0x66]	11031	1			T2	3		T3	7		T4	7
valid_sources[0x67]	11929	1			T2	6		T3	17		T4	1
valid_sources[0x68]	11350	1			T3	6		T4	7		T12	7
valid_sources[0x69]	11405	1			T2	1		T3	6		T4	5
valid_sources[0x6a]	11959	1			T2	2		T3	4		T5	3
valid_sources[0x6b]	13487	1			T2	3		T3	2		T4	9
valid_sources[0x6c]	11528	1			T2	4		T3	1		T4	5
valid_sources[0x6d]	11649	1			T2	2		T3	6		T4	1
valid_sources[0x6e]	13786	1			T2	13		T4	1		T5	3
valid_sources[0x6f]	11201	1			T2	14		T3	1		T4	10
valid_sources[0x70]	11377	1			T2	7		T3	7		T4	3
valid_sources[0x71]	11543	1			T2	2		T3	8		T4	6
valid_sources[0x72]	14571	1			T2	3		T3	6		T4	2
valid_sources[0x73]	13366	1			T2	5		T3	8		T4	3
valid_sources[0x74]	11407	1			T1	1		T2	11		T3	3
valid_sources[0x75]	11993	1			T2	2		T3	10		T4	3
valid_sources[0x76]	11543	1			T2	5		T3	20		T4	1
valid_sources[0x77]	11082	1			T2	9		T3	15		T4	2
valid_sources[0x78]	12650	1			T2	6		T3	1		T4	7
valid_sources[0x79]	10668	1			T2	2		T3	5		T4	1
valid_sources[0x7a]	14103	1			T2	5		T3	12		T4	6
valid_sources[0x7b]	14539	1			T2	4		T3	5		T4	2
valid_sources[0x7c]	11182	1			T2	9		T3	1		T4	2
valid_sources[0x7d]	11415	1			T2	4		T3	1		T4	3
valid_sources[0x7e]	11420	1			T2	2		T3	4		T4	4
valid_sources[0x7f]	17808	1			T2	5		T3	12		T4	3
valid_sources[0x80]	14314	1			T2	10		T3	4		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1456667

1

T2

214

T3

534

T4

369

values[0x0]

all_enables

biggest_size

149433

1

T1

8

T2

218

T3

206

values[0x1]

all_enables

biggest_size

148371

1

T1

4

T2

236

T3

194