Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	105860447	14756	0	0
claim_transition_if_regwen_rd_A	105860447	1545	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105860447	14756	0	0
T26	36996	0	0	0
T27	66887	0	0	0
T41	232111	0	0	0
T43	0	4	0	0
T95	155599	3	0	0
T108	0	3	0	0
T112	0	5	0	0
T147	0	9	0	0
T148	0	7	0	0
T149	0	6	0	0
T150	0	21	0	0
T151	0	13	0	0
T152	0	2	0	0
T153	20388	0	0	0
T154	6172	0	0	0
T155	28389	0	0	0
T156	59629	0	0	0
T157	5097	0	0	0
T158	38421	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105860447	1545	0	0
T43	249759	3	0	0
T69	1001	0	0	0
T105	124075	0	0	0
T114	0	57	0	0
T152	0	4	0	0
T159	0	11	0	0
T160	0	8	0	0
T161	0	8	0	0
T162	0	5	0	0
T163	0	150	0	0
T164	0	3	0	0
T165	0	3	0	0
T166	781717	0	0	0
T167	62587	0	0	0
T168	4481	0	0	0
T169	45847	0	0	0
T170	37300	0	0	0
T171	1475	0	0	0
T172	30622	0	0	0