Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1619215	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1840414

1

T1

739

T2

185

T3

768

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3116284	1			T1	598		T2	133		T3	589
values[0x0]	171244	1			T1	274		T2	76		T3	287
values[0x1]	172101	1			T1	294		T2	68		T3	273

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1286066	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2173563

1

T1

845

T2

210

T3

858

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10241	1			T1	13		T11	3		T14	9
valid_sources[0x01]	9840	1			T1	6		T3	13		T11	10
valid_sources[0x02]	19511	1			T1	6		T11	5		T21	5
valid_sources[0x03]	9761	1			T1	5		T2	1		T3	24
valid_sources[0x04]	9921	1			T1	10		T2	5		T11	3
valid_sources[0x05]	10270	1			T1	9		T2	5		T3	11
valid_sources[0x06]	13150	1			T1	2		T11	7		T21	4
valid_sources[0x07]	9498	1			T1	7		T2	2		T3	1
valid_sources[0x08]	9639	1			T1	1		T2	2		T3	3
valid_sources[0x09]	12116	1			T1	4		T3	6		T11	2
valid_sources[0x0a]	10165	1			T1	6		T2	4		T11	7
valid_sources[0x0b]	13640	1			T1	9		T2	2		T3	7
valid_sources[0x0c]	10127	1			T1	3		T2	1		T3	14
valid_sources[0x0d]	11434	1			T1	12		T3	9		T11	6
valid_sources[0x0e]	10008	1			T1	5		T3	6		T11	8
valid_sources[0x0f]	9861	1			T1	6		T11	10		T21	9
valid_sources[0x10]	9892	1			T1	6		T3	5		T11	4
valid_sources[0x11]	10025	1			T1	4		T11	11		T16	4
valid_sources[0x12]	9690	1			T1	10		T2	3		T11	4
valid_sources[0x13]	13456	1			T1	5		T2	2		T3	6
valid_sources[0x14]	16139	1			T1	12		T2	1		T11	6
valid_sources[0x15]	12455	1			T1	9		T2	1		T3	9
valid_sources[0x16]	9807	1			T1	9		T2	3		T3	8
valid_sources[0x17]	9831	1			T2	4		T11	4		T21	3
valid_sources[0x18]	11886	1			T1	5		T11	3		T14	12
valid_sources[0x19]	9768	1			T1	10		T2	3		T3	9
valid_sources[0x1a]	11096	1			T1	3		T11	10		T21	5
valid_sources[0x1b]	10824	1			T1	2		T3	1		T16	3
valid_sources[0x1c]	11254	1			T1	1		T3	1		T11	8
valid_sources[0x1d]	10371	1			T1	3		T3	6		T11	4
valid_sources[0x1e]	9720	1			T1	8		T2	1		T11	6
valid_sources[0x1f]	10191	1			T1	7		T2	2		T11	5
valid_sources[0x20]	10474	1			T11	8		T21	6		T22	5
valid_sources[0x21]	13777	1			T1	7		T3	19		T11	8
valid_sources[0x22]	9284	1			T1	4		T2	5		T11	4
valid_sources[0x23]	11126	1			T1	9		T2	1		T11	9
valid_sources[0x24]	9703	1			T1	6		T11	5		T21	3
valid_sources[0x25]	9534	1			T1	17		T3	3		T11	5
valid_sources[0x26]	19229	1			T2	5		T3	2		T11	7
valid_sources[0x27]	9573	1			T1	1		T3	12		T11	6
valid_sources[0x28]	11605	1			T1	13		T2	1		T11	12
valid_sources[0x29]	11107	1			T1	9		T11	5		T12	1
valid_sources[0x2a]	9316	1			T1	7		T3	14		T11	5
valid_sources[0x2b]	10365	1			T1	5		T2	7		T11	5
valid_sources[0x2c]	12829	1			T1	4		T3	5		T11	1
valid_sources[0x2d]	10786	1			T1	2		T3	1		T11	5
valid_sources[0x2e]	11552	1			T2	1		T11	1		T14	15
valid_sources[0x2f]	10415	1			T1	13		T11	4		T14	4
valid_sources[0x30]	9993	1			T1	7		T2	4		T11	7
valid_sources[0x31]	11994	1			T1	5		T2	1		T11	2
valid_sources[0x32]	9916	1			T1	4		T11	5		T4	4
valid_sources[0x33]	9751	1			T1	3		T3	10		T11	8
valid_sources[0x34]	18056	1			T1	3		T2	2		T11	6
valid_sources[0x35]	10982	1			T1	3		T3	24		T11	11
valid_sources[0x36]	13504	1			T1	4		T2	4		T11	8
valid_sources[0x37]	11093	1			T1	6		T2	2		T3	4
valid_sources[0x38]	10592	1			T3	12		T11	3		T21	9
valid_sources[0x39]	10587	1			T1	8		T2	2		T3	4
valid_sources[0x3a]	9876	1			T1	6		T11	10		T12	4
valid_sources[0x3b]	9520	1			T1	2		T3	6		T11	3
valid_sources[0x3c]	11658	1			T1	5		T3	19		T11	6
valid_sources[0x3d]	10173	1			T1	1		T11	7		T14	18
valid_sources[0x3e]	9966	1			T1	5		T11	7		T14	2
valid_sources[0x3f]	10235	1			T1	9		T2	3		T3	6
valid_sources[0x40]	62171	1			T1	5		T2	1		T11	15
valid_sources[0x41]	10831	1			T1	2		T11	3		T21	7
valid_sources[0x42]	10137	1			T1	5		T2	1		T11	8
valid_sources[0x43]	10631	1			T1	5		T2	3		T3	25
valid_sources[0x44]	10286	1			T1	4		T2	1		T3	31
valid_sources[0x45]	9797	1			T1	6		T2	1		T3	5
valid_sources[0x46]	10360	1			T3	4		T11	7		T4	1
valid_sources[0x47]	11783	1			T1	7		T2	1		T11	10
valid_sources[0x48]	22591	1			T1	5		T2	5		T11	7
valid_sources[0x49]	10351	1			T1	4		T2	5		T3	2
valid_sources[0x4a]	10648	1			T1	3		T11	7		T4	1
valid_sources[0x4b]	35384	1			T2	2		T11	8		T21	5
valid_sources[0x4c]	10408	1			T1	6		T3	18		T11	7
valid_sources[0x4d]	9824	1			T1	10		T2	1		T11	3
valid_sources[0x4e]	13382	1			T1	8		T2	1		T11	3
valid_sources[0x4f]	11270	1			T1	7		T11	6		T14	10
valid_sources[0x50]	25626	1			T1	1		T2	5		T3	6
valid_sources[0x51]	10030	1			T1	5		T2	1		T11	8
valid_sources[0x52]	10038	1			T1	4		T11	7		T14	11
valid_sources[0x53]	9703	1			T1	2		T2	2		T11	3
valid_sources[0x54]	10549	1			T1	9		T2	2		T11	3
valid_sources[0x55]	10189	1			T1	2		T2	2		T11	5
valid_sources[0x56]	14273	1			T1	2		T2	1		T11	6
valid_sources[0x57]	10030	1			T1	2		T2	1		T3	9
valid_sources[0x58]	9821	1			T1	3		T2	1		T11	4
valid_sources[0x59]	9200	1			T1	6		T3	6		T11	5
valid_sources[0x5a]	11668	1			T1	11		T3	2		T11	6
valid_sources[0x5b]	10906	1			T1	4		T2	1		T11	6
valid_sources[0x5c]	11376	1			T1	8		T3	14		T11	8
valid_sources[0x5d]	18241	1			T1	3		T2	1		T11	6
valid_sources[0x5e]	9796	1			T1	2		T3	12		T11	4
valid_sources[0x5f]	9362	1			T1	1		T11	3		T4	1
valid_sources[0x60]	15624	1			T1	4		T3	1		T11	4
valid_sources[0x61]	9723	1			T1	6		T11	4		T14	6
valid_sources[0x62]	9738	1			T1	1		T2	3		T3	10
valid_sources[0x63]	9604	1			T11	10		T14	2		T16	3
valid_sources[0x64]	9571	1			T1	7		T2	1		T3	13
valid_sources[0x65]	10531	1			T1	4		T2	1		T3	21
valid_sources[0x66]	10066	1			T1	4		T2	1		T3	1
valid_sources[0x67]	11347	1			T1	4		T2	2		T11	5
valid_sources[0x68]	10975	1			T1	1		T11	9		T14	10
valid_sources[0x69]	18994	1			T1	1		T11	7		T12	1
valid_sources[0x6a]	10408	1			T1	5		T3	4		T11	9
valid_sources[0x6b]	10308	1			T1	5		T2	1		T3	4
valid_sources[0x6c]	9274	1			T1	3		T3	7		T11	6
valid_sources[0x6d]	9834	1			T1	4		T11	6		T14	9
valid_sources[0x6e]	50347	1			T1	7		T11	1		T14	2
valid_sources[0x6f]	9809	1			T1	5		T3	23		T11	7
valid_sources[0x70]	11431	1			T1	8		T11	1		T4	1
valid_sources[0x71]	10357	1			T1	3		T11	8		T4	1
valid_sources[0x72]	10558	1			T1	8		T3	3		T11	5
valid_sources[0x73]	11640	1			T1	7		T2	4		T11	5
valid_sources[0x74]	9989	1			T1	3		T11	6		T12	4
valid_sources[0x75]	9384	1			T11	5		T14	4		T16	1
valid_sources[0x76]	10052	1			T1	4		T2	2		T11	8
valid_sources[0x77]	10030	1			T1	5		T3	5		T11	6
valid_sources[0x78]	10298	1			T2	1		T3	29		T11	7
valid_sources[0x79]	10877	1			T1	7		T2	1		T11	5
valid_sources[0x7a]	9773	1			T1	5		T11	6		T21	5
valid_sources[0x7b]	9983	1			T1	1		T2	3		T11	3
valid_sources[0x7c]	16830	1			T1	1		T11	7		T21	7
valid_sources[0x7d]	10145	1			T1	7		T11	7		T21	4
valid_sources[0x7e]	9877	1			T1	1		T11	5		T15	77
valid_sources[0x7f]	12836	1			T1	4		T2	2		T3	5
valid_sources[0x80]	44856	1			T1	4		T2	1		T11	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1543832

1

T1

243

T2

59

T3

282

values[0x0]

all_enables

biggest_size

148813

1

T1

243

T2

67

T3

249

values[0x1]

all_enables

biggest_size

147769

1

T1

253

T2

59

T3

237