Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	110448720	12664	0	0
claim_transition_if_regwen_rd_A	110448720	970	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110448720	12664	0	0
T9	45280	0	0	0
T19	292647	6	0	0
T20	101601	0	0	0
T39	963	0	0	0
T48	35782	0	0	0
T58	0	1	0	0
T67	0	2	0	0
T72	1803	0	0	0
T75	16363	0	0	0
T85	14218	0	0	0
T96	0	1	0	0
T102	0	1	0	0
T115	0	2	0	0
T118	0	7	0	0
T156	0	4	0	0
T157	0	4	0	0
T158	0	1	0	0
T159	13098	0	0	0
T160	33225	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110448720	970	0	0
T58	0	3	0	0
T67	0	1	0	0
T115	346569	1	0	0
T123	0	26	0	0
T124	0	7	0	0
T129	0	18	0	0
T141	0	53	0	0
T154	891159	0	0	0
T161	0	3	0	0
T162	0	267	0	0
T163	0	55	0	0
T164	991	0	0	0
T165	1142	0	0	0
T166	990	0	0	0
T167	29775	0	0	0
T168	28323	0	0	0
T169	23661	0	0	0
T170	2686	0	0	0
T171	30328	0	0	0