Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1899659	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2128149

1

T2

226

T3

1

T4

1326

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3664628	1			T2	164		T3	2		T4	1150
values[0x0]	181121	1			T2	91		T4	509		T9	208
values[0x1]	182059	1			T2	101		T3	1		T4	539

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1509612	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2518196

1

T2

260

T3

2

T4

1524

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11938	1			T4	6		T10	1		T12	9
valid_sources[0x01]	12495	1			T4	17		T12	11		T15	4
valid_sources[0x02]	12012	1			T4	4		T10	2		T12	12
valid_sources[0x03]	11867	1			T4	2		T10	1		T12	12
valid_sources[0x04]	12046	1			T4	10		T12	9		T15	14
valid_sources[0x05]	10779	1			T4	11		T12	9		T15	1
valid_sources[0x06]	114544	1			T4	4		T12	6		T13	2
valid_sources[0x07]	13448	1			T4	9		T10	3		T12	3
valid_sources[0x08]	11469	1			T4	7		T12	12		T13	1
valid_sources[0x09]	23781	1			T4	6		T12	7		T15	7
valid_sources[0x0a]	11737	1			T4	8		T10	3		T12	9
valid_sources[0x0b]	11209	1			T4	3		T12	7		T15	22
valid_sources[0x0c]	13935	1			T4	16		T12	15		T13	2
valid_sources[0x0d]	13586	1			T4	7		T10	2		T12	4
valid_sources[0x0e]	13463	1			T4	5		T12	13		T15	2
valid_sources[0x0f]	12048	1			T4	9		T12	5		T13	2
valid_sources[0x10]	115483	1			T4	6		T12	13		T15	2
valid_sources[0x11]	21722	1			T4	12		T12	18		T14	1
valid_sources[0x12]	11714	1			T4	16		T12	7		T15	4
valid_sources[0x13]	54567	1			T4	6		T10	1		T12	13
valid_sources[0x14]	11100	1			T4	6		T12	8		T15	10
valid_sources[0x15]	12356	1			T4	4		T10	1		T12	10
valid_sources[0x16]	11583	1			T4	11		T12	17		T15	3
valid_sources[0x17]	12265	1			T4	11		T12	12		T15	13
valid_sources[0x18]	11803	1			T4	7		T12	8		T15	9
valid_sources[0x19]	11909	1			T4	11		T10	1		T12	7
valid_sources[0x1a]	65645	1			T4	14		T12	13		T13	1
valid_sources[0x1b]	11419	1			T4	7		T12	17		T15	8
valid_sources[0x1c]	11305	1			T4	10		T12	8		T15	4
valid_sources[0x1d]	12065	1			T4	6		T12	5		T15	3
valid_sources[0x1e]	11598	1			T4	9		T12	9		T15	1
valid_sources[0x1f]	11496	1			T4	3		T10	2		T12	9
valid_sources[0x20]	11107	1			T4	7		T10	1		T12	5
valid_sources[0x21]	11826	1			T4	10		T12	5		T15	19
valid_sources[0x22]	12257	1			T4	5		T10	1		T12	9
valid_sources[0x23]	34245	1			T4	4		T10	6		T12	3
valid_sources[0x24]	11363	1			T4	5		T12	6		T13	2
valid_sources[0x25]	15614	1			T4	4		T12	19		T15	6
valid_sources[0x26]	11468	1			T4	11		T12	9		T13	1
valid_sources[0x27]	12146	1			T4	15		T12	13		T15	1
valid_sources[0x28]	15278	1			T4	5		T10	2		T12	8
valid_sources[0x29]	11649	1			T4	8		T10	3		T12	9
valid_sources[0x2a]	11457	1			T4	10		T10	1		T12	12
valid_sources[0x2b]	13034	1			T4	10		T12	8		T15	5
valid_sources[0x2c]	11427	1			T4	5		T10	2		T12	10
valid_sources[0x2d]	11524	1			T4	15		T10	3		T12	10
valid_sources[0x2e]	13989	1			T4	14		T10	1		T12	19
valid_sources[0x2f]	11416	1			T4	4		T12	6		T15	2
valid_sources[0x30]	11739	1			T4	5		T12	13		T15	4
valid_sources[0x31]	11656	1			T4	9		T10	1		T12	19
valid_sources[0x32]	21093	1			T4	7		T12	8		T15	8
valid_sources[0x33]	11405	1			T4	7		T10	3		T12	12
valid_sources[0x34]	11244	1			T4	10		T10	3		T12	8
valid_sources[0x35]	15583	1			T4	9		T12	15		T44	4
valid_sources[0x36]	13474	1			T4	3		T12	9		T14	1
valid_sources[0x37]	12123	1			T4	10		T12	11		T15	9
valid_sources[0x38]	11312	1			T4	7		T10	2		T12	9
valid_sources[0x39]	13446	1			T4	13		T12	7		T44	5
valid_sources[0x3a]	12020	1			T4	10		T12	10		T13	4
valid_sources[0x3b]	11598	1			T4	6		T12	17		T13	3
valid_sources[0x3c]	11519	1			T4	9		T10	1		T12	16
valid_sources[0x3d]	11587	1			T4	3		T12	10		T15	7
valid_sources[0x3e]	14904	1			T4	9		T12	9		T44	2
valid_sources[0x3f]	13703	1			T4	4		T12	16		T15	17
valid_sources[0x40]	10937	1			T4	8		T10	3		T12	15
valid_sources[0x41]	15731	1			T3	3		T4	7		T10	2
valid_sources[0x42]	11273	1			T4	6		T10	1		T12	18
valid_sources[0x43]	11564	1			T4	3		T10	1		T12	15
valid_sources[0x44]	11612	1			T4	10		T10	2		T12	10
valid_sources[0x45]	11255	1			T4	9		T12	10		T13	2
valid_sources[0x46]	12053	1			T4	7		T10	3		T12	17
valid_sources[0x47]	61385	1			T4	7		T12	14		T15	12
valid_sources[0x48]	11408	1			T4	9		T12	15		T15	7
valid_sources[0x49]	14143	1			T4	8		T12	21		T15	17
valid_sources[0x4a]	11423	1			T4	6		T12	15		T15	21
valid_sources[0x4b]	11778	1			T4	6		T12	8		T15	1
valid_sources[0x4c]	12305	1			T4	13		T9	874		T10	1
valid_sources[0x4d]	12327	1			T4	8		T12	18		T44	4
valid_sources[0x4e]	11585	1			T4	6		T12	7		T44	3
valid_sources[0x4f]	11892	1			T4	3		T12	8		T15	2
valid_sources[0x50]	13493	1			T4	6		T12	7		T15	6
valid_sources[0x51]	11020	1			T4	7		T10	2		T12	10
valid_sources[0x52]	11284	1			T4	11		T12	11		T44	3
valid_sources[0x53]	11829	1			T4	12		T10	1		T12	7
valid_sources[0x54]	11233	1			T4	8		T10	2		T12	10
valid_sources[0x55]	11185	1			T4	13		T10	2		T12	2
valid_sources[0x56]	12743	1			T4	12		T10	2		T12	11
valid_sources[0x57]	12249	1			T4	4		T10	1		T12	10
valid_sources[0x58]	12049	1			T4	10		T10	1		T12	9
valid_sources[0x59]	12975	1			T4	8		T10	2		T12	5
valid_sources[0x5a]	12412	1			T4	18		T12	17		T14	1
valid_sources[0x5b]	20356	1			T4	7		T12	17		T15	6
valid_sources[0x5c]	11304	1			T4	16		T10	3		T12	11
valid_sources[0x5d]	26501	1			T4	13		T12	11		T15	3
valid_sources[0x5e]	11504	1			T4	7		T10	2		T12	12
valid_sources[0x5f]	12244	1			T4	2		T12	10		T15	2
valid_sources[0x60]	13305	1			T4	5		T10	1		T12	15
valid_sources[0x61]	11504	1			T4	11		T12	5		T44	2
valid_sources[0x62]	12068	1			T4	12		T10	1		T12	8
valid_sources[0x63]	11362	1			T4	14		T12	8		T15	2
valid_sources[0x64]	11548	1			T4	3		T12	6		T13	2
valid_sources[0x65]	11706	1			T4	11		T10	1		T12	20
valid_sources[0x66]	15158	1			T4	10		T10	3		T12	11
valid_sources[0x67]	13403	1			T4	7		T10	1		T12	11
valid_sources[0x68]	11908	1			T4	11		T12	18		T14	1
valid_sources[0x69]	11419	1			T4	7		T12	20		T15	5
valid_sources[0x6a]	11753	1			T4	11		T10	3		T12	12
valid_sources[0x6b]	10782	1			T4	6		T12	15		T15	6
valid_sources[0x6c]	11808	1			T4	10		T10	1		T12	15
valid_sources[0x6d]	12285	1			T4	14		T12	14		T15	1
valid_sources[0x6e]	12743	1			T4	7		T10	1		T12	13
valid_sources[0x6f]	23512	1			T4	12		T12	15		T14	1
valid_sources[0x70]	62080	1			T4	12		T12	17		T15	10
valid_sources[0x71]	11616	1			T4	10		T10	3		T12	12
valid_sources[0x72]	13695	1			T4	9		T10	1		T12	7
valid_sources[0x73]	11880	1			T4	8		T10	1		T12	8
valid_sources[0x74]	11852	1			T4	15		T12	11		T15	6
valid_sources[0x75]	12084	1			T4	3		T10	1		T12	16
valid_sources[0x76]	11562	1			T4	9		T12	4		T15	6
valid_sources[0x77]	11460	1			T4	8		T12	19		T14	1
valid_sources[0x78]	10736	1			T4	6		T12	16		T15	4
valid_sources[0x79]	11885	1			T4	7		T12	23		T15	5
valid_sources[0x7a]	14281	1			T4	7		T10	3		T12	8
valid_sources[0x7b]	11736	1			T4	8		T12	17		T15	5
valid_sources[0x7c]	11823	1			T4	10		T10	3		T12	13
valid_sources[0x7d]	11432	1			T4	11		T12	14		T15	7
valid_sources[0x7e]	11386	1			T4	9		T12	8		T44	3
valid_sources[0x7f]	13473	1			T4	5		T10	1		T12	14
valid_sources[0x80]	12786	1			T4	10		T10	3		T12	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1814912

1

T2

61

T3

1

T4

414

values[0x0]

all_enables

biggest_size

157072

1

T2

81

T4

437

T9

186

values[0x1]

all_enables

biggest_size

156165

1

T2

84

T4

475

T9

179