Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	112489239	14391	0	0
claim_transition_if_regwen_rd_A	112489239	1382	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112489239	14391	0	0
T22	42791	0	0	0
T23	38052	0	0	0
T41	106790	0	0	0
T43	177735	1	0	0
T72	4537	0	0	0
T73	1282	0	0	0
T90	181892	0	0	0
T94	0	4	0	0
T104	0	2	0	0
T105	0	8	0	0
T108	0	12	0	0
T112	0	7	0	0
T150	0	2	0	0
T151	0	12	0	0
T152	0	9	0	0
T153	0	4	0	0
T154	43748	0	0	0
T155	26535	0	0	0
T156	1113	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112489239	1382	0	0
T95	10932	0	0	0
T120	0	20	0	0
T128	0	17	0	0
T157	129121	10	0	0
T158	0	17	0	0
T159	0	48	0	0
T160	0	8	0	0
T161	0	7	0	0
T162	0	5	0	0
T163	0	10	0	0
T164	0	1	0	0
T165	49499	0	0	0
T166	16329	0	0	0
T167	132121	0	0	0
T168	4199	0	0	0
T169	54901	0	0	0
T170	1346	0	0	0
T171	1603	0	0	0
T172	5532	0	0	0