Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1836165	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2064576

1

T1

628

T2

106

T3

246

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3544619	1			T1	430		T2	95		T3	225
values[0x0]	177620	1			T1	246		T2	36		T3	84
values[0x1]	178502	1			T1	234		T2	44		T3	105

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1459149	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2441592

1

T1

705

T2

119

T3

286

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	101324	1			T2	1		T3	4		T10	3
valid_sources[0x01]	19294	1			T3	1		T4	2		T10	5
valid_sources[0x02]	10871	1			T3	1		T4	2		T10	6
valid_sources[0x03]	40101	1			T10	9		T11	65		T12	4
valid_sources[0x04]	8194	1			T2	1		T10	6		T11	65
valid_sources[0x05]	8493	1			T3	4		T4	2		T10	7
valid_sources[0x06]	8608	1			T2	1		T3	1		T10	1
valid_sources[0x07]	9913	1			T2	1		T3	1		T4	1
valid_sources[0x08]	9549	1			T2	1		T3	3		T4	1
valid_sources[0x09]	8938	1			T3	1		T4	2		T10	5
valid_sources[0x0a]	9589	1			T2	1		T3	2		T4	1
valid_sources[0x0b]	9813	1			T4	1		T10	8		T11	80
valid_sources[0x0c]	120906	1			T2	4		T3	1		T4	1
valid_sources[0x0d]	8794	1			T3	1		T10	6		T11	49
valid_sources[0x0e]	10223	1			T2	2		T4	1		T10	3
valid_sources[0x0f]	8919	1			T10	3		T11	58		T12	5
valid_sources[0x10]	8936	1			T3	4		T10	3		T11	62
valid_sources[0x11]	24261	1			T3	4		T4	3		T10	3
valid_sources[0x12]	9065	1			T2	2		T3	3		T10	6
valid_sources[0x13]	8895	1			T2	1		T3	2		T4	1
valid_sources[0x14]	8720	1			T2	2		T3	2		T4	1
valid_sources[0x15]	26241	1			T2	1		T4	2		T10	1
valid_sources[0x16]	39809	1			T2	1		T3	2		T4	1
valid_sources[0x17]	8844	1			T2	3		T3	1		T10	4
valid_sources[0x18]	8891	1			T10	7		T11	59		T12	3
valid_sources[0x19]	75225	1			T2	1		T3	1		T4	2
valid_sources[0x1a]	39290	1			T3	3		T10	7		T11	43
valid_sources[0x1b]	8495	1			T4	2		T10	7		T11	67
valid_sources[0x1c]	8522	1			T3	1		T10	3		T11	60
valid_sources[0x1d]	9919	1			T3	1		T10	3		T11	63
valid_sources[0x1e]	10267	1			T2	1		T4	5		T10	4
valid_sources[0x1f]	8726	1			T2	2		T3	1		T10	6
valid_sources[0x20]	8436	1			T3	2		T10	4		T11	61
valid_sources[0x21]	9702	1			T3	3		T10	5		T11	73
valid_sources[0x22]	8931	1			T2	1		T3	2		T4	3
valid_sources[0x23]	9006	1			T10	10		T11	51		T12	7
valid_sources[0x24]	10045	1			T10	2		T11	67		T12	7
valid_sources[0x25]	8793	1			T4	3		T10	10		T11	54
valid_sources[0x26]	8737	1			T4	1		T10	8		T11	52
valid_sources[0x27]	8913	1			T2	1		T3	2		T10	5
valid_sources[0x28]	8177	1			T2	2		T4	1		T10	8
valid_sources[0x29]	9357	1			T3	2		T10	6		T11	68
valid_sources[0x2a]	8541	1			T3	2		T10	1		T11	77
valid_sources[0x2b]	9298	1			T3	4		T10	7		T11	71
valid_sources[0x2c]	8706	1			T3	2		T4	1		T10	2
valid_sources[0x2d]	10032	1			T4	3		T10	5		T11	58
valid_sources[0x2e]	8488	1			T3	1		T10	8		T11	61
valid_sources[0x2f]	10177	1			T2	1		T3	1		T4	1
valid_sources[0x30]	11113	1			T3	1		T10	3		T11	58
valid_sources[0x31]	8471	1			T2	2		T3	1		T4	1
valid_sources[0x32]	8919	1			T3	3		T4	2		T10	4
valid_sources[0x33]	47163	1			T2	2		T4	2		T10	8
valid_sources[0x34]	12224	1			T10	4		T11	51		T12	2
valid_sources[0x35]	11319	1			T2	1		T4	2		T10	2
valid_sources[0x36]	9143	1			T3	2		T4	1		T10	1
valid_sources[0x37]	50741	1			T2	3		T10	6		T11	54
valid_sources[0x38]	9003	1			T3	1		T4	1		T10	5
valid_sources[0x39]	10657	1			T4	2		T10	5		T11	69
valid_sources[0x3a]	8840	1			T3	2		T10	3		T11	70
valid_sources[0x3b]	9660	1			T3	1		T4	1		T10	14
valid_sources[0x3c]	8614	1			T2	2		T3	1		T4	2
valid_sources[0x3d]	8975	1			T2	1		T4	1		T10	6
valid_sources[0x3e]	8855	1			T4	1		T10	6		T11	74
valid_sources[0x3f]	23387	1			T2	2		T3	1		T10	8
valid_sources[0x40]	27367	1			T10	2		T11	80		T12	6
valid_sources[0x41]	8279	1			T3	2		T10	1		T11	60
valid_sources[0x42]	9935	1			T3	2		T10	6		T11	60
valid_sources[0x43]	8656	1			T3	1		T4	2		T10	6
valid_sources[0x44]	27078	1			T3	4		T4	1		T10	3
valid_sources[0x45]	59811	1			T3	3		T10	4		T11	57
valid_sources[0x46]	11409	1			T2	1		T3	4		T10	2
valid_sources[0x47]	58896	1			T2	1		T3	1		T10	1
valid_sources[0x48]	8728	1			T3	1		T4	3		T10	2
valid_sources[0x49]	8469	1			T2	2		T3	4		T10	12
valid_sources[0x4a]	20310	1			T3	1		T4	2		T10	8
valid_sources[0x4b]	60845	1			T2	2		T3	1		T4	1
valid_sources[0x4c]	20152	1			T3	1		T4	4		T10	7
valid_sources[0x4d]	8719	1			T3	2		T10	1		T11	67
valid_sources[0x4e]	12480	1			T2	1		T3	1		T4	1
valid_sources[0x4f]	8776	1			T2	3		T4	4		T10	10
valid_sources[0x50]	10418	1			T3	2		T4	3		T10	13
valid_sources[0x51]	9352	1			T3	2		T4	3		T10	10
valid_sources[0x52]	8660	1			T3	5		T10	2		T11	66
valid_sources[0x53]	8235	1			T2	1		T4	1		T10	7
valid_sources[0x54]	9158	1			T2	1		T4	1		T10	5
valid_sources[0x55]	8564	1			T2	1		T4	3		T10	2
valid_sources[0x56]	8911	1			T2	1		T3	2		T10	1
valid_sources[0x57]	8959	1			T3	3		T10	10		T11	49
valid_sources[0x58]	11370	1			T10	4		T11	57		T12	1
valid_sources[0x59]	14018	1			T4	1		T10	8		T11	57
valid_sources[0x5a]	13272	1			T2	1		T10	4		T11	65
valid_sources[0x5b]	13446	1			T1	910		T2	1		T4	4
valid_sources[0x5c]	10696	1			T3	2		T4	1		T10	5
valid_sources[0x5d]	9093	1			T3	4		T10	6		T11	77
valid_sources[0x5e]	8670	1			T3	2		T10	2		T11	62
valid_sources[0x5f]	9134	1			T2	2		T4	3		T10	5
valid_sources[0x60]	8658	1			T10	5		T11	61		T12	4
valid_sources[0x61]	65992	1			T3	3		T4	1		T10	5
valid_sources[0x62]	9700	1			T2	1		T3	2		T4	6
valid_sources[0x63]	9066	1			T2	1		T3	5		T4	1
valid_sources[0x64]	8862	1			T10	8		T11	72		T12	8
valid_sources[0x65]	9531	1			T3	3		T4	1		T10	6
valid_sources[0x66]	8749	1			T2	1		T3	2		T10	4
valid_sources[0x67]	9470	1			T2	1		T3	1		T10	9
valid_sources[0x68]	9645	1			T4	2		T10	6		T11	65
valid_sources[0x69]	80910	1			T3	7		T10	9		T11	58
valid_sources[0x6a]	8528	1			T10	6		T11	68		T12	6
valid_sources[0x6b]	20195	1			T3	3		T11	72		T12	5
valid_sources[0x6c]	18351	1			T3	1		T4	2		T10	2
valid_sources[0x6d]	9037	1			T3	1		T4	1		T10	1
valid_sources[0x6e]	8402	1			T3	1		T10	12		T11	56
valid_sources[0x6f]	22798	1			T3	1		T4	1		T10	4
valid_sources[0x70]	9501	1			T3	3		T10	7		T11	65
valid_sources[0x71]	8759	1			T3	1		T4	2		T10	3
valid_sources[0x72]	10271	1			T10	5		T11	55		T12	7
valid_sources[0x73]	8926	1			T3	5		T10	5		T11	74
valid_sources[0x74]	8363	1			T2	1		T4	1		T10	8
valid_sources[0x75]	9720	1			T3	3		T4	1		T10	2
valid_sources[0x76]	9132	1			T3	2		T4	1		T10	1
valid_sources[0x77]	48533	1			T2	1		T10	2		T11	52
valid_sources[0x78]	8952	1			T2	2		T3	1		T10	1
valid_sources[0x79]	9684	1			T3	1		T4	1		T10	5
valid_sources[0x7a]	11997	1			T3	2		T10	2		T11	72
valid_sources[0x7b]	8641	1			T2	2		T3	1		T4	3
valid_sources[0x7c]	10900	1			T2	3		T3	1		T10	5
valid_sources[0x7d]	10225	1			T4	2		T10	7		T11	58
valid_sources[0x7e]	10020	1			T2	1		T3	2		T4	1
valid_sources[0x7f]	8832	1			T2	1		T3	1		T4	2
valid_sources[0x80]	8440	1			T10	10		T11	58		T12	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1757433

1

T1

208

T2

40

T3

114

values[0x0]

all_enables

biggest_size

154101

1

T1

215

T2

31

T3

60

values[0x1]

all_enables

biggest_size

153042

1

T1

205

T2

35

T3

72