Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	120226978	16965	0	0
claim_transition_if_regwen_rd_A	120226978	1654	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120226978	16965	0	0
T24	13070	0	0	0
T50	0	20	0	0
T55	44433	0	0	0
T61	383243	4	0	0
T74	6542	0	0	0
T80	0	3	0	0
T102	331166	5	0	0
T103	0	4	0	0
T152	0	1	0	0
T153	0	7	0	0
T154	0	3	0	0
T155	0	20	0	0
T156	0	4	0	0
T157	1089	0	0	0
T158	5545	0	0	0
T159	27183	0	0	0
T160	30419	0	0	0
T161	8794	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120226978	1654	0	0
T24	13070	0	0	0
T55	44433	0	0	0
T61	383243	4	0	0
T74	6542	0	0	0
T102	331166	16	0	0
T115	0	8	0	0
T116	0	22	0	0
T117	0	20	0	0
T121	0	29	0	0
T123	0	5	0	0
T150	0	19	0	0
T157	1089	0	0	0
T158	5545	0	0	0
T159	27183	0	0	0
T160	30419	0	0	0
T161	8794	0	0	0
T162	0	12	0	0
T163	0	5	0	0