Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2190859 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 2415362 1 T1 4412 T2 14 T3 1013



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 4251144 1 T1 6952 T2 5 T3 813
values[0x0] 177417 1 T1 559 T2 8 T3 351
values[0x1] 177660 1 T1 546 T2 7 T3 337



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1742691 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 2863530 1 T1 5159 T2 15 T3 1106



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 9506 1 T3 6 T4 2 T12 5
valid_sources[0x01] 272825 1 T1 80 T3 6 T4 1
valid_sources[0x02] 10076 1 T1 10 T3 4 T4 2
valid_sources[0x03] 9940 1 T3 7 T4 4 T12 3
valid_sources[0x04] 9707 1 T1 6 T3 7 T4 1
valid_sources[0x05] 27570 1 T1 10 T3 6 T4 2
valid_sources[0x06] 25559 1 T1 19 T3 7 T4 1
valid_sources[0x07] 11124 1 T1 1 T3 4 T4 4
valid_sources[0x08] 10890 1 T1 14 T3 8 T4 4
valid_sources[0x09] 10543 1 T1 86 T3 8 T4 3
valid_sources[0x0a] 9979 1 T1 41 T3 7 T4 8
valid_sources[0x0b] 27579 1 T1 9 T3 5 T4 3
valid_sources[0x0c] 13098 1 T1 14 T3 7 T4 5
valid_sources[0x0d] 9681 1 T3 8 T4 2 T12 2
valid_sources[0x0e] 9811 1 T1 17 T3 4 T4 7
valid_sources[0x0f] 10282 1 T1 19 T3 6 T4 2
valid_sources[0x10] 13308 1 T3 10 T4 2 T12 3
valid_sources[0x11] 9613 1 T1 30 T3 5 T4 4
valid_sources[0x12] 12039 1 T1 75 T3 7 T4 4
valid_sources[0x13] 17641 1 T3 5 T4 4 T11 1
valid_sources[0x14] 12819 1 T1 15 T3 7 T4 3
valid_sources[0x15] 10094 1 T1 31 T3 9 T4 4
valid_sources[0x16] 9951 1 T1 17 T3 5 T4 3
valid_sources[0x17] 9880 1 T3 3 T4 4 T12 5
valid_sources[0x18] 10040 1 T1 51 T3 3 T4 6
valid_sources[0x19] 10079 1 T1 24 T3 8 T4 5
valid_sources[0x1a] 9962 1 T1 27 T3 4 T4 8
valid_sources[0x1b] 9329 1 T1 38 T3 5 T4 3
valid_sources[0x1c] 11497 1 T1 109 T3 7 T4 3
valid_sources[0x1d] 10391 1 T1 87 T3 10 T4 3
valid_sources[0x1e] 10702 1 T3 5 T4 3 T13 4
valid_sources[0x1f] 10627 1 T1 45 T3 7 T4 3
valid_sources[0x20] 10275 1 T1 16 T3 4 T4 5
valid_sources[0x21] 9686 1 T3 10 T4 2 T12 3
valid_sources[0x22] 10311 1 T1 119 T3 6 T4 3
valid_sources[0x23] 10073 1 T1 11 T3 3 T4 2
valid_sources[0x24] 12470 1 T1 37 T3 10 T4 3
valid_sources[0x25] 10180 1 T1 12 T3 6 T4 7
valid_sources[0x26] 9581 1 T1 18 T3 7 T4 1
valid_sources[0x27] 9982 1 T1 48 T3 5 T4 7
valid_sources[0x28] 11417 1 T3 3 T4 1 T12 5
valid_sources[0x29] 60183 1 T1 55 T3 4 T4 4
valid_sources[0x2a] 9683 1 T3 3 T4 9 T13 3
valid_sources[0x2b] 10178 1 T1 33 T3 7 T4 4
valid_sources[0x2c] 11629 1 T1 2 T3 6 T4 2
valid_sources[0x2d] 9841 1 T1 26 T3 6 T4 1
valid_sources[0x2e] 9626 1 T3 9 T4 5 T12 6
valid_sources[0x2f] 11688 1 T1 23 T3 3 T4 5
valid_sources[0x30] 9827 1 T1 83 T3 5 T4 6
valid_sources[0x31] 9993 1 T1 17 T3 3 T4 3
valid_sources[0x32] 10227 1 T1 42 T3 2 T4 5
valid_sources[0x33] 10073 1 T1 55 T3 5 T4 2
valid_sources[0x34] 10175 1 T1 118 T3 10 T4 4
valid_sources[0x35] 9792 1 T3 7 T12 5 T13 6
valid_sources[0x36] 9356 1 T1 35 T3 8 T4 4
valid_sources[0x37] 9905 1 T3 3 T4 3 T11 1
valid_sources[0x38] 11063 1 T1 77 T3 7 T4 6
valid_sources[0x39] 10990 1 T1 29 T3 7 T4 3
valid_sources[0x3a] 10318 1 T1 75 T3 3 T4 3
valid_sources[0x3b] 9934 1 T1 36 T3 10 T4 6
valid_sources[0x3c] 35377 1 T1 25 T3 1 T4 8
valid_sources[0x3d] 10101 1 T3 7 T4 2 T12 2
valid_sources[0x3e] 9747 1 T1 14 T3 7 T4 1
valid_sources[0x3f] 17226 1 T3 11 T4 3 T12 3
valid_sources[0x40] 13205 1 T1 164 T3 5 T4 4
valid_sources[0x41] 9966 1 T1 69 T3 3 T4 1
valid_sources[0x42] 9724 1 T3 5 T4 1 T12 3
valid_sources[0x43] 9926 1 T1 39 T3 9 T4 2
valid_sources[0x44] 11174 1 T1 34 T3 6 T4 2
valid_sources[0x45] 12536 1 T1 73 T3 3 T4 2
valid_sources[0x46] 10283 1 T1 42 T3 6 T4 2
valid_sources[0x47] 9608 1 T1 9 T3 4 T4 1
valid_sources[0x48] 9777 1 T1 34 T3 6 T4 2
valid_sources[0x49] 9590 1 T3 3 T4 3 T12 1
valid_sources[0x4a] 13203 1 T1 52 T3 4 T4 4
valid_sources[0x4b] 9831 1 T3 5 T4 6 T12 4
valid_sources[0x4c] 11937 1 T1 33 T3 7 T4 4
valid_sources[0x4d] 9725 1 T1 4 T3 5 T12 9
valid_sources[0x4e] 162917 1 T3 9 T4 4 T12 2
valid_sources[0x4f] 9812 1 T1 48 T3 6 T4 2
valid_sources[0x50] 10098 1 T1 42 T3 2 T4 3
valid_sources[0x51] 9851 1 T1 23 T3 8 T4 2
valid_sources[0x52] 10335 1 T1 46 T3 6 T12 6
valid_sources[0x53] 11248 1 T1 10 T3 5 T4 2
valid_sources[0x54] 11837 1 T3 6 T4 5 T12 5
valid_sources[0x55] 9939 1 T1 21 T3 8 T4 3
valid_sources[0x56] 10025 1 T1 9 T3 10 T4 2
valid_sources[0x57] 10320 1 T1 4 T3 4 T4 6
valid_sources[0x58] 15765 1 T1 31 T3 6 T4 4
valid_sources[0x59] 13601 1 T1 22 T3 10 T4 4
valid_sources[0x5a] 9571 1 T1 64 T3 1 T4 5
valid_sources[0x5b] 13671 1 T1 36 T3 7 T4 2
valid_sources[0x5c] 9734 1 T1 69 T3 8 T4 6
valid_sources[0x5d] 10270 1 T1 13 T3 9 T12 1
valid_sources[0x5e] 10103 1 T1 31 T3 5 T4 6
valid_sources[0x5f] 11088 1 T1 54 T3 8 T4 4
valid_sources[0x60] 10605 1 T3 4 T4 5 T12 5
valid_sources[0x61] 9886 1 T1 56 T3 3 T4 4
valid_sources[0x62] 9785 1 T3 5 T4 4 T12 6
valid_sources[0x63] 10207 1 T3 2 T4 4 T12 4
valid_sources[0x64] 9515 1 T3 6 T4 5 T12 5
valid_sources[0x65] 10149 1 T1 78 T3 3 T4 3
valid_sources[0x66] 10509 1 T1 13 T3 11 T4 1
valid_sources[0x67] 9658 1 T1 112 T3 6 T4 6
valid_sources[0x68] 135227 1 T1 20 T3 4 T4 1
valid_sources[0x69] 9631 1 T1 34 T3 8 T4 2
valid_sources[0x6a] 9488 1 T3 8 T4 5 T12 3
valid_sources[0x6b] 11351 1 T3 7 T4 6 T12 2
valid_sources[0x6c] 196678 1 T1 3 T3 3 T4 2
valid_sources[0x6d] 9627 1 T3 6 T4 2 T13 4
valid_sources[0x6e] 10004 1 T1 10 T3 5 T4 2
valid_sources[0x6f] 9368 1 T3 4 T4 8 T12 1
valid_sources[0x70] 12914 1 T1 6 T3 3 T4 4
valid_sources[0x71] 10096 1 T1 41 T3 4 T4 6
valid_sources[0x72] 9933 1 T1 48 T3 9 T4 6
valid_sources[0x73] 27064 1 T1 22 T3 2 T4 4
valid_sources[0x74] 9849 1 T1 114 T3 1 T4 1
valid_sources[0x75] 9421 1 T1 39 T3 5 T4 3
valid_sources[0x76] 23011 1 T1 6 T3 4 T4 4
valid_sources[0x77] 10062 1 T3 5 T4 6 T12 3
valid_sources[0x78] 10092 1 T3 5 T4 4 T11 1
valid_sources[0x79] 10173 1 T1 45 T3 6 T4 4
valid_sources[0x7a] 9879 1 T1 173 T3 5 T4 4
valid_sources[0x7b] 10028 1 T3 3 T4 6 T12 1
valid_sources[0x7c] 9953 1 T1 22 T3 7 T4 5
valid_sources[0x7d] 10173 1 T1 22 T3 3 T4 7
valid_sources[0x7e] 9545 1 T1 14 T3 11 T4 2
valid_sources[0x7f] 10356 1 T1 8 T3 4 T4 4
valid_sources[0x80] 11433 1 T1 48 T3 5 T4 5



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 2109603 1 T1 3438 T2 2 T3 404
values[0x0] all_enables biggest_size 153564 1 T1 503 T2 6 T3 310
values[0x1] all_enables biggest_size 152195 1 T1 471 T2 6 T3 299

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%