Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1874944	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2104656

1

T1

146

T3

1203

T10

1037

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3623608	1			T1	167		T3	1407		T10	1893
values[0x0]	177451	1			T1	42		T3	293		T10	63
values[0x1]	178541	1			T1	45		T3	283		T10	35

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1489851	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2489749

1

T1

168

T3

1372

T10

1233

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16945	1			T3	7		T10	11		T13	5
valid_sources[0x01]	11625	1			T3	13		T10	7		T13	7
valid_sources[0x02]	12653	1			T3	8		T4	17		T13	5
valid_sources[0x03]	11926	1			T1	2		T3	6		T10	6
valid_sources[0x04]	11645	1			T3	6		T10	12		T13	6
valid_sources[0x05]	11952	1			T1	1		T3	6		T10	2
valid_sources[0x06]	11314	1			T3	14		T10	15		T13	7
valid_sources[0x07]	12037	1			T3	12		T13	8		T14	1
valid_sources[0x08]	11809	1			T1	2		T3	12		T10	8
valid_sources[0x09]	13658	1			T3	7		T10	3		T12	1
valid_sources[0x0a]	20906	1			T1	2		T3	4		T10	4
valid_sources[0x0b]	11475	1			T3	10		T10	10		T13	10
valid_sources[0x0c]	13649	1			T3	10		T10	1		T13	8
valid_sources[0x0d]	18851	1			T3	9		T10	2		T13	3
valid_sources[0x0e]	13014	1			T3	7		T10	7		T13	6
valid_sources[0x0f]	11519	1			T3	13		T10	1		T13	6
valid_sources[0x10]	11906	1			T3	9		T10	6		T13	11
valid_sources[0x11]	13301	1			T1	3		T3	10		T10	10
valid_sources[0x12]	23485	1			T3	5		T10	15		T13	8
valid_sources[0x13]	12173	1			T3	6		T13	2		T15	3
valid_sources[0x14]	11903	1			T3	9		T10	8		T13	8
valid_sources[0x15]	12889	1			T3	11		T10	17		T12	2
valid_sources[0x16]	12018	1			T3	8		T10	2		T13	4
valid_sources[0x17]	11827	1			T3	5		T10	2		T13	7
valid_sources[0x18]	11694	1			T3	4		T10	16		T13	3
valid_sources[0x19]	14737	1			T3	9		T10	2		T12	1
valid_sources[0x1a]	12969	1			T3	7		T13	1		T15	12
valid_sources[0x1b]	11877	1			T3	8		T10	9		T13	4
valid_sources[0x1c]	11977	1			T3	8		T10	3		T13	8
valid_sources[0x1d]	12035	1			T3	5		T10	20		T13	5
valid_sources[0x1e]	11470	1			T3	7		T10	15		T13	6
valid_sources[0x1f]	27756	1			T1	12		T3	6		T10	27
valid_sources[0x20]	11557	1			T3	9		T10	5		T13	3
valid_sources[0x21]	12417	1			T3	13		T10	7		T13	2
valid_sources[0x22]	12466	1			T3	7		T10	4		T13	8
valid_sources[0x23]	31585	1			T1	1		T3	9		T10	1
valid_sources[0x24]	12434	1			T3	7		T10	7		T13	7
valid_sources[0x25]	11673	1			T3	5		T10	3		T13	5
valid_sources[0x26]	12231	1			T3	5		T12	1		T13	5
valid_sources[0x27]	11977	1			T3	6		T10	2		T13	7
valid_sources[0x28]	12829	1			T3	7		T10	1		T13	9
valid_sources[0x29]	15075	1			T3	6		T10	1		T13	6
valid_sources[0x2a]	11615	1			T3	9		T10	7		T13	7
valid_sources[0x2b]	11742	1			T3	8		T10	21		T13	9
valid_sources[0x2c]	11795	1			T1	9		T3	10		T10	2
valid_sources[0x2d]	11942	1			T3	9		T10	9		T13	4
valid_sources[0x2e]	12131	1			T3	11		T10	3		T13	7
valid_sources[0x2f]	12382	1			T3	4		T10	14		T13	7
valid_sources[0x30]	23121	1			T3	14		T10	3		T13	2
valid_sources[0x31]	12338	1			T3	5		T13	6		T15	6
valid_sources[0x32]	12630	1			T1	5		T3	4		T10	8
valid_sources[0x33]	11750	1			T1	1		T3	7		T10	14
valid_sources[0x34]	11536	1			T3	6		T10	23		T13	6
valid_sources[0x35]	12265	1			T3	9		T10	11		T12	2
valid_sources[0x36]	12000	1			T3	4		T10	39		T4	17
valid_sources[0x37]	13856	1			T1	2		T3	9		T10	9
valid_sources[0x38]	16452	1			T3	8		T10	22		T13	1
valid_sources[0x39]	11706	1			T1	1		T3	6		T4	1
valid_sources[0x3a]	12379	1			T1	5		T3	11		T12	1
valid_sources[0x3b]	15507	1			T3	8		T10	10		T12	1
valid_sources[0x3c]	14022	1			T1	1		T3	8		T10	1
valid_sources[0x3d]	13829	1			T3	8		T10	7		T13	8
valid_sources[0x3e]	20156	1			T3	6		T10	7		T4	3
valid_sources[0x3f]	11918	1			T3	7		T10	2		T13	2
valid_sources[0x40]	11387	1			T3	7		T10	4		T13	7
valid_sources[0x41]	13120	1			T3	9		T10	18		T13	7
valid_sources[0x42]	11597	1			T3	6		T10	19		T13	4
valid_sources[0x43]	42227	1			T3	6		T10	2		T13	6
valid_sources[0x44]	11346	1			T3	5		T10	2		T12	1
valid_sources[0x45]	11777	1			T1	4		T3	8		T10	2
valid_sources[0x46]	13599	1			T1	3		T3	10		T10	5
valid_sources[0x47]	10802	1			T3	9		T10	4		T13	9
valid_sources[0x48]	12276	1			T3	5		T10	1		T13	3
valid_sources[0x49]	16729	1			T3	9		T10	8		T13	5
valid_sources[0x4a]	12247	1			T1	2		T3	8		T10	12
valid_sources[0x4b]	11866	1			T3	10		T10	2		T12	1
valid_sources[0x4c]	12072	1			T3	10		T10	7		T13	7
valid_sources[0x4d]	12122	1			T3	8		T10	13		T13	8
valid_sources[0x4e]	11986	1			T3	11		T13	3		T15	7
valid_sources[0x4f]	11568	1			T3	12		T10	18		T13	3
valid_sources[0x50]	11198	1			T3	7		T13	3		T15	6
valid_sources[0x51]	12650	1			T3	8		T13	5		T15	12
valid_sources[0x52]	11877	1			T3	5		T10	3		T13	2
valid_sources[0x53]	11812	1			T1	4		T3	6		T10	30
valid_sources[0x54]	12398	1			T3	4		T10	10		T13	5
valid_sources[0x55]	11948	1			T3	12		T10	5		T4	1
valid_sources[0x56]	41069	1			T3	8		T10	4		T13	7
valid_sources[0x57]	12905	1			T3	8		T13	3		T15	7
valid_sources[0x58]	11369	1			T3	9		T13	5		T14	1
valid_sources[0x59]	14104	1			T3	9		T10	14		T13	3
valid_sources[0x5a]	13165	1			T3	6		T10	2		T13	8
valid_sources[0x5b]	11562	1			T3	5		T12	1		T13	5
valid_sources[0x5c]	11692	1			T3	10		T10	10		T13	2
valid_sources[0x5d]	12549	1			T1	1		T3	11		T10	2
valid_sources[0x5e]	50735	1			T3	7		T10	25		T13	6
valid_sources[0x5f]	11241	1			T3	10		T13	7		T15	7
valid_sources[0x60]	11603	1			T3	15		T10	6		T13	4
valid_sources[0x61]	14528	1			T3	12		T10	3		T13	4
valid_sources[0x62]	11915	1			T3	10		T10	17		T13	7
valid_sources[0x63]	98677	1			T1	5		T3	7		T10	10
valid_sources[0x64]	11278	1			T1	1		T3	6		T10	2
valid_sources[0x65]	57875	1			T3	5		T10	4		T13	2
valid_sources[0x66]	11209	1			T3	5		T13	6		T14	1
valid_sources[0x67]	165217	1			T3	6		T10	12		T13	5
valid_sources[0x68]	11561	1			T3	8		T10	10		T12	2
valid_sources[0x69]	13237	1			T1	3		T3	8		T10	6
valid_sources[0x6a]	38814	1			T3	5		T10	3		T4	27366
valid_sources[0x6b]	11784	1			T3	6		T13	4		T15	10
valid_sources[0x6c]	14603	1			T3	9		T10	27		T13	1
valid_sources[0x6d]	11404	1			T1	1		T3	5		T10	7
valid_sources[0x6e]	11769	1			T3	7		T10	15		T12	1
valid_sources[0x6f]	13884	1			T3	3		T10	3		T13	5
valid_sources[0x70]	11798	1			T3	7		T10	7		T13	5
valid_sources[0x71]	11602	1			T3	9		T10	1		T4	17
valid_sources[0x72]	11629	1			T3	10		T10	14		T13	5
valid_sources[0x73]	11256	1			T3	8		T10	3		T13	9
valid_sources[0x74]	13387	1			T1	11		T3	9		T13	1
valid_sources[0x75]	11135	1			T3	13		T10	4		T13	4
valid_sources[0x76]	13847	1			T1	4		T3	13		T10	23
valid_sources[0x77]	11605	1			T3	7		T10	13		T4	17
valid_sources[0x78]	17436	1			T1	5		T3	3		T10	14
valid_sources[0x79]	11795	1			T1	7		T3	6		T10	4
valid_sources[0x7a]	14822	1			T3	6		T13	10		T15	8
valid_sources[0x7b]	15701	1			T3	9		T10	14		T13	3
valid_sources[0x7c]	13426	1			T3	12		T10	3		T13	4
valid_sources[0x7d]	13292	1			T1	9		T3	10		T13	7
valid_sources[0x7e]	95416	1			T1	8		T3	6		T10	2
valid_sources[0x7f]	11577	1			T3	5		T10	5		T12	4
valid_sources[0x80]	22071	1			T1	1		T3	4		T10	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1797714

1

T1

73

T3

696

T10

951

values[0x0]

all_enables

biggest_size

153920

1

T1

35

T3

258

T10

55

values[0x1]

all_enables

biggest_size

153022

1

T1

38

T3

249

T10

31