Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	113512018	15779	0	0
claim_transition_if_regwen_rd_A	113512018	1039	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113512018	15779	0	0
T4	160526	8	0	0
T5	77021	0	0	0
T13	35419	0	0	0
T14	10801	0	0	0
T15	47729	0	0	0
T16	17505	0	0	0
T17	67494	0	0	0
T18	120860	0	0	0
T22	1331	0	0	0
T41	0	6	0	0
T46	0	2	0	0
T52	0	3	0	0
T54	0	5	0	0
T72	0	11	0	0
T79	15322	0	0	0
T148	0	1	0	0
T149	0	7	0	0
T150	0	2	0	0
T151	0	1	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113512018	1039	0	0
T89	270581	0	0	0
T116	0	63	0	0
T128	0	58	0	0
T130	0	2	0	0
T135	0	11	0	0
T145	0	7	0	0
T152	139203	3	0	0
T153	0	2	0	0
T154	0	2	0	0
T155	0	69	0	0
T156	0	76	0	0
T157	27710	0	0	0
T158	3538	0	0	0
T159	184757	0	0	0
T160	27464	0	0	0
T161	4482	0	0	0
T162	28675	0	0	0
T163	24968	0	0	0
T164	45623	0	0	0