Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1684499	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1919460

1

T1

1009

T2

52

T3

692

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3237155	1			T1	673		T2	73		T3	456
values[0x0]	183411	1			T1	398		T2	32		T3	289
values[0x1]	183393	1			T1	386		T2	39		T3	279

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1337438	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2266521

1

T1

1112

T2

68

T3

780

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12445	1			T3	1024		T10	1		T4	7
valid_sources[0x01]	12648	1			T10	4		T4	5		T5	50
valid_sources[0x02]	10512	1			T4	2		T5	91		T11	3
valid_sources[0x03]	10957	1			T10	1		T4	4		T5	146
valid_sources[0x04]	14143	1			T2	1		T4	6		T5	88
valid_sources[0x05]	11019	1			T2	1		T10	1		T4	5
valid_sources[0x06]	10553	1			T4	7		T5	83		T13	7
valid_sources[0x07]	10416	1			T2	1		T4	2		T5	26
valid_sources[0x08]	15734	1			T10	2		T4	5		T5	42
valid_sources[0x09]	14260	1			T10	1		T4	8		T5	57
valid_sources[0x0a]	10532	1			T4	2		T5	76		T11	27
valid_sources[0x0b]	10756	1			T2	1		T4	4		T5	41
valid_sources[0x0c]	11602	1			T2	1		T4	5		T5	77
valid_sources[0x0d]	11148	1			T4	6		T5	69		T11	20
valid_sources[0x0e]	23673	1			T2	3		T4	6		T5	81
valid_sources[0x0f]	10974	1			T4	2		T5	88		T11	8
valid_sources[0x10]	12157	1			T10	1		T4	5		T5	101
valid_sources[0x11]	12334	1			T4	4		T5	50		T11	7
valid_sources[0x12]	14152	1			T4	4		T5	62		T11	14
valid_sources[0x13]	10648	1			T2	1		T4	8		T5	68
valid_sources[0x14]	16820	1			T10	1		T4	5		T5	105
valid_sources[0x15]	10647	1			T2	1		T4	4		T5	33
valid_sources[0x16]	11098	1			T4	5		T5	123		T11	4
valid_sources[0x17]	11650	1			T4	3		T5	63		T11	25
valid_sources[0x18]	13408	1			T4	4		T5	75		T11	14
valid_sources[0x19]	13247	1			T4	5		T5	72		T11	3
valid_sources[0x1a]	30523	1			T2	1		T4	2		T5	97
valid_sources[0x1b]	19015	1			T2	2		T10	1		T4	3
valid_sources[0x1c]	21356	1			T10	2		T4	4		T5	113
valid_sources[0x1d]	10957	1			T4	1		T5	88		T11	7
valid_sources[0x1e]	10529	1			T4	5		T5	114		T11	6
valid_sources[0x1f]	10714	1			T10	3		T4	4		T5	48
valid_sources[0x20]	11082	1			T2	1		T4	1		T5	67
valid_sources[0x21]	12391	1			T2	2		T4	6		T5	71
valid_sources[0x22]	10706	1			T4	3		T5	31		T11	8
valid_sources[0x23]	13023	1			T4	6		T5	89		T11	3
valid_sources[0x24]	15490	1			T2	1		T10	1		T4	9
valid_sources[0x25]	11007	1			T10	1		T4	9		T5	81
valid_sources[0x26]	10938	1			T4	6		T5	74		T11	5
valid_sources[0x27]	10826	1			T4	10		T5	104		T11	2
valid_sources[0x28]	11203	1			T4	8		T5	102		T11	6
valid_sources[0x29]	12176	1			T2	2		T4	2		T5	27
valid_sources[0x2a]	10863	1			T10	1		T4	7		T5	77
valid_sources[0x2b]	10853	1			T10	1		T4	6		T5	57
valid_sources[0x2c]	10722	1			T4	5		T5	78		T11	20
valid_sources[0x2d]	10807	1			T2	1		T4	5		T5	86
valid_sources[0x2e]	67090	1			T2	1		T4	4		T5	75
valid_sources[0x2f]	11154	1			T4	2		T5	66		T11	17
valid_sources[0x30]	11143	1			T10	4		T4	2		T5	54
valid_sources[0x31]	11038	1			T10	2		T4	6		T5	85
valid_sources[0x32]	10852	1			T10	1		T4	4		T5	17
valid_sources[0x33]	10958	1			T2	1		T4	2		T5	23
valid_sources[0x34]	11096	1			T10	2		T4	4		T5	50
valid_sources[0x35]	12101	1			T2	1		T10	1		T4	2
valid_sources[0x36]	11296	1			T2	2		T4	6		T5	21
valid_sources[0x37]	11210	1			T2	1		T10	1		T4	1
valid_sources[0x38]	11002	1			T2	1		T4	6		T5	172
valid_sources[0x39]	10889	1			T4	2		T5	112		T11	4
valid_sources[0x3a]	11070	1			T4	5		T5	37		T11	8
valid_sources[0x3b]	10770	1			T4	7		T5	96		T11	4
valid_sources[0x3c]	10783	1			T2	2		T10	1		T4	7
valid_sources[0x3d]	11450	1			T4	6		T5	171		T11	4
valid_sources[0x3e]	56896	1			T4	3		T5	63		T11	6
valid_sources[0x3f]	10472	1			T2	2		T4	9		T5	69
valid_sources[0x40]	10847	1			T10	1		T4	2		T5	71
valid_sources[0x41]	13440	1			T4	5		T5	91		T11	2
valid_sources[0x42]	10816	1			T2	4		T4	4		T5	80
valid_sources[0x43]	11745	1			T4	7		T5	90		T11	15
valid_sources[0x44]	10607	1			T4	2		T5	43		T11	15
valid_sources[0x45]	12036	1			T10	1		T4	2		T5	53
valid_sources[0x46]	10818	1			T10	3		T4	4		T5	59
valid_sources[0x47]	10592	1			T10	2		T4	5		T5	96
valid_sources[0x48]	10757	1			T4	7		T5	65		T11	2
valid_sources[0x49]	19166	1			T4	3		T5	75		T11	4
valid_sources[0x4a]	11743	1			T2	4		T10	1		T4	6
valid_sources[0x4b]	12196	1			T10	1		T4	2		T5	64
valid_sources[0x4c]	11014	1			T4	5		T5	45		T11	9
valid_sources[0x4d]	10842	1			T4	5		T5	28		T11	21
valid_sources[0x4e]	10514	1			T2	1		T4	4		T5	120
valid_sources[0x4f]	24021	1			T4	4		T5	69		T11	12
valid_sources[0x50]	12680	1			T4	3		T5	58		T11	3
valid_sources[0x51]	10623	1			T2	1		T4	7		T5	24
valid_sources[0x52]	11342	1			T10	1		T4	3		T5	128
valid_sources[0x53]	16214	1			T10	1		T4	3		T5	104
valid_sources[0x54]	11983	1			T4	5		T5	73		T11	14
valid_sources[0x55]	11159	1			T4	4		T5	93		T11	2
valid_sources[0x56]	10881	1			T10	3		T4	5		T5	165
valid_sources[0x57]	11243	1			T4	1		T5	155		T11	14
valid_sources[0x58]	12311	1			T4	4		T5	64		T14	17
valid_sources[0x59]	15158	1			T4	7		T5	50		T11	7
valid_sources[0x5a]	10670	1			T2	1		T4	5		T5	116
valid_sources[0x5b]	17767	1			T2	1		T4	6		T5	65
valid_sources[0x5c]	11025	1			T4	4		T5	43		T11	5
valid_sources[0x5d]	109453	1			T2	2		T4	7		T5	48
valid_sources[0x5e]	12577	1			T4	2		T5	91		T11	14
valid_sources[0x5f]	10689	1			T2	1		T4	4		T5	87
valid_sources[0x60]	11504	1			T10	1		T4	5		T5	20
valid_sources[0x61]	10703	1			T10	2		T4	4		T5	59
valid_sources[0x62]	27739	1			T4	1		T5	76		T11	9
valid_sources[0x63]	64057	1			T2	3		T4	6		T5	64
valid_sources[0x64]	10877	1			T4	2		T5	45		T11	15
valid_sources[0x65]	10922	1			T10	1		T4	6		T5	49
valid_sources[0x66]	12500	1			T1	1457		T2	1		T4	8
valid_sources[0x67]	11084	1			T2	1		T4	5		T5	58
valid_sources[0x68]	10824	1			T10	2		T4	4		T5	43
valid_sources[0x69]	11082	1			T2	2		T10	1		T4	6
valid_sources[0x6a]	10766	1			T4	5		T5	21		T11	2
valid_sources[0x6b]	10651	1			T10	2		T5	111		T11	10
valid_sources[0x6c]	24758	1			T2	1		T10	1		T4	2
valid_sources[0x6d]	12093	1			T4	6		T5	117		T11	9
valid_sources[0x6e]	10565	1			T4	5		T5	47		T11	1
valid_sources[0x6f]	10893	1			T4	4		T5	51		T11	3
valid_sources[0x70]	11003	1			T2	4		T10	3		T4	2
valid_sources[0x71]	11107	1			T2	1		T4	10		T5	50
valid_sources[0x72]	11942	1			T4	11		T5	70		T11	4
valid_sources[0x73]	11937	1			T2	3		T4	2		T5	93
valid_sources[0x74]	25220	1			T4	11		T5	71		T11	5
valid_sources[0x75]	10595	1			T2	4		T4	4		T5	69
valid_sources[0x76]	12157	1			T2	1		T4	5		T5	57
valid_sources[0x77]	11914	1			T4	4		T5	129		T11	10
valid_sources[0x78]	12601	1			T10	1		T4	3		T5	59
valid_sources[0x79]	10638	1			T10	1		T4	2		T5	76
valid_sources[0x7a]	10205	1			T4	3		T5	28		T11	3
valid_sources[0x7b]	10932	1			T10	2		T4	1		T5	61
valid_sources[0x7c]	11590	1			T4	5		T5	136		T11	15
valid_sources[0x7d]	11541	1			T4	3		T5	90		T11	7
valid_sources[0x7e]	11133	1			T4	5		T5	85		T11	1
valid_sources[0x7f]	10909	1			T4	3		T5	80		T11	4
valid_sources[0x80]	11032	1			T4	5		T5	120		T11	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1602624

1

T1

312

T2

29

T3

200

values[0x0]

all_enables

biggest_size

159234

1

T1

360

T2

14

T3

255

values[0x1]

all_enables

biggest_size

157602

1

T1

337

T2

9

T3

237