Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	117710786	14565	0	0
claim_transition_if_regwen_rd_A	117710786	1352	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117710786	14565	0	0
T5	206931	4	0	0
T6	86550	0	0	0
T11	43519	0	0	0
T12	1488	0	0	0
T13	34193	0	0	0
T14	255892	5	0	0
T15	37993	0	0	0
T16	64328	0	0	0
T20	0	1	0	0
T37	29282	0	0	0
T40	0	7	0	0
T52	0	9	0	0
T53	7238	0	0	0
T129	0	19	0	0
T130	0	2	0	0
T131	0	3	0	0
T132	0	5	0	0
T133	0	1	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117710786	1352	0	0
T20	117308	1	0	0
T33	120077	0	0	0
T40	112749	0	0	0
T45	30587	0	0	0
T55	1695	0	0	0
T130	0	5	0	0
T133	0	4	0	0
T134	0	1	0	0
T135	0	13	0	0
T136	0	7	0	0
T137	0	4	0	0
T138	0	78	0	0
T139	0	35	0	0
T140	0	1	0	0
T141	30639	0	0	0
T142	196814	0	0	0
T143	2106	0	0	0
T144	7749	0	0	0
T145	39488	0	0	0