Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2099662	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2330517

1

T1

21

T2

8970

T4

67

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4065234	1			T2	17640		T4	96		T5	62
values[0x0]	182107	1			T1	33		T2	84		T4	12
values[0x1]	182838	1			T1	23		T2	81		T4	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1670337	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2759842

1

T1

26

T2

10776

T4

73

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13187	1			T1	1		T2	77		T9	6
valid_sources[0x01]	12431	1			T2	58		T5	1		T9	4
valid_sources[0x02]	16280	1			T2	56		T4	1		T9	2
valid_sources[0x03]	13520	1			T2	68		T9	7		T10	6
valid_sources[0x04]	12880	1			T1	2		T2	69		T10	6
valid_sources[0x05]	12580	1			T1	1		T2	67		T10	3
valid_sources[0x06]	12532	1			T2	67		T8	1		T10	3
valid_sources[0x07]	13326	1			T2	71		T8	3		T10	5
valid_sources[0x08]	12772	1			T2	56		T5	1		T9	4
valid_sources[0x09]	12833	1			T1	1		T2	55		T5	1
valid_sources[0x0a]	12844	1			T2	55		T8	2		T9	3
valid_sources[0x0b]	13170	1			T2	55		T4	1		T9	4
valid_sources[0x0c]	13253	1			T2	86		T4	1		T9	7
valid_sources[0x0d]	77522	1			T2	88		T5	3		T10	7
valid_sources[0x0e]	12731	1			T2	68		T8	1		T9	3
valid_sources[0x0f]	13444	1			T2	78		T5	1		T8	4
valid_sources[0x10]	13115	1			T2	68		T9	5		T10	5
valid_sources[0x11]	12494	1			T2	73		T8	3		T9	3
valid_sources[0x12]	18770	1			T2	67		T8	7		T9	3
valid_sources[0x13]	12851	1			T2	70		T4	1		T8	1
valid_sources[0x14]	12695	1			T1	1		T2	55		T9	3
valid_sources[0x15]	12941	1			T2	77		T9	3		T10	10
valid_sources[0x16]	12641	1			T2	70		T4	2		T9	1
valid_sources[0x17]	12658	1			T2	86		T9	5		T10	9
valid_sources[0x18]	13532	1			T1	1		T2	53		T9	5
valid_sources[0x19]	23267	1			T1	5		T2	51		T4	1
valid_sources[0x1a]	12594	1			T2	70		T9	1		T10	8
valid_sources[0x1b]	12639	1			T2	71		T4	2		T9	1
valid_sources[0x1c]	12596	1			T2	83		T8	15		T9	3
valid_sources[0x1d]	12329	1			T2	75		T8	10		T9	1
valid_sources[0x1e]	13658	1			T1	1		T2	76		T4	4
valid_sources[0x1f]	13158	1			T2	79		T5	1		T9	5
valid_sources[0x20]	12815	1			T2	74		T4	1		T8	2
valid_sources[0x21]	12971	1			T2	57		T4	1		T5	2
valid_sources[0x22]	16119	1			T2	88		T5	1		T9	5
valid_sources[0x23]	15849	1			T2	78		T9	3		T10	5
valid_sources[0x24]	12678	1			T2	63		T4	1		T8	4
valid_sources[0x25]	13310	1			T1	1		T2	62		T5	1
valid_sources[0x26]	12915	1			T2	69		T8	5		T9	4
valid_sources[0x27]	12912	1			T1	1		T2	49		T4	1
valid_sources[0x28]	12754	1			T2	78		T4	2		T9	2
valid_sources[0x29]	18050	1			T2	89		T5	1		T10	4
valid_sources[0x2a]	14406	1			T2	52		T9	4		T10	4
valid_sources[0x2b]	24561	1			T2	72		T5	2		T8	16
valid_sources[0x2c]	13878	1			T2	69		T9	6		T10	8
valid_sources[0x2d]	11870	1			T2	49		T8	3		T9	3
valid_sources[0x2e]	12643	1			T2	77		T5	3		T8	1
valid_sources[0x2f]	18689	1			T2	64		T4	1		T5	1
valid_sources[0x30]	12978	1			T1	1		T2	66		T9	3
valid_sources[0x31]	14603	1			T2	69		T5	1		T8	2
valid_sources[0x32]	48034	1			T2	73		T9	1		T10	4
valid_sources[0x33]	12488	1			T2	67		T8	2		T9	5
valid_sources[0x34]	12810	1			T2	62		T4	1		T8	3
valid_sources[0x35]	16158	1			T1	2		T2	67		T9	5
valid_sources[0x36]	13371	1			T2	84		T4	1		T5	2
valid_sources[0x37]	12410	1			T2	68		T4	1		T8	5
valid_sources[0x38]	77446	1			T2	78		T9	3		T10	6
valid_sources[0x39]	12862	1			T2	71		T5	1		T9	3
valid_sources[0x3a]	12704	1			T2	71		T4	2		T5	1
valid_sources[0x3b]	12748	1			T2	84		T4	1		T9	1
valid_sources[0x3c]	12810	1			T2	60		T4	4		T5	1
valid_sources[0x3d]	38336	1			T1	1		T2	85		T8	3
valid_sources[0x3e]	16213	1			T2	61		T8	6		T9	1
valid_sources[0x3f]	27779	1			T2	70		T5	2		T9	1
valid_sources[0x40]	12231	1			T2	76		T4	2		T8	3
valid_sources[0x41]	13664	1			T2	71		T4	1		T8	1
valid_sources[0x42]	13135	1			T2	67		T9	1		T10	6
valid_sources[0x43]	12901	1			T2	67		T4	3		T5	1
valid_sources[0x44]	13149	1			T2	75		T10	5		T11	1
valid_sources[0x45]	14688	1			T2	74		T4	4		T5	1
valid_sources[0x46]	16206	1			T2	47		T9	3		T10	6
valid_sources[0x47]	13895	1			T1	2		T2	76		T8	10
valid_sources[0x48]	13770	1			T2	87		T9	7		T10	2
valid_sources[0x49]	12427	1			T2	65		T4	1		T8	2
valid_sources[0x4a]	12900	1			T2	90		T5	1		T9	5
valid_sources[0x4b]	14732	1			T2	70		T9	6		T10	7
valid_sources[0x4c]	13144	1			T2	54		T5	1		T9	2
valid_sources[0x4d]	13835	1			T2	49		T4	1		T8	4
valid_sources[0x4e]	38303	1			T2	55		T10	9		T11	1
valid_sources[0x4f]	14503	1			T2	81		T4	1		T9	3
valid_sources[0x50]	14089	1			T2	65		T9	1		T10	11
valid_sources[0x51]	64612	1			T2	62		T9	6		T10	8
valid_sources[0x52]	13000	1			T1	3		T2	57		T4	2
valid_sources[0x53]	13983	1			T2	83		T8	2		T9	1
valid_sources[0x54]	13138	1			T2	60		T5	3		T8	10
valid_sources[0x55]	12629	1			T2	87		T9	2		T10	5
valid_sources[0x56]	14560	1			T1	1		T2	83		T5	2
valid_sources[0x57]	32106	1			T2	64		T8	2		T9	3
valid_sources[0x58]	14885	1			T2	76		T4	1		T8	5
valid_sources[0x59]	16810	1			T2	59		T4	1		T5	1
valid_sources[0x5a]	12996	1			T1	1		T2	67		T4	2
valid_sources[0x5b]	12789	1			T2	88		T9	4		T10	6
valid_sources[0x5c]	12617	1			T2	75		T9	3		T10	2
valid_sources[0x5d]	12488	1			T2	59		T9	5		T10	2
valid_sources[0x5e]	12814	1			T2	81		T4	1		T5	1
valid_sources[0x5f]	25711	1			T2	67		T4	2		T5	4
valid_sources[0x60]	12629	1			T2	73		T8	8		T9	1
valid_sources[0x61]	13794	1			T2	100		T4	4		T9	7
valid_sources[0x62]	12469	1			T2	51		T5	1		T9	3
valid_sources[0x63]	16800	1			T2	66		T9	2		T10	6
valid_sources[0x64]	12779	1			T2	74		T9	1		T10	6
valid_sources[0x65]	12473	1			T2	73		T9	2		T10	7
valid_sources[0x66]	12267	1			T1	1		T2	62		T4	1
valid_sources[0x67]	12145	1			T2	66		T8	2		T9	2
valid_sources[0x68]	13159	1			T2	76		T9	2		T10	6
valid_sources[0x69]	15190	1			T2	63		T9	5		T10	8
valid_sources[0x6a]	16126	1			T2	65		T8	1		T10	6
valid_sources[0x6b]	12908	1			T1	1		T2	65		T9	2
valid_sources[0x6c]	13267	1			T2	65		T5	1		T10	5
valid_sources[0x6d]	12373	1			T2	62		T5	3		T9	3
valid_sources[0x6e]	12784	1			T2	79		T4	1		T9	1
valid_sources[0x6f]	14415	1			T2	72		T5	1		T8	3
valid_sources[0x70]	12462	1			T2	85		T4	2		T9	1
valid_sources[0x71]	14497	1			T2	59		T8	5		T9	4
valid_sources[0x72]	12373	1			T2	65		T9	4		T10	5
valid_sources[0x73]	15004	1			T2	77		T4	1		T8	9
valid_sources[0x74]	12559	1			T2	64		T8	1		T9	7
valid_sources[0x75]	13160	1			T2	60		T5	1		T10	7
valid_sources[0x76]	14755	1			T2	84		T9	10		T10	2
valid_sources[0x77]	12533	1			T2	86		T8	5		T9	5
valid_sources[0x78]	63863	1			T2	82		T5	1		T8	1
valid_sources[0x79]	12700	1			T2	88		T4	1		T8	3
valid_sources[0x7a]	12879	1			T2	62		T4	1		T10	6
valid_sources[0x7b]	13650	1			T2	75		T5	1		T9	1
valid_sources[0x7c]	12726	1			T1	1		T2	60		T8	9
valid_sources[0x7d]	12701	1			T2	79		T8	1		T9	2
valid_sources[0x7e]	13650	1			T2	76		T4	2		T9	5
valid_sources[0x7f]	12510	1			T2	91		T9	1		T10	3
valid_sources[0x80]	12737	1			T1	2		T2	72		T5	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2015826

1

T2

8828

T4

46

T5

26

values[0x0]

all_enables

biggest_size

157846

1

T1

16

T2

72

T4

12

values[0x1]

all_enables

biggest_size

156845

1

T1

5

T2

70

T4

9