Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	117237315	12673	0	0
claim_transition_if_regwen_rd_A	117237315	1502	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117237315	12673	0	0
T45	0	4	0	0
T53	45379	0	0	0
T55	22023	0	0	0
T86	149961	9	0	0
T87	0	3	0	0
T104	0	5	0	0
T152	0	3	0	0
T153	0	5	0	0
T154	0	11	0	0
T155	0	16	0	0
T156	0	10	0	0
T157	0	23	0	0
T158	1074	0	0	0
T159	8162	0	0	0
T160	42240	0	0	0
T161	18954	0	0	0
T162	2031	0	0	0
T163	11160	0	0	0
T164	1081	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117237315	1502	0	0
T22	81172	0	0	0
T57	10457	0	0	0
T68	3105	0	0	0
T78	82086	0	0	0
T89	642851	2	0	0
T96	83912	0	0	0
T97	45307	0	0	0
T98	56961	0	0	0
T99	1413	0	0	0
T106	0	2	0	0
T107	0	9	0	0
T115	0	46	0	0
T121	0	17	0	0
T165	0	6	0	0
T166	0	16	0	0
T167	0	230	0	0
T168	0	2	0	0
T169	0	1	0	0
T170	1350	0	0	0