Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2126804	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2356342

1

T1

1577

T2

118

T10

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4121991	1			T1	2031		T2	94		T10	11
values[0x0]	179843	1			T1	342		T2	56		T10	8
values[0x1]	181312	1			T1	346		T2	40		T10	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1690250	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2792896

1

T1

1808

T2

132

T10

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12446	1			T2	5		T5	123		T15	3
valid_sources[0x01]	14179	1			T5	141		T15	12		T45	15
valid_sources[0x02]	13882	1			T5	146		T15	3		T106	1
valid_sources[0x03]	12327	1			T5	133		T15	4		T45	10
valid_sources[0x04]	13637	1			T5	132		T15	2		T45	8
valid_sources[0x05]	12519	1			T5	122		T15	4		T45	13
valid_sources[0x06]	14341	1			T5	163		T15	7		T45	13
valid_sources[0x07]	12348	1			T5	138		T15	9		T45	5
valid_sources[0x08]	12908	1			T2	6		T5	142		T15	1
valid_sources[0x09]	12080	1			T5	122		T15	3		T45	14
valid_sources[0x0a]	13882	1			T5	152		T15	5		T45	13
valid_sources[0x0b]	12723	1			T2	1		T5	149		T15	5
valid_sources[0x0c]	12350	1			T5	141		T15	7		T45	1
valid_sources[0x0d]	90405	1			T2	5		T5	151		T25	1
valid_sources[0x0e]	12762	1			T5	158		T15	3		T45	6
valid_sources[0x0f]	11734	1			T2	1		T5	140		T15	8
valid_sources[0x10]	12116	1			T5	147		T15	1		T45	14
valid_sources[0x11]	12321	1			T5	150		T15	4		T45	7
valid_sources[0x12]	13009	1			T2	3		T5	137		T15	2
valid_sources[0x13]	14626	1			T5	141		T15	6		T45	1
valid_sources[0x14]	12785	1			T5	136		T15	2		T47	7
valid_sources[0x15]	12303	1			T5	135		T25	1		T15	4
valid_sources[0x16]	14985	1			T2	2		T5	127		T15	4
valid_sources[0x17]	13560	1			T2	6		T5	158		T15	4
valid_sources[0x18]	12294	1			T5	152		T15	6		T17	64
valid_sources[0x19]	12340	1			T5	152		T15	1		T45	7
valid_sources[0x1a]	17455	1			T5	127		T15	3		T45	15
valid_sources[0x1b]	11922	1			T5	152		T15	4		T45	2
valid_sources[0x1c]	12671	1			T5	139		T15	5		T45	5
valid_sources[0x1d]	11882	1			T5	120		T15	4		T45	13
valid_sources[0x1e]	12101	1			T5	136		T15	8		T45	2
valid_sources[0x1f]	12834	1			T5	133		T15	8		T45	21
valid_sources[0x20]	12686	1			T5	122		T15	3		T45	2
valid_sources[0x21]	12782	1			T2	2		T5	138		T15	7
valid_sources[0x22]	12478	1			T5	134		T15	7		T17	1
valid_sources[0x23]	13425	1			T5	124		T15	8		T45	9
valid_sources[0x24]	12386	1			T5	112		T15	11		T45	4
valid_sources[0x25]	12354	1			T2	1		T5	140		T15	5
valid_sources[0x26]	13835	1			T5	119		T15	3		T45	6
valid_sources[0x27]	12405	1			T5	142		T15	6		T45	6
valid_sources[0x28]	11961	1			T5	130		T15	3		T45	9
valid_sources[0x29]	12127	1			T2	3		T5	137		T15	3
valid_sources[0x2a]	12197	1			T5	142		T15	4		T45	2
valid_sources[0x2b]	13373	1			T5	159		T15	7		T45	2
valid_sources[0x2c]	12454	1			T5	146		T15	7		T45	9
valid_sources[0x2d]	11773	1			T5	147		T15	2		T45	1
valid_sources[0x2e]	12276	1			T5	122		T15	2		T45	2
valid_sources[0x2f]	14885	1			T1	2719		T5	158		T15	5
valid_sources[0x30]	12771	1			T5	148		T15	3		T45	18
valid_sources[0x31]	12483	1			T2	1		T5	157		T15	3
valid_sources[0x32]	12473	1			T5	131		T15	5		T45	6
valid_sources[0x33]	73957	1			T14	3		T5	121		T15	7
valid_sources[0x34]	12416	1			T5	142		T15	6		T106	4
valid_sources[0x35]	38117	1			T5	129		T25	1		T15	3
valid_sources[0x36]	12211	1			T5	139		T25	1		T15	2
valid_sources[0x37]	12246	1			T5	115		T15	4		T106	1
valid_sources[0x38]	14173	1			T5	132		T15	2		T17	77
valid_sources[0x39]	18923	1			T5	129		T25	1		T15	2
valid_sources[0x3a]	50275	1			T2	1		T5	137		T15	3
valid_sources[0x3b]	13796	1			T5	160		T15	3		T45	1
valid_sources[0x3c]	12227	1			T2	2		T5	132		T15	3
valid_sources[0x3d]	12104	1			T5	126		T17	49		T45	1
valid_sources[0x3e]	12122	1			T5	140		T15	6		T45	6
valid_sources[0x3f]	89223	1			T5	147		T15	4		T17	29
valid_sources[0x40]	12491	1			T2	1		T5	130		T45	13
valid_sources[0x41]	115460	1			T5	122		T15	1		T45	12
valid_sources[0x42]	12610	1			T5	123		T15	3		T45	2
valid_sources[0x43]	12595	1			T5	124		T15	6		T45	4
valid_sources[0x44]	12070	1			T5	119		T15	4		T45	2
valid_sources[0x45]	12660	1			T5	137		T15	7		T45	11
valid_sources[0x46]	34849	1			T5	146		T15	7		T45	1
valid_sources[0x47]	25620	1			T2	1		T5	143		T15	3
valid_sources[0x48]	24666	1			T5	136		T15	5		T45	4
valid_sources[0x49]	58559	1			T5	149		T15	2		T45	10
valid_sources[0x4a]	12431	1			T2	1		T5	150		T15	4
valid_sources[0x4b]	12105	1			T5	136		T15	5		T45	16
valid_sources[0x4c]	31041	1			T2	2		T5	141		T15	4
valid_sources[0x4d]	12908	1			T2	2		T5	128		T15	3
valid_sources[0x4e]	103898	1			T5	138		T15	6		T45	7
valid_sources[0x4f]	31267	1			T5	136		T15	7		T45	6
valid_sources[0x50]	12324	1			T2	2		T5	141		T15	4
valid_sources[0x51]	21677	1			T5	146		T15	7		T45	6
valid_sources[0x52]	12460	1			T10	1		T5	116		T15	2
valid_sources[0x53]	12245	1			T5	145		T15	6		T45	5
valid_sources[0x54]	12005	1			T5	121		T15	4		T106	8
valid_sources[0x55]	12052	1			T5	132		T15	5		T45	6
valid_sources[0x56]	12194	1			T5	140		T15	4		T106	10
valid_sources[0x57]	13874	1			T5	130		T15	4		T45	5
valid_sources[0x58]	12064	1			T5	121		T15	5		T45	2
valid_sources[0x59]	12494	1			T5	145		T15	7		T106	1
valid_sources[0x5a]	13779	1			T5	147		T15	6		T45	12
valid_sources[0x5b]	11950	1			T5	149		T15	4		T45	9
valid_sources[0x5c]	12522	1			T5	109		T25	2		T15	4
valid_sources[0x5d]	15367	1			T2	2		T5	140		T15	4
valid_sources[0x5e]	12688	1			T5	131		T15	7		T45	14
valid_sources[0x5f]	12753	1			T2	3		T5	144		T25	1
valid_sources[0x60]	12696	1			T10	5		T5	107		T15	4
valid_sources[0x61]	61537	1			T5	105		T15	6		T45	4
valid_sources[0x62]	12660	1			T5	124		T15	3		T106	13
valid_sources[0x63]	15497	1			T2	6		T5	130		T15	5
valid_sources[0x64]	41183	1			T5	125		T15	4		T44	801
valid_sources[0x65]	12918	1			T5	151		T15	5		T45	10
valid_sources[0x66]	12502	1			T5	134		T15	9		T45	7
valid_sources[0x67]	12332	1			T2	2		T5	135		T15	6
valid_sources[0x68]	13226	1			T5	128		T15	5		T45	2
valid_sources[0x69]	12760	1			T5	142		T15	4		T45	17
valid_sources[0x6a]	12409	1			T2	12		T5	138		T15	5
valid_sources[0x6b]	12490	1			T5	153		T25	1		T15	3
valid_sources[0x6c]	12495	1			T5	129		T15	2		T45	1
valid_sources[0x6d]	13205	1			T5	108		T15	5		T45	5
valid_sources[0x6e]	12013	1			T5	125		T15	5		T45	16
valid_sources[0x6f]	19028	1			T2	1		T5	122		T25	1
valid_sources[0x70]	14593	1			T5	159		T45	1		T106	1
valid_sources[0x71]	12493	1			T5	147		T15	6		T45	4
valid_sources[0x72]	12456	1			T5	131		T15	4		T45	10
valid_sources[0x73]	12809	1			T2	1		T5	142		T15	4
valid_sources[0x74]	12681	1			T5	140		T15	12		T45	13
valid_sources[0x75]	13410	1			T5	160		T15	1		T45	3
valid_sources[0x76]	12268	1			T5	147		T15	6		T45	1
valid_sources[0x77]	12184	1			T5	136		T25	1		T15	12
valid_sources[0x78]	78521	1			T5	116		T15	4		T45	5
valid_sources[0x79]	11774	1			T2	7		T5	129		T15	3
valid_sources[0x7a]	12286	1			T5	125		T15	7		T17	29
valid_sources[0x7b]	13380	1			T5	158		T15	6		T45	8
valid_sources[0x7c]	13437	1			T5	132		T15	6		T45	24
valid_sources[0x7d]	12190	1			T2	1		T5	146		T15	5
valid_sources[0x7e]	12151	1			T5	150		T25	1		T15	2
valid_sources[0x7f]	12355	1			T2	2		T5	123		T15	3
valid_sources[0x80]	15035	1			T2	5		T5	130		T15	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2045346

1

T1

980

T2

36

T12

2116

values[0x0]

all_enables

biggest_size

155826

1

T1

305

T2

48

T10

5

values[0x1]

all_enables

biggest_size

155170

1

T1

292

T2

34

T10

6