Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	129260737	14577	0	0
claim_transition_if_regwen_rd_A	129260737	1121	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129260737	14577	0	0
T5	184391	1	0	0
T15	30023	0	0	0
T16	43814	0	0	0
T17	14698	0	0	0
T25	1675	0	0	0
T42	1315	0	0	0
T44	22174	0	0	0
T45	38577	0	0	0
T58	0	1	0	0
T59	0	2	0	0
T67	49580	0	0	0
T78	0	14	0	0
T106	27600	0	0	0
T115	0	4	0	0
T117	0	2	0	0
T157	0	3	0	0
T158	0	2	0	0
T159	0	1	0	0
T160	0	8	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129260737	1121	0	0
T7	27563	0	0	0
T59	324619	7	0	0
T61	0	9	0	0
T62	0	3	0	0
T71	22573	0	0	0
T122	0	10	0	0
T128	0	12	0	0
T153	0	6	0	0
T161	0	4	0	0
T162	0	6	0	0
T163	0	28	0	0
T164	0	16	0	0
T165	29652	0	0	0
T166	140389	0	0	0
T167	21515	0	0	0
T168	43720	0	0	0
T169	29986	0	0	0
T170	29027	0	0	0
T171	89617	0	0	0