Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1899332	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2125209

1

T2

703

T8

177

T4

202

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3669618	1			T2	611		T8	210		T4	156
values[0x0]	176776	1			T2	285		T8	42		T4	63
values[0x1]	178147	1			T2	267		T8	59		T4	97

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1509561	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2514980

1

T2

825

T8

215

T4

229

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26934	1			T8	4		T9	14		T11	12
valid_sources[0x01]	14075	1			T8	2		T14	312		T27	5
valid_sources[0x02]	11873	1			T8	1		T14	290		T27	5
valid_sources[0x03]	14997	1			T8	3		T4	2		T9	2
valid_sources[0x04]	13599	1			T8	2		T4	9		T9	5
valid_sources[0x05]	11429	1			T8	1		T14	265		T27	3
valid_sources[0x06]	11091	1			T14	268		T5	1		T27	5
valid_sources[0x07]	17036	1			T8	3		T4	1		T14	301
valid_sources[0x08]	11307	1			T8	2		T14	268		T27	5
valid_sources[0x09]	12238	1			T9	2		T14	269		T27	3
valid_sources[0x0a]	11272	1			T8	1		T9	29		T11	8
valid_sources[0x0b]	11384	1			T9	1		T14	284		T27	2
valid_sources[0x0c]	11688	1			T8	1		T4	13		T14	268
valid_sources[0x0d]	12834	1			T8	1		T9	6		T14	242
valid_sources[0x0e]	11350	1			T8	2		T14	267		T27	6
valid_sources[0x0f]	11005	1			T8	3		T9	1		T14	185
valid_sources[0x10]	11624	1			T8	2		T4	3		T14	270
valid_sources[0x11]	11694	1			T8	2		T9	4		T14	287
valid_sources[0x12]	30608	1			T9	12		T14	255		T27	6
valid_sources[0x13]	10896	1			T8	1		T9	9		T14	318
valid_sources[0x14]	11309	1			T8	2		T14	284		T27	5
valid_sources[0x15]	11398	1			T8	5		T9	31		T14	186
valid_sources[0x16]	11610	1			T8	2		T9	10		T14	319
valid_sources[0x17]	14497	1			T4	3		T9	1		T14	328
valid_sources[0x18]	11553	1			T8	2		T9	6		T14	275
valid_sources[0x19]	11939	1			T8	1		T14	291		T27	6
valid_sources[0x1a]	14799	1			T9	21		T14	229		T27	3
valid_sources[0x1b]	11111	1			T8	1		T14	266		T27	1
valid_sources[0x1c]	13505	1			T14	259		T27	3		T28	4
valid_sources[0x1d]	11208	1			T8	3		T14	249		T5	1
valid_sources[0x1e]	12232	1			T4	9		T9	29		T14	272
valid_sources[0x1f]	11751	1			T14	278		T27	3		T28	8
valid_sources[0x20]	12794	1			T2	1163		T8	1		T9	12
valid_sources[0x21]	12487	1			T9	8		T14	285		T27	3
valid_sources[0x22]	14262	1			T8	2		T14	244		T27	2
valid_sources[0x23]	11280	1			T8	1		T9	11		T14	307
valid_sources[0x24]	12252	1			T8	1		T9	4		T14	294
valid_sources[0x25]	120266	1			T9	9		T14	263		T27	5
valid_sources[0x26]	11001	1			T8	1		T9	6		T14	203
valid_sources[0x27]	16773	1			T4	1		T14	279		T27	6
valid_sources[0x28]	11298	1			T8	1		T9	11		T14	286
valid_sources[0x29]	69504	1			T14	241		T27	3		T28	12
valid_sources[0x2a]	12723	1			T9	14		T14	304		T27	2
valid_sources[0x2b]	11109	1			T9	5		T14	214		T27	5
valid_sources[0x2c]	10810	1			T8	1		T4	9		T9	9
valid_sources[0x2d]	11136	1			T14	277		T5	41		T27	4
valid_sources[0x2e]	12500	1			T8	4		T9	2		T14	215
valid_sources[0x2f]	12514	1			T8	3		T14	270		T27	3
valid_sources[0x30]	15063	1			T8	5		T14	251		T5	38
valid_sources[0x31]	11636	1			T14	263		T27	3		T28	3
valid_sources[0x32]	11309	1			T8	3		T9	10		T14	266
valid_sources[0x33]	39026	1			T9	16		T14	228		T5	1
valid_sources[0x34]	12947	1			T8	4		T9	3		T14	261
valid_sources[0x35]	15401	1			T8	2		T9	20		T14	283
valid_sources[0x36]	182381	1			T4	13		T14	200		T27	4
valid_sources[0x37]	11260	1			T8	1		T4	3		T14	245
valid_sources[0x38]	11178	1			T8	1		T9	3		T14	245
valid_sources[0x39]	16635	1			T8	1		T9	20		T14	282
valid_sources[0x3a]	12186	1			T9	9		T14	273		T28	3
valid_sources[0x3b]	11461	1			T8	1		T9	21		T14	261
valid_sources[0x3c]	11258	1			T9	3		T14	276		T27	3
valid_sources[0x3d]	12979	1			T8	1		T9	6		T14	271
valid_sources[0x3e]	11595	1			T9	6		T14	200		T27	4
valid_sources[0x3f]	40844	1			T8	6		T9	5		T14	318
valid_sources[0x40]	10843	1			T9	6		T14	279		T27	4
valid_sources[0x41]	13677	1			T8	2		T14	264		T27	3
valid_sources[0x42]	13457	1			T9	2		T14	234		T27	1
valid_sources[0x43]	11674	1			T8	1		T4	4		T14	230
valid_sources[0x44]	11035	1			T4	16		T9	13		T14	308
valid_sources[0x45]	22594	1			T8	1		T14	272		T27	4
valid_sources[0x46]	11063	1			T8	1		T14	268		T27	9
valid_sources[0x47]	10943	1			T9	21		T14	199		T27	1
valid_sources[0x48]	13704	1			T8	2		T14	304		T27	4
valid_sources[0x49]	11238	1			T8	1		T14	276		T27	3
valid_sources[0x4a]	11397	1			T8	1		T9	7		T14	249
valid_sources[0x4b]	12414	1			T8	1		T14	303		T27	4
valid_sources[0x4c]	11022	1			T9	14		T14	247		T27	2
valid_sources[0x4d]	21466	1			T8	2		T14	246		T27	6
valid_sources[0x4e]	11332	1			T8	1		T4	10		T14	293
valid_sources[0x4f]	11478	1			T14	258		T5	5		T27	1
valid_sources[0x50]	10516	1			T9	3		T14	188		T27	1
valid_sources[0x51]	11039	1			T8	2		T9	4		T14	265
valid_sources[0x52]	11790	1			T8	1		T14	304		T27	5
valid_sources[0x53]	11608	1			T9	4		T14	334		T27	4
valid_sources[0x54]	12049	1			T8	4		T9	10		T14	225
valid_sources[0x55]	11101	1			T8	1		T4	11		T9	2
valid_sources[0x56]	11021	1			T8	4		T14	271		T27	1
valid_sources[0x57]	27332	1			T8	3		T4	5		T14	260
valid_sources[0x58]	11252	1			T9	10		T14	291		T5	30
valid_sources[0x59]	11110	1			T14	235		T5	1		T27	4
valid_sources[0x5a]	12915	1			T8	1		T14	283		T27	5
valid_sources[0x5b]	12817	1			T8	4		T4	2		T9	10
valid_sources[0x5c]	22108	1			T8	3		T9	5		T14	314
valid_sources[0x5d]	11402	1			T8	2		T9	2		T14	249
valid_sources[0x5e]	11818	1			T14	266		T27	3		T28	7
valid_sources[0x5f]	12163	1			T8	1		T4	3		T9	6
valid_sources[0x60]	10759	1			T8	1		T14	264		T27	3
valid_sources[0x61]	11364	1			T8	1		T9	1		T14	245
valid_sources[0x62]	11068	1			T8	3		T9	16		T14	214
valid_sources[0x63]	11207	1			T8	1		T9	13		T14	304
valid_sources[0x64]	11225	1			T8	5		T9	19		T14	253
valid_sources[0x65]	11955	1			T8	1		T14	300		T5	1
valid_sources[0x66]	12379	1			T8	4		T9	9		T14	273
valid_sources[0x67]	11552	1			T8	1		T14	315		T27	1
valid_sources[0x68]	11880	1			T8	2		T4	4		T9	9
valid_sources[0x69]	26641	1			T8	1		T4	9		T9	21
valid_sources[0x6a]	13960	1			T8	2		T14	267		T5	34
valid_sources[0x6b]	12339	1			T8	3		T9	7		T14	249
valid_sources[0x6c]	12848	1			T14	239		T27	3		T28	6
valid_sources[0x6d]	11163	1			T8	2		T9	2		T14	233
valid_sources[0x6e]	11496	1			T8	1		T14	214		T27	3
valid_sources[0x6f]	10816	1			T9	7		T14	258		T27	6
valid_sources[0x70]	17799	1			T8	2		T14	246		T27	4
valid_sources[0x71]	11641	1			T8	1		T9	18		T14	326
valid_sources[0x72]	12663	1			T9	19		T14	264		T27	3
valid_sources[0x73]	11793	1			T8	1		T9	2		T14	235
valid_sources[0x74]	10645	1			T8	1		T14	331		T27	2
valid_sources[0x75]	11562	1			T4	20		T9	7		T14	232
valid_sources[0x76]	11499	1			T8	4		T9	6		T14	302
valid_sources[0x77]	11168	1			T8	1		T4	3		T9	4
valid_sources[0x78]	10830	1			T9	3		T14	240		T27	2
valid_sources[0x79]	11219	1			T8	5		T9	19		T14	267
valid_sources[0x7a]	144875	1			T9	38		T14	219		T27	3
valid_sources[0x7b]	10990	1			T8	1		T9	11		T14	269
valid_sources[0x7c]	11897	1			T9	2		T14	303		T27	4
valid_sources[0x7d]	11195	1			T8	2		T9	14		T14	252
valid_sources[0x7e]	11303	1			T14	295		T27	6		T28	6
valid_sources[0x7f]	10921	1			T8	1		T9	8		T14	307
valid_sources[0x80]	11032	1			T14	244		T27	4		T28	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1819666

1

T2

240

T8

95

T4

65

values[0x0]

all_enables

biggest_size

153056

1

T2

237

T8

33

T4

49

values[0x1]

all_enables

biggest_size

152487

1

T2

226

T8

49

T4

88