Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	110509758	13622	0	0
claim_transition_if_regwen_rd_A	110509758	1242	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110509758	13622	0	0
T7	22536	0	0	0
T19	32052	0	0	0
T36	24069	0	0	0
T44	29232	0	0	0
T46	0	11	0	0
T47	0	17	0	0
T50	35187	0	0	0
T60	0	12	0	0
T63	4197	0	0	0
T86	227976	3	0	0
T88	0	6	0	0
T102	0	9	0	0
T145	0	11	0	0
T146	0	1	0	0
T147	0	3	0	0
T148	0	2	0	0
T149	39733	0	0	0
T150	18338	0	0	0
T151	946273	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110509758	1242	0	0
T73	1595	0	0	0
T107	0	14	0	0
T119	0	20	0	0
T152	228491	7	0	0
T153	0	8	0	0
T154	0	7	0	0
T155	0	18	0	0
T156	0	27	0	0
T157	0	13	0	0
T158	0	9	0	0
T159	0	26	0	0
T160	23182	0	0	0
T161	11243	0	0	0
T162	20034	0	0	0
T163	910	0	0	0
T164	56577	0	0	0
T165	22305	0	0	0
T166	23070	0	0	0
T167	23741	0	0	0