Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1996062	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2226968

1

T1

11

T2

76

T3

743

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3861382	1			T1	5		T2	70		T3	455
values[0x0]	180552	1			T1	5		T2	29		T3	305
values[0x1]	181096	1			T1	10		T2	19		T3	327

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1586538	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2636492

1

T1

13

T2

88

T3

820

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15966	1			T3	3		T5	94		T6	1024
valid_sources[0x01]	14208	1			T3	2		T5	93		T6	1035
valid_sources[0x02]	13863	1			T3	5		T5	91		T6	994
valid_sources[0x03]	15009	1			T5	102		T6	1079		T13	9
valid_sources[0x04]	14237	1			T3	2		T5	109		T6	1138
valid_sources[0x05]	14183	1			T3	2		T4	2		T5	105
valid_sources[0x06]	16419	1			T3	3		T5	95		T6	985
valid_sources[0x07]	15066	1			T3	2		T5	108		T6	1132
valid_sources[0x08]	14043	1			T2	1		T3	7		T5	105
valid_sources[0x09]	21541	1			T2	4		T3	6		T4	20
valid_sources[0x0a]	13582	1			T3	4		T5	94		T6	1111
valid_sources[0x0b]	15458	1			T3	4		T5	96		T6	1141
valid_sources[0x0c]	16312	1			T3	6		T5	101		T6	971
valid_sources[0x0d]	14705	1			T3	2		T4	11		T5	119
valid_sources[0x0e]	14670	1			T2	3		T3	1		T4	1
valid_sources[0x0f]	14522	1			T3	4		T5	106		T6	1029
valid_sources[0x10]	14646	1			T3	2		T4	9		T5	125
valid_sources[0x11]	15268	1			T3	4		T5	105		T6	1049
valid_sources[0x12]	14290	1			T5	104		T6	1043		T7	1
valid_sources[0x13]	13931	1			T3	5		T4	30		T5	105
valid_sources[0x14]	14559	1			T3	8		T4	14		T5	122
valid_sources[0x15]	14151	1			T3	5		T4	29		T5	115
valid_sources[0x16]	34794	1			T3	5		T5	108		T6	1024
valid_sources[0x17]	14356	1			T3	2		T5	110		T6	1045
valid_sources[0x18]	68769	1			T2	3		T3	9		T5	115
valid_sources[0x19]	14182	1			T3	6		T5	90		T6	1030
valid_sources[0x1a]	14569	1			T3	3		T4	6		T5	108
valid_sources[0x1b]	15193	1			T3	5		T5	132		T6	1044
valid_sources[0x1c]	15557	1			T3	5		T4	15		T5	106
valid_sources[0x1d]	14309	1			T2	1		T3	6		T5	98
valid_sources[0x1e]	13648	1			T3	5		T5	93		T6	1051
valid_sources[0x1f]	13607	1			T3	3		T5	105		T6	1065
valid_sources[0x20]	13890	1			T3	9		T4	19		T5	120
valid_sources[0x21]	14754	1			T3	5		T4	28		T5	110
valid_sources[0x22]	14054	1			T2	14		T3	6		T4	33
valid_sources[0x23]	13437	1			T2	4		T3	3		T5	122
valid_sources[0x24]	14592	1			T2	2		T3	6		T5	115
valid_sources[0x25]	13968	1			T3	6		T4	1		T5	101
valid_sources[0x26]	14613	1			T3	3		T5	117		T6	1046
valid_sources[0x27]	13711	1			T3	3		T5	94		T6	1064
valid_sources[0x28]	14260	1			T3	7		T4	21		T5	87
valid_sources[0x29]	14288	1			T3	4		T5	109		T6	1057
valid_sources[0x2a]	13823	1			T3	1		T4	5		T5	114
valid_sources[0x2b]	13692	1			T3	4		T5	102		T6	996
valid_sources[0x2c]	14816	1			T3	3		T5	93		T6	1076
valid_sources[0x2d]	14538	1			T3	3		T5	120		T6	1040
valid_sources[0x2e]	13779	1			T2	7		T3	1		T4	21
valid_sources[0x2f]	13914	1			T3	5		T5	105		T6	1009
valid_sources[0x30]	14629	1			T3	7		T4	12		T5	107
valid_sources[0x31]	14367	1			T3	3		T5	104		T6	1055
valid_sources[0x32]	15883	1			T3	11		T5	98		T6	1032
valid_sources[0x33]	14503	1			T3	5		T5	107		T6	1025
valid_sources[0x34]	14007	1			T3	3		T4	13		T5	105
valid_sources[0x35]	15397	1			T3	7		T5	115		T6	1074
valid_sources[0x36]	15737	1			T3	5		T4	8		T5	110
valid_sources[0x37]	14381	1			T3	5		T4	3		T5	104
valid_sources[0x38]	16052	1			T3	3		T4	28		T5	116
valid_sources[0x39]	15668	1			T3	4		T5	116		T6	1070
valid_sources[0x3a]	15992	1			T3	4		T5	107		T6	1066
valid_sources[0x3b]	15094	1			T3	2		T5	101		T6	977
valid_sources[0x3c]	13359	1			T3	1		T4	13		T5	88
valid_sources[0x3d]	17461	1			T2	1		T3	5		T4	1
valid_sources[0x3e]	15294	1			T3	4		T5	96		T6	1079
valid_sources[0x3f]	13975	1			T2	6		T3	4		T5	114
valid_sources[0x40]	14541	1			T3	5		T4	7		T5	113
valid_sources[0x41]	14351	1			T3	5		T5	112		T6	1035
valid_sources[0x42]	14008	1			T3	5		T4	2		T5	96
valid_sources[0x43]	13980	1			T3	6		T5	101		T6	990
valid_sources[0x44]	14068	1			T3	1		T4	3		T5	108
valid_sources[0x45]	14363	1			T3	1		T4	35		T5	112
valid_sources[0x46]	18344	1			T3	2		T4	10		T5	101
valid_sources[0x47]	14060	1			T2	3		T3	5		T5	86
valid_sources[0x48]	15918	1			T3	3		T5	100		T6	1024
valid_sources[0x49]	15580	1			T3	8		T5	104		T6	1093
valid_sources[0x4a]	14265	1			T3	4		T5	108		T6	1127
valid_sources[0x4b]	21789	1			T3	1		T5	106		T6	1101
valid_sources[0x4c]	14150	1			T3	5		T4	39		T5	108
valid_sources[0x4d]	19090	1			T3	1		T5	107		T6	1047
valid_sources[0x4e]	14049	1			T3	1		T5	102		T6	1049
valid_sources[0x4f]	15020	1			T2	2		T3	3		T5	106
valid_sources[0x50]	16116	1			T4	16		T5	99		T6	1043
valid_sources[0x51]	13550	1			T3	3		T5	99		T6	948
valid_sources[0x52]	16338	1			T3	9		T4	28		T5	111
valid_sources[0x53]	13872	1			T3	4		T5	130		T6	1040
valid_sources[0x54]	13933	1			T3	5		T4	22		T5	102
valid_sources[0x55]	13961	1			T2	4		T3	4		T5	114
valid_sources[0x56]	14692	1			T3	6		T5	101		T6	1042
valid_sources[0x57]	13853	1			T3	4		T4	28		T5	105
valid_sources[0x58]	14853	1			T3	5		T5	97		T6	1095
valid_sources[0x59]	15389	1			T3	7		T5	89		T6	1065
valid_sources[0x5a]	14997	1			T3	4		T5	91		T6	1034
valid_sources[0x5b]	16332	1			T2	3		T3	7		T5	89
valid_sources[0x5c]	15217	1			T2	6		T3	1		T4	49
valid_sources[0x5d]	17803	1			T3	4		T4	37		T5	103
valid_sources[0x5e]	19074	1			T3	11		T5	113		T6	1013
valid_sources[0x5f]	19938	1			T3	3		T4	50		T5	105
valid_sources[0x60]	55704	1			T3	4		T5	115		T6	1075
valid_sources[0x61]	13846	1			T3	2		T5	104		T6	1044
valid_sources[0x62]	14324	1			T3	2		T4	41		T5	127
valid_sources[0x63]	14321	1			T3	7		T5	116		T6	991
valid_sources[0x64]	14516	1			T3	3		T5	105		T6	1106
valid_sources[0x65]	13878	1			T3	4		T4	6		T5	80
valid_sources[0x66]	14324	1			T3	1		T5	109		T6	1012
valid_sources[0x67]	13534	1			T3	9		T5	93		T6	996
valid_sources[0x68]	14617	1			T3	2		T5	124		T6	1005
valid_sources[0x69]	14223	1			T3	6		T5	105		T6	1025
valid_sources[0x6a]	14004	1			T3	2		T5	101		T6	1038
valid_sources[0x6b]	16271	1			T3	5		T5	100		T6	1029
valid_sources[0x6c]	13862	1			T3	4		T5	112		T6	1003
valid_sources[0x6d]	14035	1			T3	2		T5	104		T6	1024
valid_sources[0x6e]	14506	1			T3	5		T5	98		T6	1039
valid_sources[0x6f]	14176	1			T3	4		T5	108		T6	1001
valid_sources[0x70]	15048	1			T2	3		T3	3		T5	102
valid_sources[0x71]	15092	1			T1	20		T3	7		T4	14
valid_sources[0x72]	15139	1			T3	8		T4	3		T5	103
valid_sources[0x73]	14179	1			T3	1		T5	97		T6	1006
valid_sources[0x74]	14617	1			T2	5		T3	4		T5	116
valid_sources[0x75]	15821	1			T3	3		T4	9		T5	95
valid_sources[0x76]	14265	1			T3	4		T5	109		T6	1023
valid_sources[0x77]	15843	1			T3	3		T5	104		T6	1015
valid_sources[0x78]	14481	1			T3	2		T5	118		T6	1080
valid_sources[0x79]	13781	1			T3	1		T5	100		T6	1098
valid_sources[0x7a]	14697	1			T3	5		T4	66		T5	100
valid_sources[0x7b]	15910	1			T3	3		T5	85		T6	986
valid_sources[0x7c]	15344	1			T3	12		T5	98		T6	1095
valid_sources[0x7d]	16477	1			T3	3		T5	90		T6	992
valid_sources[0x7e]	14315	1			T3	5		T4	25		T5	123
valid_sources[0x7f]	13939	1			T3	5		T5	117		T6	953
valid_sources[0x80]	13892	1			T3	3		T4	5		T5	129

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1915531

1

T1

1

T2

32

T3

196

values[0x0]

all_enables

biggest_size

156489

1

T1

3

T2

26

T3

253

values[0x1]

all_enables

biggest_size

154948

1

T1

7

T2

18

T3

294