| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 91.67 | 1 | 100 | 1 | 1 | 64 | 64 | 
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| mubi4_cov_of_tb.dut.u_otp_lc_data_i_rma_token_valid_if | 83.33 | 1 | 100 | 1 | 64 | 64 | 
| mubi4_cov_of_tb.dut.u_otp_lc_data_i_secrets_valid_if | 83.33 | 1 | 100 | 1 | 64 | 64 | 
| mubi4_cov_of_tb.dut.u_otp_lc_data_i_test_tokens_valid_if | 83.33 | 1 | 100 | 1 | 64 | 64 | 
| mubi4_cov_of_tb.dut.u_lc_clk_byp_ack_i_if | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[0].lc_tx_if | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[1].lc_tx_if | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 83.33 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 6 | 1 | 5 | 83.33 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 83.33 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 6 | 1 | 5 | 83.33 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 83.33 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 6 | 1 | 5 | 83.33 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 6 | 0 | 6 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 6 | 0 | 6 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 6 | 0 | 6 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 6 | 1 | 5 | 83.33 | 
| NAME | COUNT | AT LEAST | NUMBER | STATUS | 
| false | 0 | 1 | 1 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 324 | 1 | T50 | 8 | T51 | 8 | T52 | 15 | ||||
| others[1] | 335 | 1 | T50 | 14 | T51 | 8 | T52 | 10 | ||||
| others[2] | 296 | 1 | T50 | 6 | T51 | 16 | T52 | 6 | ||||
| others[3] | 562 | 1 | T50 | 12 | T51 | 4 | T52 | 12 | ||||
| true | 62991 | 1 | T1 | 1 | T2 | 7 | T3 | 80 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 6 | 1 | 5 | 83.33 | 
| NAME | COUNT | AT LEAST | NUMBER | STATUS | 
| true | 0 | 1 | 1 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 306 | 1 | T50 | 13 | T51 | 2 | T52 | 14 | ||||
| others[1] | 338 | 1 | T50 | 17 | T51 | 4 | T52 | 2 | ||||
| others[2] | 356 | 1 | T50 | 10 | T51 | 2 | T52 | 2 | ||||
| others[3] | 575 | 1 | T50 | 8 | T51 | 14 | T52 | 11 | ||||
| false | 62986 | 1 | T1 | 1 | T2 | 7 | T3 | 80 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 6 | 1 | 5 | 83.33 | 
| NAME | COUNT | AT LEAST | NUMBER | STATUS | 
| false | 0 | 1 | 1 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 306 | 1 | T50 | 2 | T51 | 6 | T52 | 6 | ||||
| others[1] | 329 | 1 | T51 | 6 | T52 | 8 | T200 | 12 | ||||
| others[2] | 357 | 1 | T50 | 4 | T51 | 8 | T52 | 8 | ||||
| others[3] | 585 | 1 | T50 | 14 | T51 | 9 | T52 | 14 | ||||
| true | 62988 | 1 | T1 | 1 | T2 | 7 | T3 | 80 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 6 | 0 | 6 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 153 | 1 | T50 | 5 | T51 | 2 | T200 | 3 | ||||
| others[1] | 192 | 1 | T50 | 5 | T51 | 3 | T52 | 6 | ||||
| others[2] | 164 | 1 | T50 | 4 | T51 | 3 | T52 | 2 | ||||
| others[3] | 286 | 1 | T50 | 9 | T51 | 4 | T52 | 7 | ||||
| false | 1311742 | 1 | T1 | 1 | T2 | 7 | T3 | 80 | ||||
| true | 1247845 | 1 | T5 | 679 | T6 | 38773 | T13 | 5 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 6 | 0 | 6 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 195 | 1 | T50 | 2 | T52 | 9 | T200 | 5 | ||||
| others[1] | 200 | 1 | T51 | 1 | T52 | 3 | T200 | 2 | ||||
| others[2] | 191 | 1 | T50 | 3 | T51 | 3 | T52 | 4 | ||||
| others[3] | 316 | 1 | T50 | 9 | T51 | 2 | T52 | 7 | ||||
| false | 4180352 | 1 | T1 | 1 | T2 | 7 | T3 | 81 | ||||
| true | 4116539 | 1 | T3 | 1 | T4 | 2 | T5 | 34775 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 6 | 0 | 6 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 195 | 1 | T50 | 2 | T52 | 9 | T200 | 5 | ||||
| others[1] | 200 | 1 | T51 | 1 | T52 | 3 | T200 | 2 | ||||
| others[2] | 191 | 1 | T50 | 3 | T51 | 3 | T52 | 4 | ||||
| others[3] | 316 | 1 | T50 | 9 | T51 | 2 | T52 | 7 | ||||
| false | 4180352 | 1 | T1 | 1 | T2 | 7 | T3 | 81 | ||||
| true | 4116539 | 1 | T3 | 1 | T4 | 2 | T5 | 34775 | 
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |