Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	131040499	13002	0	0
claim_transition_if_regwen_rd_A	131040499	1905	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131040499	13002	0	0
T6	507941	17	0	0
T7	25257	0	0	0
T8	39969	0	0	0
T11	32210	0	0	0
T12	1072	0	0	0
T13	66854	0	0	0
T14	36149	0	0	0
T15	21843	0	0	0
T28	30750	0	0	0
T29	3908	0	0	0
T47	0	10	0	0
T81	0	2	0	0
T92	0	1	0	0
T94	0	1	0	0
T133	0	7	0	0
T134	0	13	0	0
T135	0	6	0	0
T136	0	1	0	0
T137	0	3	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131040499	1905	0	0
T71	633844	0	0	0
T95	0	72	0	0
T96	0	11	0	0
T109	0	1	0	0
T138	259046	3	0	0
T139	0	4	0	0
T140	0	2	0	0
T141	0	10	0	0
T142	0	133	0	0
T143	0	9	0	0
T144	0	73	0	0
T145	208275	0	0	0
T146	4494	0	0	0
T147	34091	0	0	0
T148	254038	0	0	0
T149	134672	0	0	0
T150	75407	0	0	0
T151	20495	0	0	0
T152	18604	0	0	0