Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1642861	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1863898

1

T1

11

T2

1421

T3

1641

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3165430	1			T1	11		T2	1564		T3	3022
values[0x0]	170250	1			T1	6		T2	366		T3	75
values[0x1]	171079	1			T1	3		T2	354		T3	76

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1306411	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2200348

1

T1

14

T2

1606

T3

1943

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10223	1			T3	15		T12	4		T7	10
valid_sources[0x01]	10359	1			T3	17		T12	3		T27	4
valid_sources[0x02]	11446	1			T3	13		T6	4		T12	4
valid_sources[0x03]	11626	1			T3	12		T12	5		T13	1038
valid_sources[0x04]	11979	1			T3	7		T6	2		T12	9
valid_sources[0x05]	10295	1			T3	13		T12	5		T14	1
valid_sources[0x06]	62476	1			T1	1		T3	18		T6	1
valid_sources[0x07]	11610	1			T3	10		T11	44		T6	2
valid_sources[0x08]	10063	1			T3	15		T11	5		T6	6
valid_sources[0x09]	10124	1			T3	11		T6	3		T12	7
valid_sources[0x0a]	11549	1			T3	13		T11	26		T12	8
valid_sources[0x0b]	10200	1			T3	19		T11	36		T12	4
valid_sources[0x0c]	10265	1			T3	12		T12	1		T27	3
valid_sources[0x0d]	9824	1			T3	10		T6	2		T12	5
valid_sources[0x0e]	10750	1			T3	11		T12	1		T14	1
valid_sources[0x0f]	10203	1			T3	9		T6	1		T12	2
valid_sources[0x10]	26690	1			T3	11		T11	42		T12	5
valid_sources[0x11]	11199	1			T3	13		T12	3		T14	3
valid_sources[0x12]	10298	1			T3	11		T6	6		T12	11
valid_sources[0x13]	10134	1			T3	10		T6	2		T12	8
valid_sources[0x14]	71062	1			T3	11		T11	13		T6	1
valid_sources[0x15]	10125	1			T3	10		T12	5		T14	1
valid_sources[0x16]	10150	1			T3	11		T11	2		T12	12
valid_sources[0x17]	13742	1			T3	21		T6	5		T12	7
valid_sources[0x18]	13357	1			T3	14		T12	8		T27	5
valid_sources[0x19]	11439	1			T3	9		T12	7		T27	2
valid_sources[0x1a]	10250	1			T3	11		T12	7		T14	1
valid_sources[0x1b]	10541	1			T3	13		T6	1		T12	13
valid_sources[0x1c]	11983	1			T3	14		T12	4		T27	4
valid_sources[0x1d]	10353	1			T3	17		T11	1		T6	2
valid_sources[0x1e]	13678	1			T3	9		T11	1		T6	1
valid_sources[0x1f]	10204	1			T3	13		T12	5		T14	2
valid_sources[0x20]	10051	1			T3	17		T6	5		T12	12
valid_sources[0x21]	29006	1			T3	13		T12	12		T27	2
valid_sources[0x22]	10176	1			T3	11		T12	6		T27	3
valid_sources[0x23]	12371	1			T3	10		T11	3		T12	3
valid_sources[0x24]	10097	1			T3	17		T12	7		T27	2
valid_sources[0x25]	10087	1			T3	16		T11	37		T6	2
valid_sources[0x26]	10362	1			T3	17		T12	8		T14	1
valid_sources[0x27]	10002	1			T3	10		T11	4		T12	7
valid_sources[0x28]	11933	1			T3	15		T11	16		T12	5
valid_sources[0x29]	11726	1			T3	9		T12	5		T7	13
valid_sources[0x2a]	12193	1			T3	7		T11	26		T6	1
valid_sources[0x2b]	10269	1			T3	8		T12	2		T27	7
valid_sources[0x2c]	10313	1			T3	11		T12	6		T27	2
valid_sources[0x2d]	10099	1			T3	14		T11	27		T12	7
valid_sources[0x2e]	29712	1			T3	16		T11	27		T6	1
valid_sources[0x2f]	10280	1			T3	12		T6	1		T12	5
valid_sources[0x30]	10005	1			T3	16		T12	5		T27	6
valid_sources[0x31]	12031	1			T3	12		T12	3		T14	3
valid_sources[0x32]	15863	1			T3	8		T12	2		T27	3
valid_sources[0x33]	10127	1			T3	11		T6	5		T12	7
valid_sources[0x34]	12425	1			T3	13		T6	17		T12	9
valid_sources[0x35]	10333	1			T3	12		T6	1		T12	10
valid_sources[0x36]	20645	1			T3	10		T12	5		T14	6
valid_sources[0x37]	10081	1			T3	15		T12	6		T14	1
valid_sources[0x38]	9994	1			T3	15		T11	21		T6	1
valid_sources[0x39]	10655	1			T3	8		T6	1		T12	7
valid_sources[0x3a]	10067	1			T3	10		T12	4		T27	4
valid_sources[0x3b]	10446	1			T3	15		T11	6		T6	1
valid_sources[0x3c]	10446	1			T3	6		T12	9		T14	1
valid_sources[0x3d]	10432	1			T3	11		T11	5		T12	2
valid_sources[0x3e]	11025	1			T3	12		T11	20		T6	2
valid_sources[0x3f]	10266	1			T3	18		T6	1		T12	9
valid_sources[0x40]	9895	1			T1	1		T3	15		T11	10
valid_sources[0x41]	10606	1			T3	10		T6	1		T12	9
valid_sources[0x42]	9881	1			T3	11		T12	3		T14	2
valid_sources[0x43]	10466	1			T3	12		T12	9		T27	6
valid_sources[0x44]	10338	1			T3	10		T12	2		T14	3
valid_sources[0x45]	10415	1			T3	15		T11	8		T6	1
valid_sources[0x46]	10001	1			T3	10		T11	11		T12	8
valid_sources[0x47]	71112	1			T3	9		T12	12		T14	2
valid_sources[0x48]	9968	1			T3	12		T12	2		T27	5
valid_sources[0x49]	11479	1			T3	8		T6	1		T12	5
valid_sources[0x4a]	11688	1			T3	17		T11	2		T6	3
valid_sources[0x4b]	9996	1			T3	15		T6	4		T12	11
valid_sources[0x4c]	10188	1			T3	14		T12	3		T27	4
valid_sources[0x4d]	13144	1			T3	7		T12	7		T14	5
valid_sources[0x4e]	10113	1			T3	8		T12	5		T14	2
valid_sources[0x4f]	10322	1			T3	11		T12	6		T27	8
valid_sources[0x50]	10245	1			T3	12		T11	21		T6	1
valid_sources[0x51]	9862	1			T3	23		T12	4		T27	3
valid_sources[0x52]	10790	1			T3	14		T11	4		T12	4
valid_sources[0x53]	9941	1			T3	9		T12	5		T7	1
valid_sources[0x54]	11298	1			T3	11		T12	9		T7	7
valid_sources[0x55]	10116	1			T3	9		T11	13		T6	3
valid_sources[0x56]	54367	1			T3	8		T12	8		T27	4
valid_sources[0x57]	10421	1			T3	8		T12	5		T14	1
valid_sources[0x58]	14941	1			T3	12		T6	3		T12	12
valid_sources[0x59]	10445	1			T3	14		T12	6		T27	3
valid_sources[0x5a]	10237	1			T3	21		T6	2		T12	4
valid_sources[0x5b]	10182	1			T3	14		T12	5		T14	1
valid_sources[0x5c]	15971	1			T3	12		T12	6		T27	3
valid_sources[0x5d]	27562	1			T3	11		T6	3		T12	4
valid_sources[0x5e]	11640	1			T3	5		T12	7		T27	4
valid_sources[0x5f]	12379	1			T3	15		T11	24		T12	7
valid_sources[0x60]	12186	1			T3	12		T11	2		T12	13
valid_sources[0x61]	10298	1			T3	10		T12	12		T14	5
valid_sources[0x62]	16495	1			T3	9		T12	5		T27	6
valid_sources[0x63]	10349	1			T3	2		T6	6		T12	10
valid_sources[0x64]	15831	1			T3	13		T6	2		T12	5
valid_sources[0x65]	19556	1			T3	13		T11	17		T12	6
valid_sources[0x66]	10837	1			T3	14		T11	14		T6	3
valid_sources[0x67]	13382	1			T3	12		T6	2		T12	4
valid_sources[0x68]	10181	1			T3	9		T12	2		T7	1
valid_sources[0x69]	11480	1			T3	16		T6	1		T12	15
valid_sources[0x6a]	12645	1			T3	12		T11	22		T6	2
valid_sources[0x6b]	11926	1			T3	15		T12	5		T27	7
valid_sources[0x6c]	13167	1			T3	14		T12	7		T27	3
valid_sources[0x6d]	9675	1			T3	12		T12	7		T14	1
valid_sources[0x6e]	10287	1			T1	1		T3	10		T12	6
valid_sources[0x6f]	10382	1			T3	13		T11	6		T6	4
valid_sources[0x70]	11976	1			T3	16		T11	18		T6	7
valid_sources[0x71]	10353	1			T3	8		T11	2		T12	4
valid_sources[0x72]	10043	1			T3	18		T6	3		T12	5
valid_sources[0x73]	9989	1			T3	14		T6	2		T12	6
valid_sources[0x74]	10197	1			T3	14		T12	9		T14	6
valid_sources[0x75]	10618	1			T3	18		T12	5		T14	4
valid_sources[0x76]	10419	1			T3	19		T6	1		T12	6
valid_sources[0x77]	10435	1			T3	11		T12	4		T27	3
valid_sources[0x78]	10650	1			T3	11		T6	1		T12	15
valid_sources[0x79]	13631	1			T3	9		T6	4		T12	5
valid_sources[0x7a]	11914	1			T3	12		T12	4		T7	3
valid_sources[0x7b]	10293	1			T3	12		T12	11		T27	1
valid_sources[0x7c]	16880	1			T3	14		T12	4		T27	3
valid_sources[0x7d]	11616	1			T3	13		T6	3		T12	9
valid_sources[0x7e]	13660	1			T3	16		T12	2		T7	10
valid_sources[0x7f]	10128	1			T3	11		T6	1		T12	4
valid_sources[0x80]	12587	1			T3	23		T11	14		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1569719

1

T1

5

T2

798

T3

1512

values[0x0]

all_enables

biggest_size

147562

1

T1

4

T2

322

T3

66

values[0x1]

all_enables

biggest_size

146617

1

T1

2

T2

301

T3

63