Unified Coverage Report :: Module :: lc_ctrl_reg_top

Module : lc_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.36	100.00	97.45			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.36	100.00	97.45			100.00	100.00
tb.dut.u_reg_tap	99.73	100.00	98.92			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.36	100.00	97.45			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.10	97.79	97.70	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_bus_integ_error	100.00	100.00
u_alert_test_fatal_prog_error	100.00	100.00
u_alert_test_fatal_state_error	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_claim_transition_if	100.00	100.00
u_claim_transition_if_regwen	100.00	100.00	100.00			100.00
u_device_id_0	100.00	100.00
u_device_id_1	100.00	100.00
u_device_id_2	100.00	100.00
u_device_id_3	100.00	100.00
u_device_id_4	100.00	100.00
u_device_id_5	100.00	100.00
u_device_id_6	100.00	100.00
u_device_id_7	100.00	100.00
u_hw_revision0_product_id	33.33	33.33
u_hw_revision0_silicon_creator_id	33.33	33.33
u_hw_revision1_reserved	33.33	33.33
u_hw_revision1_revision_id	33.33	33.33
u_lc_id_state	66.67	66.67
u_lc_state	100.00	100.00
u_lc_transition_cnt	100.00	100.00
u_manuf_state_0	100.00	100.00
u_manuf_state_1	100.00	100.00
u_manuf_state_2	100.00	100.00
u_manuf_state_3	100.00	100.00
u_manuf_state_4	100.00	100.00
u_manuf_state_5	100.00	100.00
u_manuf_state_6	100.00	100.00
u_manuf_state_7	100.00	100.00
u_otp_vendor_test_ctrl	100.00	100.00
u_otp_vendor_test_status	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.97	97.14	98.75			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_bus_integ_error	100.00	100.00
u_status_ext_clock_switched	100.00	100.00
u_status_flash_rma_error	100.00	100.00
u_status_initialized	100.00	100.00
u_status_otp_error	100.00	100.00
u_status_otp_partition_error	100.00	100.00
u_status_ready	100.00	100.00
u_status_state_error	100.00	100.00
u_status_token_error	100.00	100.00
u_status_transition_count_error	100.00	100.00
u_status_transition_error	100.00	100.00
u_status_transition_successful	100.00	100.00
u_transition_cmd	100.00	100.00
u_transition_ctrl_ext_clock_en	100.00	100.00
u_transition_ctrl_volatile_raw_unlock	100.00	100.00
u_transition_regwen	100.00	100.00
u_transition_target	100.00	100.00
u_transition_token_0	100.00	100.00
u_transition_token_1	100.00	100.00
u_transition_token_2	100.00	100.00
u_transition_token_3	100.00	100.00

---

Module Instance : tb.dut.u_reg_tap

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.73	100.00	98.92			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.90	97.36	98.54	73.61		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_bus_integ_error	100.00	100.00
u_alert_test_fatal_prog_error	100.00	100.00
u_alert_test_fatal_state_error	100.00	100.00
u_chk	90.18	100.00		70.54			100.00
u_claim_transition_if	100.00	100.00
u_claim_transition_if_regwen	100.00	100.00	100.00			100.00
u_device_id_0	100.00	100.00
u_device_id_1	100.00	100.00
u_device_id_2	100.00	100.00
u_device_id_3	100.00	100.00
u_device_id_4	100.00	100.00
u_device_id_5	100.00	100.00
u_device_id_6	100.00	100.00
u_device_id_7	100.00	100.00
u_hw_revision0_product_id	33.33	33.33
u_hw_revision0_silicon_creator_id	33.33	33.33
u_hw_revision1_reserved	33.33	33.33
u_hw_revision1_revision_id	33.33	33.33
u_lc_id_state	100.00	100.00
u_lc_state	100.00	100.00
u_lc_transition_cnt	100.00	100.00
u_manuf_state_0	100.00	100.00
u_manuf_state_1	100.00	100.00
u_manuf_state_2	100.00	100.00
u_manuf_state_3	100.00	100.00
u_manuf_state_4	100.00	100.00
u_manuf_state_5	100.00	100.00
u_manuf_state_6	100.00	100.00
u_manuf_state_7	100.00	100.00
u_otp_vendor_test_ctrl	100.00	100.00
u_otp_vendor_test_status	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	97.14	92.19	96.36			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_bus_integ_error	100.00	100.00
u_status_ext_clock_switched	100.00	100.00
u_status_flash_rma_error	100.00	100.00
u_status_initialized	100.00	100.00
u_status_otp_error	100.00	100.00
u_status_otp_partition_error	100.00	100.00
u_status_ready	100.00	100.00
u_status_state_error	100.00	100.00
u_status_token_error	100.00	100.00
u_status_transition_count_error	100.00	100.00
u_status_transition_error	100.00	100.00
u_status_transition_successful	100.00	100.00
u_transition_cmd	100.00	100.00
u_transition_ctrl_ext_clock_en	100.00	100.00
u_transition_ctrl_volatile_raw_unlock	100.00	100.00
u_transition_regwen	100.00	100.00
u_transition_target	100.00	100.00
u_transition_token_0	100.00	100.00
u_transition_token_1	100.00	100.00
u_transition_token_2	100.00	100.00
u_transition_token_3	100.00	100.00

Line Coverage for Module : lc_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		227	227	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	592	1	1	100.00
CONT_ASSIGN	599	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	616	1	1	100.00
CONT_ASSIGN	623	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	671	1	1	100.00
CONT_ASSIGN	674	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	694	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	711	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
ALWAYS	1140	36	36	100.00
CONT_ASSIGN	1178	1	1	100.00
ALWAYS	1182	1	1	100.00
CONT_ASSIGN	1221	1	1	100.00
CONT_ASSIGN	1223	1	1	100.00
CONT_ASSIGN	1225	1	1	100.00
CONT_ASSIGN	1227	1	1	100.00
CONT_ASSIGN	1228	1	1	100.00
CONT_ASSIGN	1229	1	1	100.00
CONT_ASSIGN	1231	1	1	100.00
CONT_ASSIGN	1232	1	1	100.00
CONT_ASSIGN	1233	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1236	1	1	100.00
CONT_ASSIGN	1237	1	1	100.00
CONT_ASSIGN	1239	1	1	100.00
CONT_ASSIGN	1240	1	1	100.00
CONT_ASSIGN	1241	1	1	100.00
CONT_ASSIGN	1243	1	1	100.00
CONT_ASSIGN	1245	1	1	100.00
CONT_ASSIGN	1246	1	1	100.00
CONT_ASSIGN	1247	1	1	100.00
CONT_ASSIGN	1249	1	1	100.00
CONT_ASSIGN	1250	1	1	100.00
CONT_ASSIGN	1251	1	1	100.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1255	1	1	100.00
CONT_ASSIGN	1257	1	1	100.00
CONT_ASSIGN	1258	1	1	100.00
CONT_ASSIGN	1259	1	1	100.00
CONT_ASSIGN	1261	1	1	100.00
CONT_ASSIGN	1262	1	1	100.00
CONT_ASSIGN	1263	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1266	1	1	100.00
CONT_ASSIGN	1267	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1271	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1278	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1280	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1283	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
ALWAYS	1295	36	36	100.00
ALWAYS	1335	53	53	100.00
CONT_ASSIGN	1504	0	0
CONT_ASSIGN	1512	1	1	100.00
CONT_ASSIGN	1513	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
233	1	1
248	1	1
264	1	1
280	1	1
496	1	1
499	1	1
513	1	1
535	1	1
538	1	1
552	1	1
558	1	1
561	1	1
576	1	1
592	1	1
599	1	1
602	1	1
616	1	1
623	1	1
626	1	1
640	1	1
647	1	1
650	1	1
664	1	1
671	1	1
674	1	1
688	1	1
694	1	1
697	1	1
711	1	1
717	1	1
720	1	1
734	1	1
1140	1	1
1141	1	1
1142	1	1
1143	1	1
1144	1	1
1145	1	1
1146	1	1
1147	1	1
1148	1	1
1149	1	1
1150	1	1
1151	1	1
1152	1	1
1153	1	1
1154	1	1
1155	1	1
1156	1	1
1157	1	1
1158	1	1
1159	1	1
1160	1	1
1161	1	1
1162	1	1
1163	1	1
1164	1	1
1165	1	1
1166	1	1
1167	1	1
1168	1	1
1169	1	1
1170	1	1
1171	1	1
1172	1	1
1173	1	1
1174	1	1
1175	1	1
1178	1	1
1182	1	1
1221	1	1
1223	1	1
1225	1	1
1227	1	1
1228	1	1
1229	1	1
1231	1	1
1232	1	1
1233	1	1
1235	1	1
1236	1	1
1237	1	1
1239	1	1
1240	1	1
1241	1	1
1243	1	1
1245	1	1
1246	1	1
1247	1	1
1249	1	1
1250	1	1
1251	1	1
1253	1	1
1254	1	1
1255	1	1
1257	1	1
1258	1	1
1259	1	1
1261	1	1
1262	1	1
1263	1	1
1265	1	1
1266	1	1
1267	1	1
1269	1	1
1270	1	1
1271	1	1
1272	1	1
1273	1	1
1274	1	1
1275	1	1
1276	1	1
1277	1	1
1278	1	1
1279	1	1
1280	1	1
1281	1	1
1282	1	1
1283	1	1
1284	1	1
1285	1	1
1286	1	1
1287	1	1
1288	1	1
1289	1	1
1290	1	1
1291	1	1
1295	1	1
1296	1	1
1297	1	1
1298	1	1
1299	1	1
1300	1	1
1301	1	1
1302	1	1
1303	1	1
1304	1	1
1305	1	1
1306	1	1
1307	1	1
1308	1	1
1309	1	1
1310	1	1
1311	1	1
1312	1	1
1313	1	1
1314	1	1
1315	1	1
1316	1	1
1317	1	1
1318	1	1
1319	1	1
1320	1	1
1321	1	1
1322	1	1
1323	1	1
1324	1	1
1325	1	1
1326	1	1
1327	1	1
1328	1	1
1329	1	1
1330	1	1
1335	1	1
1336	1	1
1338	1	1
1339	1	1
1340	1	1
1344	1	1
1345	1	1
1346	1	1
1347	1	1
1348	1	1
1349	1	1
1350	1	1
1351	1	1
1352	1	1
1353	1	1
1354	1	1
1355	1	1
1359	1	1
1363	1	1
1367	1	1
1371	1	1
1375	1	1
1376	1	1
1380	1	1
1384	1	1
1388	1	1
1392	1	1
1396	1	1
1400	1	1
1404	1	1
1408	1	1
1412	1	1
1416	1	1
1420	1	1
1421	1	1
1425	1	1
1426	1	1
1430	1	1
1434	1	1
1438	1	1
1442	1	1
1446	1	1
1450	1	1
1454	1	1
1458	1	1
1462	1	1
1466	1	1
1470	1	1
1474	1	1
1478	1	1
1482	1	1
1486	1	1
1490	1	1
1504		unreachable
1512	1	1
1513	1	1

---

Cond Coverage for Module : lc_ctrl_reg_top

	Total	Covered	Percent
Conditions	432	421	97.45
Logical	432	421	97.45
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
58-1290	97.43
1291	100.00

---

Branch Coverage for Module : lc_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	1178	2	2	100.00
IF	68	3	3	100.00
CASE	1336	36	36	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1178	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T79,T80,T57
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1336	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : lc_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	221612182	3910978	0	0
reAfterRv	221612182	3910978	0	0
rePulse	221612182	3430905	0	0
wePulse	221612182	480073	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	221612182	3910978	0	0
T1	10994	42	0	0
T2	106006	2284	0	0
T3	69226	3173	0	0
T4	25442	79	0	0
T5	56568	225	0	0
T6	52596	552	0	0
T7	0	314	0	0
T8	0	146	0	0
T10	2876	18	0	0
T11	55842	954	0	0
T12	78136	1616	0	0
T13	77996	1038	0	0
T14	0	191	0	0
T15	0	699	0	0
T16	0	787	0	0
T17	0	134	0	0
T18	0	974	0	0
T19	0	10820	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	221612182	3910978	0	0
T1	10994	42	0	0
T2	106006	2284	0	0
T3	69226	3173	0	0
T4	25442	79	0	0
T5	56568	225	0	0
T6	52596	552	0	0
T7	0	314	0	0
T8	0	146	0	0
T10	2876	18	0	0
T11	55842	954	0	0
T12	78136	1616	0	0
T13	77996	1038	0	0
T14	0	191	0	0
T15	0	699	0	0
T16	0	787	0	0
T17	0	134	0	0
T18	0	974	0	0
T19	0	10820	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	221612182	3430905	0	0
T1	10994	23	0	0
T2	106006	1564	0	0
T3	69226	3022	0	0
T4	25442	45	0	0
T5	56568	101	0	0
T6	52596	278	0	0
T7	0	355	0	0
T8	0	80	0	0
T10	2876	0	0	0
T11	55842	506	0	0
T12	78136	1024	0	0
T13	77996	542	0	0
T14	0	101	0	0
T15	0	411	0	0
T16	0	711	0	0
T17	0	62	0	0
T18	0	618	0	0
T19	0	6971	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	221612182	480073	0	0
T1	10994	19	0	0
T2	106006	720	0	0
T3	69226	151	0	0
T4	25442	34	0	0
T5	56568	124	0	0
T6	52596	274	0	0
T7	0	142	0	0
T8	0	66	0	0
T10	2876	18	0	0
T11	55842	448	0	0
T12	78136	592	0	0
T13	77996	496	0	0
T14	0	90	0	0
T15	0	288	0	0
T16	0	76	0	0
T17	0	72	0	0
T18	0	356	0	0
T19	0	3849	0	0

Line Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
TOTAL		227	227	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	592	1	1	100.00
CONT_ASSIGN	599	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	616	1	1	100.00
CONT_ASSIGN	623	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	671	1	1	100.00
CONT_ASSIGN	674	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	694	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	711	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
ALWAYS	1140	36	36	100.00
CONT_ASSIGN	1178	1	1	100.00
ALWAYS	1182	1	1	100.00
CONT_ASSIGN	1221	1	1	100.00
CONT_ASSIGN	1223	1	1	100.00
CONT_ASSIGN	1225	1	1	100.00
CONT_ASSIGN	1227	1	1	100.00
CONT_ASSIGN	1228	1	1	100.00
CONT_ASSIGN	1229	1	1	100.00
CONT_ASSIGN	1231	1	1	100.00
CONT_ASSIGN	1232	1	1	100.00
CONT_ASSIGN	1233	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1236	1	1	100.00
CONT_ASSIGN	1237	1	1	100.00
CONT_ASSIGN	1239	1	1	100.00
CONT_ASSIGN	1240	1	1	100.00
CONT_ASSIGN	1241	1	1	100.00
CONT_ASSIGN	1243	1	1	100.00
CONT_ASSIGN	1245	1	1	100.00
CONT_ASSIGN	1246	1	1	100.00
CONT_ASSIGN	1247	1	1	100.00
CONT_ASSIGN	1249	1	1	100.00
CONT_ASSIGN	1250	1	1	100.00
CONT_ASSIGN	1251	1	1	100.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1255	1	1	100.00
CONT_ASSIGN	1257	1	1	100.00
CONT_ASSIGN	1258	1	1	100.00
CONT_ASSIGN	1259	1	1	100.00
CONT_ASSIGN	1261	1	1	100.00
CONT_ASSIGN	1262	1	1	100.00
CONT_ASSIGN	1263	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1266	1	1	100.00
CONT_ASSIGN	1267	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1271	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1278	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1280	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1283	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
ALWAYS	1295	36	36	100.00
ALWAYS	1335	53	53	100.00
CONT_ASSIGN	1504	0	0
CONT_ASSIGN	1512	1	1	100.00
CONT_ASSIGN	1513	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
233	1	1
248	1	1
264	1	1
280	1	1
496	1	1
499	1	1
513	1	1
535	1	1
538	1	1
552	1	1
558	1	1
561	1	1
576	1	1
592	1	1
599	1	1
602	1	1
616	1	1
623	1	1
626	1	1
640	1	1
647	1	1
650	1	1
664	1	1
671	1	1
674	1	1
688	1	1
694	1	1
697	1	1
711	1	1
717	1	1
720	1	1
734	1	1
1140	1	1
1141	1	1
1142	1	1
1143	1	1
1144	1	1
1145	1	1
1146	1	1
1147	1	1
1148	1	1
1149	1	1
1150	1	1
1151	1	1
1152	1	1
1153	1	1
1154	1	1
1155	1	1
1156	1	1
1157	1	1
1158	1	1
1159	1	1
1160	1	1
1161	1	1
1162	1	1
1163	1	1
1164	1	1
1165	1	1
1166	1	1
1167	1	1
1168	1	1
1169	1	1
1170	1	1
1171	1	1
1172	1	1
1173	1	1
1174	1	1
1175	1	1
1178	1	1
1182	1	1
1221	1	1
1223	1	1
1225	1	1
1227	1	1
1228	1	1
1229	1	1
1231	1	1
1232	1	1
1233	1	1
1235	1	1
1236	1	1
1237	1	1
1239	1	1
1240	1	1
1241	1	1
1243	1	1
1245	1	1
1246	1	1
1247	1	1
1249	1	1
1250	1	1
1251	1	1
1253	1	1
1254	1	1
1255	1	1
1257	1	1
1258	1	1
1259	1	1
1261	1	1
1262	1	1
1263	1	1
1265	1	1
1266	1	1
1267	1	1
1269	1	1
1270	1	1
1271	1	1
1272	1	1
1273	1	1
1274	1	1
1275	1	1
1276	1	1
1277	1	1
1278	1	1
1279	1	1
1280	1	1
1281	1	1
1282	1	1
1283	1	1
1284	1	1
1285	1	1
1286	1	1
1287	1	1
1288	1	1
1289	1	1
1290	1	1
1291	1	1
1295	1	1
1296	1	1
1297	1	1
1298	1	1
1299	1	1
1300	1	1
1301	1	1
1302	1	1
1303	1	1
1304	1	1
1305	1	1
1306	1	1
1307	1	1
1308	1	1
1309	1	1
1310	1	1
1311	1	1
1312	1	1
1313	1	1
1314	1	1
1315	1	1
1316	1	1
1317	1	1
1318	1	1
1319	1	1
1320	1	1
1321	1	1
1322	1	1
1323	1	1
1324	1	1
1325	1	1
1326	1	1
1327	1	1
1328	1	1
1329	1	1
1330	1	1
1335	1	1
1336	1	1
1338	1	1
1339	1	1
1340	1	1
1344	1	1
1345	1	1
1346	1	1
1347	1	1
1348	1	1
1349	1	1
1350	1	1
1351	1	1
1352	1	1
1353	1	1
1354	1	1
1355	1	1
1359	1	1
1363	1	1
1367	1	1
1371	1	1
1375	1	1
1376	1	1
1380	1	1
1384	1	1
1388	1	1
1392	1	1
1396	1	1
1400	1	1
1404	1	1
1408	1	1
1412	1	1
1416	1	1
1420	1	1
1421	1	1
1425	1	1
1426	1	1
1430	1	1
1434	1	1
1438	1	1
1442	1	1
1446	1	1
1450	1	1
1454	1	1
1458	1	1
1462	1	1
1466	1	1
1470	1	1
1474	1	1
1478	1	1
1482	1	1
1486	1	1
1490	1	1
1504		unreachable
1512	1	1
1513	1	1

---

Cond Coverage for Instance : tb.dut.u_reg

	Total	Covered	Percent
Conditions	432	421	97.45
Logical	432	421	97.45
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
58-1290	97.43
1291	100.00

---

Branch Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	1178	2	2	100.00
IF	68	3	3	100.00
CASE	1336	36	36	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1178	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T79,T80,T57
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1336	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	110806091	3495194	0	0
reAfterRv	110806091	3495194	0	0
rePulse	110806091	3162538	0	0
wePulse	110806091	332656	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	110806091	3495194	0	0
T1	5497	20	0	0
T2	53003	2284	0	0
T3	34613	3173	0	0
T4	12721	0	0	0
T5	28284	0	0	0
T6	26298	276	0	0
T10	1438	18	0	0
T11	27921	954	0	0
T12	39068	1616	0	0
T13	38998	1038	0	0
T14	0	191	0	0
T16	0	787	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	110806091	3495194	0	0
T1	5497	20	0	0
T2	53003	2284	0	0
T3	34613	3173	0	0
T4	12721	0	0	0
T5	28284	0	0	0
T6	26298	276	0	0
T10	1438	18	0	0
T11	27921	954	0	0
T12	39068	1616	0	0
T13	38998	1038	0	0
T14	0	191	0	0
T16	0	787	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	110806091	3162538	0	0
T1	5497	11	0	0
T2	53003	1564	0	0
T3	34613	3022	0	0
T4	12721	0	0	0
T5	28284	0	0	0
T6	26298	139	0	0
T7	0	183	0	0
T10	1438	0	0	0
T11	27921	506	0	0
T12	39068	1024	0	0
T13	38998	542	0	0
T14	0	101	0	0
T16	0	711	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	110806091	332656	0	0
T1	5497	9	0	0
T2	53003	720	0	0
T3	34613	151	0	0
T4	12721	0	0	0
T5	28284	0	0	0
T6	26298	137	0	0
T10	1438	18	0	0
T11	27921	448	0	0
T12	39068	592	0	0
T13	38998	496	0	0
T14	0	90	0	0
T16	0	76	0	0

Line Coverage for Instance : tb.dut.u_reg_tap

	Line No.	Total	Covered	Percent
TOTAL		227	227	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	592	1	1	100.00
CONT_ASSIGN	599	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	616	1	1	100.00
CONT_ASSIGN	623	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	650	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	671	1	1	100.00
CONT_ASSIGN	674	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	694	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	711	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
ALWAYS	1140	36	36	100.00
CONT_ASSIGN	1178	1	1	100.00
ALWAYS	1182	1	1	100.00
CONT_ASSIGN	1221	1	1	100.00
CONT_ASSIGN	1223	1	1	100.00
CONT_ASSIGN	1225	1	1	100.00
CONT_ASSIGN	1227	1	1	100.00
CONT_ASSIGN	1228	1	1	100.00
CONT_ASSIGN	1229	1	1	100.00
CONT_ASSIGN	1231	1	1	100.00
CONT_ASSIGN	1232	1	1	100.00
CONT_ASSIGN	1233	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1236	1	1	100.00
CONT_ASSIGN	1237	1	1	100.00
CONT_ASSIGN	1239	1	1	100.00
CONT_ASSIGN	1240	1	1	100.00
CONT_ASSIGN	1241	1	1	100.00
CONT_ASSIGN	1243	1	1	100.00
CONT_ASSIGN	1245	1	1	100.00
CONT_ASSIGN	1246	1	1	100.00
CONT_ASSIGN	1247	1	1	100.00
CONT_ASSIGN	1249	1	1	100.00
CONT_ASSIGN	1250	1	1	100.00
CONT_ASSIGN	1251	1	1	100.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1255	1	1	100.00
CONT_ASSIGN	1257	1	1	100.00
CONT_ASSIGN	1258	1	1	100.00
CONT_ASSIGN	1259	1	1	100.00
CONT_ASSIGN	1261	1	1	100.00
CONT_ASSIGN	1262	1	1	100.00
CONT_ASSIGN	1263	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1266	1	1	100.00
CONT_ASSIGN	1267	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1271	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1278	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1280	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1283	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
ALWAYS	1295	36	36	100.00
ALWAYS	1335	53	53	100.00
CONT_ASSIGN	1504	0	0
CONT_ASSIGN	1512	1	1	100.00
CONT_ASSIGN	1513	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
233	1	1
248	1	1
264	1	1
280	1	1
496	1	1
499	1	1
513	1	1
535	1	1
538	1	1
552	1	1
558	1	1
561	1	1
576	1	1
592	1	1
599	1	1
602	1	1
616	1	1
623	1	1
626	1	1
640	1	1
647	1	1
650	1	1
664	1	1
671	1	1
674	1	1
688	1	1
694	1	1
697	1	1
711	1	1
717	1	1
720	1	1
734	1	1
1140	1	1
1141	1	1
1142	1	1
1143	1	1
1144	1	1
1145	1	1
1146	1	1
1147	1	1
1148	1	1
1149	1	1
1150	1	1
1151	1	1
1152	1	1
1153	1	1
1154	1	1
1155	1	1
1156	1	1
1157	1	1
1158	1	1
1159	1	1
1160	1	1
1161	1	1
1162	1	1
1163	1	1
1164	1	1
1165	1	1
1166	1	1
1167	1	1
1168	1	1
1169	1	1
1170	1	1
1171	1	1
1172	1	1
1173	1	1
1174	1	1
1175	1	1
1178	1	1
1182	1	1
1221	1	1
1223	1	1
1225	1	1
1227	1	1
1228	1	1
1229	1	1
1231	1	1
1232	1	1
1233	1	1
1235	1	1
1236	1	1
1237	1	1
1239	1	1
1240	1	1
1241	1	1
1243	1	1
1245	1	1
1246	1	1
1247	1	1
1249	1	1
1250	1	1
1251	1	1
1253	1	1
1254	1	1
1255	1	1
1257	1	1
1258	1	1
1259	1	1
1261	1	1
1262	1	1
1263	1	1
1265	1	1
1266	1	1
1267	1	1
1269	1	1
1270	1	1
1271	1	1
1272	1	1
1273	1	1
1274	1	1
1275	1	1
1276	1	1
1277	1	1
1278	1	1
1279	1	1
1280	1	1
1281	1	1
1282	1	1
1283	1	1
1284	1	1
1285	1	1
1286	1	1
1287	1	1
1288	1	1
1289	1	1
1290	1	1
1291	1	1
1295	1	1
1296	1	1
1297	1	1
1298	1	1
1299	1	1
1300	1	1
1301	1	1
1302	1	1
1303	1	1
1304	1	1
1305	1	1
1306	1	1
1307	1	1
1308	1	1
1309	1	1
1310	1	1
1311	1	1
1312	1	1
1313	1	1
1314	1	1
1315	1	1
1316	1	1
1317	1	1
1318	1	1
1319	1	1
1320	1	1
1321	1	1
1322	1	1
1323	1	1
1324	1	1
1325	1	1
1326	1	1
1327	1	1
1328	1	1
1329	1	1
1330	1	1
1335	1	1
1336	1	1
1338	1	1
1339	1	1
1340	1	1
1344	1	1
1345	1	1
1346	1	1
1347	1	1
1348	1	1
1349	1	1
1350	1	1
1351	1	1
1352	1	1
1353	1	1
1354	1	1
1355	1	1
1359	1	1
1363	1	1
1367	1	1
1371	1	1
1375	1	1
1376	1	1
1380	1	1
1384	1	1
1388	1	1
1392	1	1
1396	1	1
1400	1	1
1404	1	1
1408	1	1
1412	1	1
1416	1	1
1420	1	1
1421	1	1
1425	1	1
1426	1	1
1430	1	1
1434	1	1
1438	1	1
1442	1	1
1446	1	1
1450	1	1
1454	1	1
1458	1	1
1462	1	1
1466	1	1
1470	1	1
1474	1	1
1478	1	1
1482	1	1
1486	1	1
1490	1	1
1504		unreachable
1512	1	1
1513	1	1

---

Cond Coverage for Instance : tb.dut.u_reg_tap

	Total	Covered	Percent
Conditions	278	275	98.92
Logical	278	275	98.92
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Covered	T79,T80,T57
1	0	Excluded		VC_COV_UNR

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T79,T80,T57
0	1	0	Excluded		VC_COV_UNR
1	0	0	Covered	T79,T80,T57

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	0	0	Covered	T1,T2,T3
0	0	1	Excluded		VC_COV_UNR
0	1	0	Excluded		VC_COV_UNR
1	0	0	Not Covered

 LINE       499
 EXPRESSION (claim_transition_if_we & claim_transition_if_regwen_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T108,T131,T132
1	1	Covered	T1,T4,T5

 LINE       538
 EXPRESSION (transition_cmd_we & transition_regwen_qs)
             --------1--------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T15,T18,T19
1	1	Covered	T4,T5,T17

 LINE       561
 EXPRESSION (transition_ctrl_we & transition_regwen_qs)
             ---------1--------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T7
1	1	Covered	T4,T5,T6

 LINE       602
 EXPRESSION (transition_token_0_we & transition_regwen_qs)
             ----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T15,T7
1	1	Covered	T4,T5,T6

 LINE       626
 EXPRESSION (transition_token_1_we & transition_regwen_qs)
             ----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T15,T7
1	1	Covered	T4,T5,T6

 LINE       650
 EXPRESSION (transition_token_2_we & transition_regwen_qs)
             ----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T15,T7
1	1	Covered	T4,T5,T6

 LINE       674
 EXPRESSION (transition_token_3_we & transition_regwen_qs)
             ----------1----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T15,T7
1	1	Covered	T4,T5,T6

 LINE       697
 EXPRESSION (transition_target_we & transition_regwen_qs)
             ----------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T15,T7
1	1	Covered	T4,T5,T6

 LINE       720
 EXPRESSION (otp_vendor_test_ctrl_we & transition_regwen_qs)
             -----------1-----------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T15,T7
1	1	Covered	T4,T5,T6

 LINE       1141
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_ALERT_TEST_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T19,T61,T82

 LINE       1142
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_STATUS_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1143
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_CLAIM_TRANSITION_IF_REGWEN_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T19,T61,T82

 LINE       1144
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_CLAIM_TRANSITION_IF_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       1145
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_REGWEN_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T7

 LINE       1146
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_CMD_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1147
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_CTRL_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       1148
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_TOKEN_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       1149
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_TOKEN_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       1150
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_TOKEN_2_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       1151
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_TOKEN_3_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       1152
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_TRANSITION_TARGET_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       1153
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_OTP_VENDOR_TEST_CTRL_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       1154
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_OTP_VENDOR_TEST_STATUS_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1155
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_LC_STATE_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1156
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_LC_TRANSITION_CNT_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1157
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_LC_ID_STATE_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T114,T99,T108

 LINE       1158
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_HW_REVISION0_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1159
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_HW_REVISION1_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1160
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_0_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1161
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_1_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1162
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_2_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1163
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_3_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1164
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_4_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1165
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_5_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1166
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_6_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1167
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_DEVICE_ID_7_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1168
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_0_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1169
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_1_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1170
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_2_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1171
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_3_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1172
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_4_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1173
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_5_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1174
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_6_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1175
 EXPRESSION (reg_addr == lc_ctrl_reg_pkg::LC_CTRL_MANUF_STATE_7_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T15

 LINE       1178
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       1178
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       1182
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T4,T5
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests	Exclude Annotation
ALL ZEROS	Covered	T1,T4,T5
35 (addr_hit[34] & ((|(4'...	Excluded		VC_COV_UNR
34 (addr_hit[33] & ((|(4'...	Excluded		VC_COV_UNR
33 (addr_hit[32] & ((|(4'...	Excluded		VC_COV_UNR
32 (addr_hit[31] & ((|(4'...	Excluded		VC_COV_UNR
31 (addr_hit[30] & ((|(4'...	Excluded		VC_COV_UNR
30 (addr_hit[29] & ((|(4'...	Excluded		VC_COV_UNR
29 (addr_hit[28] & ((|(4'...	Excluded		VC_COV_UNR
28 (addr_hit[27] & ((|(4'...	Excluded		VC_COV_UNR
27 (addr_hit[26] & ((|(4'...	Excluded		VC_COV_UNR
26 (addr_hit[25] & ((|(4'...	Excluded		VC_COV_UNR
25 (addr_hit[24] & ((|(4'...	Excluded		VC_COV_UNR
24 (addr_hit[23] & ((|(4'...	Excluded		VC_COV_UNR
23 (addr_hit[22] & ((|(4'...	Excluded		VC_COV_UNR
22 (addr_hit[21] & ((|(4'...	Excluded		VC_COV_UNR
21 (addr_hit[20] & ((|(4'...	Excluded		VC_COV_UNR
20 (addr_hit[19] & ((|(4'...	Excluded		VC_COV_UNR
19 (addr_hit[18] & ((|(4'...	Excluded		VC_COV_UNR
18 (addr_hit[17] & ((|(4'...	Excluded		VC_COV_UNR
17 (addr_hit[16] & ((|(4'...	Excluded		VC_COV_UNR
16 (addr_hit[15] & ((|(4'...	Excluded		VC_COV_UNR
15 (addr_hit[14] & ((|(4'...	Excluded		VC_COV_UNR
14 (addr_hit[13] & ((|(4'...	Excluded		VC_COV_UNR
13 (addr_hit[12] & ((|(4'...	Excluded		VC_COV_UNR
12 (addr_hit[11] & ((|(4'...	Excluded		VC_COV_UNR
11 (addr_hit[10] & ((|(4'...	Excluded		VC_COV_UNR
10 (addr_hit[9] & ((|(4'b...	Excluded		VC_COV_UNR
9 (addr_hit[8] & ((|(4'b...	Excluded		VC_COV_UNR
8 (addr_hit[7] & ((|(4'b...	Excluded		VC_COV_UNR
7 (addr_hit[6] & ((|(4'b...	Excluded		VC_COV_UNR
6 (addr_hit[5] & ((|(4'b...	Excluded		VC_COV_UNR
5 (addr_hit[4] & ((|(4'b...	Excluded		VC_COV_UNR
4 (addr_hit[3] & ((|(4'b...	Excluded		VC_COV_UNR
3 (addr_hit[2] & ((|(4'b...	Excluded		VC_COV_UNR
2 (addr_hit[1] & ((|(4'b...	Excluded		VC_COV_UNR
1 (addr_hit[0] & ((|(4'b...	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T19,T61,T82
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T19,T61,T82
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T4,T5
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T6,T7
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T4,T5
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T4,T5
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T4,T5
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T4,T5
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T4,T5
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T4,T5
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T4,T5
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T114,T99,T108
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1182
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T5,T15
1	1	Excluded		VC_COV_UNR

 LINE       1221
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T19,T61,T82
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T114,T99,T133

 LINE       1228
 EXPRESSION (addr_hit[1] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1229
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T19,T61,T82
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T114,T99,T133

 LINE       1232
 EXPRESSION (addr_hit[3] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T6,T15

 LINE       1233
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T4,T5

 LINE       1236
 EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T6,T7
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T6,T7

 LINE       1237
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1240
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T6,T7

 LINE       1241
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T4,T5

 LINE       1246
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T6,T7

 LINE       1247
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T4,T5

 LINE       1250
 EXPRESSION (addr_hit[8] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T6,T7

 LINE       1251
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T4,T5

 LINE       1254
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T6,T7

 LINE       1255
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T4,T5

 LINE       1258
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T6,T7

 LINE       1259
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T4,T5

 LINE       1262
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T6,T7

 LINE       1263
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T4,T5

 LINE       1266
 EXPRESSION (addr_hit[12] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T6,T7

 LINE       1267
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T4,T5

 LINE       1270
 EXPRESSION (addr_hit[13] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1271
 EXPRESSION (addr_hit[14] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1272
 EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1273
 EXPRESSION (addr_hit[16] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T114,T99,T108
1	1	0	Excluded		VC_COV_UNR
1	1	1	Not Covered

 LINE       1274
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1275
 EXPRESSION (addr_hit[18] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1276
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1277
 EXPRESSION (addr_hit[20] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1278
 EXPRESSION (addr_hit[21] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1279
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1280
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1281
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1282
 EXPRESSION (addr_hit[25] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1283
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1284
 EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1285
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1286
 EXPRESSION (addr_hit[29] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1287
 EXPRESSION (addr_hit[30] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1288
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1289
 EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1290
 EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

 LINE       1291
 EXPRESSION (addr_hit[34] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T4,T5,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T4,T5,T15

---

Branch Coverage for Instance : tb.dut.u_reg_tap

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	1178	2	2	100.00
IF	68	3	3	100.00
CASE	1336	36	36	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1178	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T79,T80,T57
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1336	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_tap

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	110806091	415784	0	0
reAfterRv	110806091	415784	0	0
rePulse	110806091	268367	0	0
wePulse	110806091	147417	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	110806091	415784	0	0
T1	5497	22	0	0
T2	53003	0	0	0
T3	34613	0	0	0
T4	12721	79	0	0
T5	28284	225	0	0
T6	26298	276	0	0
T7	0	314	0	0
T8	0	146	0	0
T10	1438	0	0	0
T11	27921	0	0	0
T12	39068	0	0	0
T13	38998	0	0	0
T15	0	699	0	0
T17	0	134	0	0
T18	0	974	0	0
T19	0	10820	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	110806091	415784	0	0
T1	5497	22	0	0
T2	53003	0	0	0
T3	34613	0	0	0
T4	12721	79	0	0
T5	28284	225	0	0
T6	26298	276	0	0
T7	0	314	0	0
T8	0	146	0	0
T10	1438	0	0	0
T11	27921	0	0	0
T12	39068	0	0	0
T13	38998	0	0	0
T15	0	699	0	0
T17	0	134	0	0
T18	0	974	0	0
T19	0	10820	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	110806091	268367	0	0
T1	5497	12	0	0
T2	53003	0	0	0
T3	34613	0	0	0
T4	12721	45	0	0
T5	28284	101	0	0
T6	26298	139	0	0
T7	0	172	0	0
T8	0	80	0	0
T10	1438	0	0	0
T11	27921	0	0	0
T12	39068	0	0	0
T13	38998	0	0	0
T15	0	411	0	0
T17	0	62	0	0
T18	0	618	0	0
T19	0	6971	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	110806091	147417	0	0
T1	5497	10	0	0
T2	53003	0	0	0
T3	34613	0	0	0
T4	12721	34	0	0
T5	28284	124	0	0
T6	26298	137	0	0
T7	0	142	0	0
T8	0	66	0	0
T10	1438	0	0	0
T11	27921	0	0	0
T12	39068	0	0	0
T13	38998	0	0	0
T15	0	288	0	0
T17	0	72	0	0
T18	0	356	0	0
T19	0	3849	0	0