Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	110806091	15239	0	0
claim_transition_if_regwen_rd_A	110806091	1482	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110806091	15239	0	0
T9	37692	0	0	0
T19	369717	5	0	0
T40	390912	0	0	0
T44	148633	0	0	0
T48	0	9	0	0
T50	0	2	0	0
T61	803137	8	0	0
T77	17197	0	0	0
T78	14962	0	0	0
T82	0	17	0	0
T95	0	6	0	0
T109	50435	0	0	0
T134	0	6	0	0
T135	0	5	0	0
T136	0	1	0	0
T137	0	3	0	0
T138	23794	0	0	0
T139	101463	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110806091	1482	0	0
T96	0	5	0	0
T100	0	3	0	0
T106	0	5	0	0
T140	353451	9	0	0
T141	0	3	0	0
T142	0	5	0	0
T143	0	3	0	0
T144	0	41	0	0
T145	0	16	0	0
T146	0	308	0	0
T147	6286	0	0	0
T148	20951	0	0	0
T149	19417	0	0	0
T150	939	0	0	0
T151	30765	0	0	0
T152	2546	0	0	0
T153	1283	0	0	0
T154	1349	0	0	0
T155	529344	0	0	0