Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1287524	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1498943

1

T2

238

T3

1838

T9

1224

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2458976	1			T2	211		T3	2876		T9	1557
values[0x0]	163207	1			T2	69		T3	269		T9	268
values[0x1]	164284	1			T2	83		T3	235		T9	292

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1021386	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1765081

1

T2

260

T3

2152

T9

1413

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10235	1			T2	2		T3	23		T4	2
valid_sources[0x01]	10271	1			T3	14		T9	5		T4	2
valid_sources[0x02]	9866	1			T3	7		T9	11		T10	5
valid_sources[0x03]	9372	1			T3	13		T9	4		T4	1
valid_sources[0x04]	14403	1			T3	12		T9	16		T10	7
valid_sources[0x05]	9887	1			T3	12		T9	6		T4	1
valid_sources[0x06]	10274	1			T3	10		T4	3		T10	12
valid_sources[0x07]	9414	1			T3	16		T9	10		T41	2
valid_sources[0x08]	10693	1			T2	6		T3	13		T9	27
valid_sources[0x09]	9477	1			T3	14		T9	16		T4	1
valid_sources[0x0a]	9475	1			T3	12		T10	3		T15	2
valid_sources[0x0b]	10555	1			T3	11		T9	10		T18	145
valid_sources[0x0c]	15820	1			T3	13		T4	1		T10	5
valid_sources[0x0d]	10036	1			T2	1		T3	12		T9	17
valid_sources[0x0e]	15375	1			T3	7		T9	32		T4	1
valid_sources[0x0f]	9765	1			T3	11		T4	2		T10	4
valid_sources[0x10]	8815	1			T3	18		T9	14		T4	1
valid_sources[0x11]	9868	1			T3	13		T15	1		T41	6
valid_sources[0x12]	9479	1			T3	8		T4	3		T41	2
valid_sources[0x13]	9522	1			T3	8		T9	15		T4	3
valid_sources[0x14]	9541	1			T3	9		T9	1		T4	2
valid_sources[0x15]	9827	1			T3	14		T9	34		T4	2
valid_sources[0x16]	9453	1			T3	22		T10	1		T41	7
valid_sources[0x17]	10228	1			T3	17		T9	9		T4	4
valid_sources[0x18]	9725	1			T3	9		T9	54		T15	2
valid_sources[0x19]	10583	1			T3	10		T9	6		T4	4
valid_sources[0x1a]	8991	1			T2	6		T3	13		T4	1
valid_sources[0x1b]	8963	1			T3	5		T9	2		T41	1
valid_sources[0x1c]	12769	1			T2	6		T3	10		T9	18
valid_sources[0x1d]	9813	1			T3	10		T9	3		T10	1
valid_sources[0x1e]	9078	1			T3	16		T9	12		T4	1
valid_sources[0x1f]	17207	1			T3	11		T9	8		T4	2
valid_sources[0x20]	10002	1			T2	7		T3	14		T9	5
valid_sources[0x21]	9655	1			T3	14		T9	6		T4	1
valid_sources[0x22]	9240	1			T3	7		T9	8		T4	1
valid_sources[0x23]	9754	1			T3	12		T4	1		T15	1
valid_sources[0x24]	9622	1			T3	10		T4	4		T10	2
valid_sources[0x25]	10431	1			T3	17		T9	13		T4	2
valid_sources[0x26]	9969	1			T3	18		T9	3		T41	1
valid_sources[0x27]	9607	1			T3	8		T9	44		T4	4
valid_sources[0x28]	10212	1			T3	13		T9	21		T4	3
valid_sources[0x29]	9275	1			T3	12		T9	9		T4	2
valid_sources[0x2a]	9977	1			T3	16		T10	4		T15	1
valid_sources[0x2b]	9198	1			T2	10		T3	17		T4	2
valid_sources[0x2c]	9374	1			T3	9		T9	3		T4	4
valid_sources[0x2d]	9744	1			T3	13		T4	1		T10	2
valid_sources[0x2e]	9790	1			T3	17		T9	7		T4	1
valid_sources[0x2f]	10359	1			T3	13		T9	9		T10	7
valid_sources[0x30]	9599	1			T3	15		T9	8		T18	162
valid_sources[0x31]	10379	1			T3	12		T9	16		T4	7
valid_sources[0x32]	13383	1			T3	9		T9	19		T10	2
valid_sources[0x33]	9715	1			T3	15		T4	3		T10	2
valid_sources[0x34]	10113	1			T2	3		T3	34		T4	3
valid_sources[0x35]	11071	1			T2	1		T3	14		T41	5
valid_sources[0x36]	13117	1			T3	10		T9	6		T10	2
valid_sources[0x37]	17456	1			T3	7		T9	4		T4	4
valid_sources[0x38]	11528	1			T3	10		T9	5		T4	2
valid_sources[0x39]	12421	1			T3	14		T4	2		T15	1
valid_sources[0x3a]	9699	1			T3	18		T4	1		T10	3
valid_sources[0x3b]	17611	1			T3	9		T9	8		T41	5
valid_sources[0x3c]	24617	1			T3	11		T9	1		T18	150
valid_sources[0x3d]	9954	1			T2	7		T3	11		T9	9
valid_sources[0x3e]	9697	1			T2	3		T3	13		T9	1
valid_sources[0x3f]	10286	1			T3	10		T9	13		T4	3
valid_sources[0x40]	9831	1			T3	6		T10	3		T15	1
valid_sources[0x41]	13685	1			T3	14		T9	5		T11	1
valid_sources[0x42]	8962	1			T3	20		T9	4		T10	1
valid_sources[0x43]	9504	1			T3	18		T9	4		T4	1
valid_sources[0x44]	9486	1			T3	24		T10	6		T15	1
valid_sources[0x45]	9213	1			T2	5		T3	17		T4	1
valid_sources[0x46]	9575	1			T2	2		T3	14		T4	2
valid_sources[0x47]	11530	1			T2	7		T3	15		T9	11
valid_sources[0x48]	9609	1			T2	3		T3	14		T9	10
valid_sources[0x49]	9415	1			T3	18		T9	1		T4	1
valid_sources[0x4a]	9734	1			T3	16		T9	13		T4	3
valid_sources[0x4b]	9941	1			T3	14		T4	6		T12	7
valid_sources[0x4c]	10918	1			T3	11		T10	10		T15	1
valid_sources[0x4d]	13447	1			T3	7		T9	7		T4	2
valid_sources[0x4e]	11571	1			T3	17		T9	6		T4	7
valid_sources[0x4f]	9209	1			T3	17		T9	6		T4	2
valid_sources[0x50]	9420	1			T3	11		T9	6		T12	3
valid_sources[0x51]	9149	1			T3	14		T9	6		T4	2
valid_sources[0x52]	11322	1			T3	12		T9	7		T4	1
valid_sources[0x53]	9259	1			T3	16		T9	3		T4	8
valid_sources[0x54]	9221	1			T2	2		T3	12		T4	1
valid_sources[0x55]	9732	1			T3	7		T9	8		T4	3
valid_sources[0x56]	11427	1			T3	12		T4	5		T10	1
valid_sources[0x57]	9566	1			T3	19		T9	10		T4	1
valid_sources[0x58]	10453	1			T3	10		T9	11		T10	1
valid_sources[0x59]	9096	1			T3	12		T4	2		T10	2
valid_sources[0x5a]	61101	1			T3	23		T9	31		T4	4
valid_sources[0x5b]	9465	1			T3	15		T9	5		T4	1
valid_sources[0x5c]	9668	1			T3	13		T4	1		T10	2
valid_sources[0x5d]	12590	1			T3	11		T4	1		T15	2
valid_sources[0x5e]	9655	1			T3	14		T9	16		T15	3
valid_sources[0x5f]	9556	1			T2	5		T3	22		T9	11
valid_sources[0x60]	9820	1			T3	12		T9	5		T41	1
valid_sources[0x61]	10017	1			T3	12		T4	1		T15	1
valid_sources[0x62]	9242	1			T3	11		T9	19		T4	2
valid_sources[0x63]	9420	1			T3	12		T9	8		T4	4
valid_sources[0x64]	10937	1			T3	16		T9	14		T4	2
valid_sources[0x65]	26240	1			T3	4		T9	2		T11	1
valid_sources[0x66]	9961	1			T3	14		T9	7		T4	1
valid_sources[0x67]	9731	1			T3	21		T4	1		T10	4
valid_sources[0x68]	10194	1			T3	11		T10	3		T18	140
valid_sources[0x69]	9407	1			T3	11		T9	2		T4	3
valid_sources[0x6a]	9794	1			T3	12		T9	24		T4	3
valid_sources[0x6b]	9564	1			T3	15		T9	4		T4	5
valid_sources[0x6c]	9353	1			T3	10		T9	10		T4	2
valid_sources[0x6d]	11325	1			T2	1		T3	11		T9	10
valid_sources[0x6e]	9023	1			T3	7		T9	5		T41	4
valid_sources[0x6f]	18175	1			T3	18		T9	1		T4	2
valid_sources[0x70]	10491	1			T2	7		T3	22		T9	5
valid_sources[0x71]	9166	1			T3	16		T9	9		T4	1
valid_sources[0x72]	9742	1			T3	8		T10	1		T18	142
valid_sources[0x73]	11117	1			T3	14		T9	12		T10	4
valid_sources[0x74]	9623	1			T2	11		T3	11		T9	8
valid_sources[0x75]	13758	1			T3	19		T9	7		T4	4
valid_sources[0x76]	9987	1			T3	12		T9	15		T4	1
valid_sources[0x77]	12036	1			T3	6		T9	14		T4	4
valid_sources[0x78]	11200	1			T3	15		T9	7		T4	3
valid_sources[0x79]	11384	1			T3	15		T4	1		T10	1
valid_sources[0x7a]	9788	1			T3	9		T9	8		T41	1
valid_sources[0x7b]	9631	1			T3	15		T9	17		T4	2
valid_sources[0x7c]	9403	1			T3	16		T4	2		T10	3
valid_sources[0x7d]	10255	1			T3	12		T15	1		T41	2
valid_sources[0x7e]	9860	1			T3	18		T9	14		T4	2
valid_sources[0x7f]	9411	1			T3	19		T9	6		T4	1
valid_sources[0x80]	9760	1			T3	23		T9	6		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1216742

1

T2

108

T3

1408

T9

737

values[0x0]

all_enables

biggest_size

141319

1

T2

59

T3

232

T9

228

values[0x1]

all_enables

biggest_size

140882

1

T2

71

T3

198

T9

259