SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
93.47 | 100.00 | 83.10 | 99.89 | 100.00 | 84.38 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.00 | 98.87 | 94.19 | 100.00 | 98.63 | 93.33 | u_lc_ctrl_fsm |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.00 | 98.87 | 94.19 | 100.00 | 98.63 | 93.33 | u_lc_ctrl_fsm |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.00 | 98.87 | 94.19 | 100.00 | 98.63 | 93.33 | u_lc_ctrl_fsm |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.00 | 98.87 | 94.19 | 100.00 | 98.63 | 93.33 | u_lc_ctrl_fsm |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.00 | 98.87 | 94.19 | 100.00 | 98.63 | 93.33 | u_lc_ctrl_fsm |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.00 | 98.87 | 94.19 | 100.00 | 98.63 | 93.33 | u_lc_ctrl_fsm |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 4 | 4 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 4 | 4 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 9 | 9 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 8 | 8 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 5698 | 5698 | 0 | 0 |
OutputsKnown_A | 649268423 | 622030079 | 0 | 0 |
gen_flops.OutputDelay_A | 278201348 | 266083497 | 0 | 7209 |
gen_no_flops.OutputDelay_A | 371067075 | 355480088 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 5698 | 5698 | 0 | 0 |
T1 | 7 | 7 | 0 | 0 |
T2 | 7 | 7 | 0 | 0 |
T3 | 7 | 7 | 0 | 0 |
T4 | 7 | 7 | 0 | 0 |
T5 | 7 | 7 | 0 | 0 |
T9 | 7 | 7 | 0 | 0 |
T10 | 7 | 7 | 0 | 0 |
T11 | 7 | 7 | 0 | 0 |
T12 | 7 | 7 | 0 | 0 |
T13 | 7 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 649268423 | 622030079 | 0 | 0 |
T1 | 1075137 | 1029777 | 0 | 0 |
T2 | 65989 | 56007 | 0 | 0 |
T3 | 262836 | 229201 | 0 | 0 |
T4 | 963004 | 962647 | 0 | 0 |
T5 | 1368969 | 1337504 | 0 | 0 |
T9 | 354151 | 316575 | 0 | 0 |
T10 | 46879 | 40635 | 0 | 0 |
T11 | 10241 | 9653 | 0 | 0 |
T12 | 23002 | 18543 | 0 | 0 |
T13 | 357301 | 347893 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 278201348 | 266083497 | 0 | 7209 |
T1 | 460773 | 440523 | 0 | 9 |
T2 | 28281 | 23823 | 0 | 9 |
T3 | 112644 | 97653 | 0 | 9 |
T4 | 412716 | 412554 | 0 | 9 |
T5 | 586701 | 572658 | 0 | 9 |
T9 | 151779 | 135036 | 0 | 9 |
T10 | 20091 | 17307 | 0 | 9 |
T11 | 4389 | 4128 | 0 | 9 |
T12 | 9858 | 7875 | 0 | 9 |
T13 | 153129 | 148935 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 371067075 | 355480088 | 0 | 0 |
T1 | 614364 | 588444 | 0 | 0 |
T2 | 37708 | 32004 | 0 | 0 |
T3 | 150192 | 130972 | 0 | 0 |
T4 | 550288 | 550084 | 0 | 0 |
T5 | 782268 | 764288 | 0 | 0 |
T9 | 202372 | 180900 | 0 | 0 |
T10 | 26788 | 23220 | 0 | 0 |
T11 | 5852 | 5516 | 0 | 0 |
T12 | 13144 | 10596 | 0 | 0 |
T13 | 204172 | 198796 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 814 | 814 | 0 | 0 |
OutputsKnown_A | 93072220 | 89135182 | 0 | 0 |
gen_no_flops.OutputDelay_A | 93072220 | 89135182 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 814 | 814 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 93072220 | 89135182 | 0 | 0 |
T1 | 153591 | 147111 | 0 | 0 |
T2 | 9427 | 8001 | 0 | 0 |
T3 | 37548 | 32743 | 0 | 0 |
T4 | 137572 | 137521 | 0 | 0 |
T5 | 195567 | 191072 | 0 | 0 |
T9 | 50593 | 45225 | 0 | 0 |
T10 | 6697 | 5805 | 0 | 0 |
T11 | 1463 | 1379 | 0 | 0 |
T12 | 3286 | 2649 | 0 | 0 |
T13 | 51043 | 49699 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 93072220 | 89135182 | 0 | 0 |
T1 | 153591 | 147111 | 0 | 0 |
T2 | 9427 | 8001 | 0 | 0 |
T3 | 37548 | 32743 | 0 | 0 |
T4 | 137572 | 137521 | 0 | 0 |
T5 | 195567 | 191072 | 0 | 0 |
T9 | 50593 | 45225 | 0 | 0 |
T10 | 6697 | 5805 | 0 | 0 |
T11 | 1463 | 1379 | 0 | 0 |
T12 | 3286 | 2649 | 0 | 0 |
T13 | 51043 | 49699 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 814 | 814 | 0 | 0 |
OutputsKnown_A | 92816650 | 88931557 | 0 | 0 |
gen_flops.OutputDelay_A | 92816650 | 88776007 | 0 | 2421 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 814 | 814 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92816650 | 88931557 | 0 | 0 |
T1 | 153591 | 147111 | 0 | 0 |
T2 | 9427 | 8001 | 0 | 0 |
T3 | 37548 | 32743 | 0 | 0 |
T4 | 137572 | 137521 | 0 | 0 |
T5 | 195567 | 191072 | 0 | 0 |
T9 | 50593 | 45225 | 0 | 0 |
T10 | 6697 | 5805 | 0 | 0 |
T11 | 1463 | 1379 | 0 | 0 |
T12 | 3286 | 2649 | 0 | 0 |
T13 | 51043 | 49699 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92816650 | 88776007 | 0 | 2421 |
T1 | 153591 | 146841 | 0 | 3 |
T2 | 9427 | 7941 | 0 | 3 |
T3 | 37548 | 32551 | 0 | 3 |
T4 | 137572 | 137518 | 0 | 3 |
T5 | 195567 | 190886 | 0 | 3 |
T9 | 50593 | 45012 | 0 | 3 |
T10 | 6697 | 5769 | 0 | 3 |
T11 | 1463 | 1376 | 0 | 3 |
T12 | 3286 | 2625 | 0 | 3 |
T13 | 51043 | 49645 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 814 | 814 | 0 | 0 |
OutputsKnown_A | 92692349 | 88809217 | 0 | 0 |
gen_no_flops.OutputDelay_A | 92692349 | 88809217 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 814 | 814 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92692349 | 88809217 | 0 | 0 |
T1 | 153591 | 147111 | 0 | 0 |
T2 | 9427 | 8001 | 0 | 0 |
T3 | 37548 | 32743 | 0 | 0 |
T4 | 137572 | 137521 | 0 | 0 |
T5 | 195567 | 191072 | 0 | 0 |
T9 | 50593 | 45225 | 0 | 0 |
T10 | 6697 | 5805 | 0 | 0 |
T11 | 1463 | 1379 | 0 | 0 |
T12 | 3286 | 2649 | 0 | 0 |
T13 | 51043 | 49699 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92692349 | 88809217 | 0 | 0 |
T1 | 153591 | 147111 | 0 | 0 |
T2 | 9427 | 8001 | 0 | 0 |
T3 | 37548 | 32743 | 0 | 0 |
T4 | 137572 | 137521 | 0 | 0 |
T5 | 195567 | 191072 | 0 | 0 |
T9 | 50593 | 45225 | 0 | 0 |
T10 | 6697 | 5805 | 0 | 0 |
T11 | 1463 | 1379 | 0 | 0 |
T12 | 3286 | 2649 | 0 | 0 |
T13 | 51043 | 49699 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 814 | 814 | 0 | 0 |
OutputsKnown_A | 92644374 | 88759525 | 0 | 0 |
gen_no_flops.OutputDelay_A | 92644374 | 88759525 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 814 | 814 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92644374 | 88759525 | 0 | 0 |
T1 | 153591 | 147111 | 0 | 0 |
T2 | 9427 | 8001 | 0 | 0 |
T3 | 37548 | 32743 | 0 | 0 |
T4 | 137572 | 137521 | 0 | 0 |
T5 | 195567 | 191072 | 0 | 0 |
T9 | 50593 | 45225 | 0 | 0 |
T10 | 6697 | 5805 | 0 | 0 |
T11 | 1463 | 1379 | 0 | 0 |
T12 | 3286 | 2649 | 0 | 0 |
T13 | 51043 | 49699 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92644374 | 88759525 | 0 | 0 |
T1 | 153591 | 147111 | 0 | 0 |
T2 | 9427 | 8001 | 0 | 0 |
T3 | 37548 | 32743 | 0 | 0 |
T4 | 137572 | 137521 | 0 | 0 |
T5 | 195567 | 191072 | 0 | 0 |
T9 | 50593 | 45225 | 0 | 0 |
T10 | 6697 | 5805 | 0 | 0 |
T11 | 1463 | 1379 | 0 | 0 |
T12 | 3286 | 2649 | 0 | 0 |
T13 | 51043 | 49699 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 9 | 9 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 8 | 8 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 814 | 814 | 0 | 0 |
OutputsKnown_A | 92658132 | 88776164 | 0 | 0 |
gen_no_flops.OutputDelay_A | 92658132 | 88776164 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 814 | 814 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92658132 | 88776164 | 0 | 0 |
T1 | 153591 | 147111 | 0 | 0 |
T2 | 9427 | 8001 | 0 | 0 |
T3 | 37548 | 32743 | 0 | 0 |
T4 | 137572 | 137521 | 0 | 0 |
T5 | 195567 | 191072 | 0 | 0 |
T9 | 50593 | 45225 | 0 | 0 |
T10 | 6697 | 5805 | 0 | 0 |
T11 | 1463 | 1379 | 0 | 0 |
T12 | 3286 | 2649 | 0 | 0 |
T13 | 51043 | 49699 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92658132 | 88776164 | 0 | 0 |
T1 | 153591 | 147111 | 0 | 0 |
T2 | 9427 | 8001 | 0 | 0 |
T3 | 37548 | 32743 | 0 | 0 |
T4 | 137572 | 137521 | 0 | 0 |
T5 | 195567 | 191072 | 0 | 0 |
T9 | 50593 | 45225 | 0 | 0 |
T10 | 6697 | 5805 | 0 | 0 |
T11 | 1463 | 1379 | 0 | 0 |
T12 | 3286 | 2649 | 0 | 0 |
T13 | 51043 | 49699 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 814 | 814 | 0 | 0 |
OutputsKnown_A | 92692349 | 88809217 | 0 | 0 |
gen_flops.OutputDelay_A | 92692349 | 88653745 | 0 | 2394 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 814 | 814 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92692349 | 88809217 | 0 | 0 |
T1 | 153591 | 147111 | 0 | 0 |
T2 | 9427 | 8001 | 0 | 0 |
T3 | 37548 | 32743 | 0 | 0 |
T4 | 137572 | 137521 | 0 | 0 |
T5 | 195567 | 191072 | 0 | 0 |
T9 | 50593 | 45225 | 0 | 0 |
T10 | 6697 | 5805 | 0 | 0 |
T11 | 1463 | 1379 | 0 | 0 |
T12 | 3286 | 2649 | 0 | 0 |
T13 | 51043 | 49699 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92692349 | 88653745 | 0 | 2394 |
T1 | 153591 | 146841 | 0 | 3 |
T2 | 9427 | 7941 | 0 | 3 |
T3 | 37548 | 32551 | 0 | 3 |
T4 | 137572 | 137518 | 0 | 3 |
T5 | 195567 | 190886 | 0 | 3 |
T9 | 50593 | 45012 | 0 | 3 |
T10 | 6697 | 5769 | 0 | 3 |
T11 | 1463 | 1376 | 0 | 3 |
T12 | 3286 | 2625 | 0 | 3 |
T13 | 51043 | 49645 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 814 | 814 | 0 | 0 |
OutputsKnown_A | 92692349 | 88809217 | 0 | 0 |
gen_flops.OutputDelay_A | 92692349 | 88653745 | 0 | 2394 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 814 | 814 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92692349 | 88809217 | 0 | 0 |
T1 | 153591 | 147111 | 0 | 0 |
T2 | 9427 | 8001 | 0 | 0 |
T3 | 37548 | 32743 | 0 | 0 |
T4 | 137572 | 137521 | 0 | 0 |
T5 | 195567 | 191072 | 0 | 0 |
T9 | 50593 | 45225 | 0 | 0 |
T10 | 6697 | 5805 | 0 | 0 |
T11 | 1463 | 1379 | 0 | 0 |
T12 | 3286 | 2649 | 0 | 0 |
T13 | 51043 | 49699 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92692349 | 88653745 | 0 | 2394 |
T1 | 153591 | 146841 | 0 | 3 |
T2 | 9427 | 7941 | 0 | 3 |
T3 | 37548 | 32551 | 0 | 3 |
T4 | 137572 | 137518 | 0 | 3 |
T5 | 195567 | 190886 | 0 | 3 |
T9 | 50593 | 45012 | 0 | 3 |
T10 | 6697 | 5769 | 0 | 3 |
T11 | 1463 | 1376 | 0 | 3 |
T12 | 3286 | 2625 | 0 | 3 |
T13 | 51043 | 49645 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |