Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	95290172	15036	0	0
claim_transition_if_regwen_rd_A	95290172	1645	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95290172	15036	0	0
T45	181280	5	0	0
T50	287952	0	0	0
T62	33533	0	0	0
T93	0	11	0	0
T105	0	3	0	0
T142	0	1	0	0
T143	0	2	0	0
T144	0	2	0	0
T145	0	5	0	0
T146	0	3	0	0
T147	0	12	0	0
T148	0	6	0	0
T149	6888	0	0	0
T150	20748	0	0	0
T151	66712	0	0	0
T152	45366	0	0	0
T153	24343	0	0	0
T154	29498	0	0	0
T155	38835	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95290172	1645	0	0
T50	287952	5	0	0
T62	33533	0	0	0
T109	0	41	0	0
T133	0	48	0	0
T145	0	5	0	0
T149	6888	0	0	0
T150	20748	0	0	0
T151	66712	0	0	0
T152	45366	0	0	0
T153	24343	0	0	0
T154	29498	0	0	0
T155	38835	0	0	0
T156	0	13	0	0
T157	0	455	0	0
T158	0	27	0	0
T159	0	33	0	0
T160	0	25	0	0
T161	0	7	0	0
T162	25073	0	0	0