Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1925336	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2143979

1

T1

970

T2

84

T3

1164

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3719296	1			T1	1058		T2	68		T3	1317
values[0x0]	174716	1			T1	260		T2	21		T3	300
values[0x1]	175303	1			T1	284		T2	27		T3	276

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1530371	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2538944

1

T1

1098

T2

89

T3

1328

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12010	1			T3	7		T4	1		T14	3
valid_sources[0x01]	19176	1			T3	7		T15	7		T16	1
valid_sources[0x02]	9994	1			T3	10		T15	5		T16	5
valid_sources[0x03]	9752	1			T3	4		T14	1		T15	4
valid_sources[0x04]	10410	1			T3	7		T14	1		T15	9
valid_sources[0x05]	10358	1			T3	4		T14	1		T15	7
valid_sources[0x06]	10347	1			T3	5		T4	1		T15	7
valid_sources[0x07]	10153	1			T3	7		T14	1		T15	2
valid_sources[0x08]	10692	1			T3	9		T14	3		T15	3
valid_sources[0x09]	10003	1			T3	8		T14	1		T15	3
valid_sources[0x0a]	10404	1			T3	10		T14	2		T15	3
valid_sources[0x0b]	12550	1			T3	6		T15	3		T16	2
valid_sources[0x0c]	9795	1			T3	6		T14	1		T15	7
valid_sources[0x0d]	31886	1			T3	9		T14	2		T15	4
valid_sources[0x0e]	10454	1			T3	6		T14	2		T15	3
valid_sources[0x0f]	38959	1			T3	9		T15	8		T16	3
valid_sources[0x10]	11459	1			T3	10		T11	1		T4	1
valid_sources[0x11]	10181	1			T3	9		T4	1		T14	1
valid_sources[0x12]	10029	1			T3	10		T11	2		T4	1
valid_sources[0x13]	12482	1			T3	5		T14	2		T15	3
valid_sources[0x14]	10123	1			T3	4		T15	4		T16	2
valid_sources[0x15]	10030	1			T3	5		T14	1		T15	2
valid_sources[0x16]	9895	1			T3	6		T15	6		T43	4
valid_sources[0x17]	20345	1			T3	10		T4	2		T14	1
valid_sources[0x18]	10302	1			T3	11		T15	3		T16	4
valid_sources[0x19]	14200	1			T3	6		T15	4		T16	4
valid_sources[0x1a]	11322	1			T3	8		T14	1		T6	1
valid_sources[0x1b]	11445	1			T3	3		T6	2		T15	5
valid_sources[0x1c]	9738	1			T3	6		T11	2		T15	4
valid_sources[0x1d]	10877	1			T3	9		T14	2		T15	3
valid_sources[0x1e]	11924	1			T3	4		T15	2		T16	1
valid_sources[0x1f]	10367	1			T3	6		T15	4		T16	6
valid_sources[0x20]	10329	1			T14	1		T6	6		T15	2
valid_sources[0x21]	9452	1			T3	11		T6	1		T15	8
valid_sources[0x22]	21516	1			T3	9		T4	1		T14	2
valid_sources[0x23]	11137	1			T3	3		T14	5		T15	5
valid_sources[0x24]	10412	1			T3	7		T14	1		T15	2
valid_sources[0x25]	10221	1			T3	6		T4	1		T15	3
valid_sources[0x26]	17698	1			T3	12		T15	5		T16	6
valid_sources[0x27]	10062	1			T3	7		T14	1		T6	2
valid_sources[0x28]	9973	1			T3	11		T4	1		T14	1
valid_sources[0x29]	10390	1			T3	3		T15	3		T16	2
valid_sources[0x2a]	10011	1			T3	13		T15	8		T16	2
valid_sources[0x2b]	12628	1			T3	8		T4	1		T14	3
valid_sources[0x2c]	11646	1			T3	11		T4	1		T15	4
valid_sources[0x2d]	10221	1			T3	10		T14	1		T15	4
valid_sources[0x2e]	9948	1			T3	9		T11	1		T14	4
valid_sources[0x2f]	9990	1			T3	7		T14	2		T15	4
valid_sources[0x30]	54635	1			T3	4		T11	1		T14	1
valid_sources[0x31]	11428	1			T3	6		T11	1		T4	2
valid_sources[0x32]	9684	1			T3	13		T14	5		T15	3
valid_sources[0x33]	11294	1			T3	7		T14	1		T15	2
valid_sources[0x34]	55711	1			T3	8		T4	1		T14	1
valid_sources[0x35]	10250	1			T3	7		T4	1		T14	7
valid_sources[0x36]	10167	1			T3	9		T4	3		T14	1
valid_sources[0x37]	10416	1			T3	9		T13	20		T14	2
valid_sources[0x38]	12811	1			T3	7		T4	1		T14	1
valid_sources[0x39]	12921	1			T3	9		T4	1		T15	1
valid_sources[0x3a]	11376	1			T3	10		T14	10		T43	6
valid_sources[0x3b]	9976	1			T3	6		T14	4		T15	3
valid_sources[0x3c]	10651	1			T3	6		T15	2		T16	4
valid_sources[0x3d]	10297	1			T3	8		T4	1		T15	4
valid_sources[0x3e]	27086	1			T3	6		T15	3		T16	4
valid_sources[0x3f]	54867	1			T3	8		T11	1		T14	2
valid_sources[0x40]	10327	1			T3	8		T14	1		T15	3
valid_sources[0x41]	10660	1			T3	10		T15	4		T16	8
valid_sources[0x42]	10005	1			T3	13		T15	3		T16	4
valid_sources[0x43]	169195	1			T3	8		T15	6		T16	3
valid_sources[0x44]	9831	1			T3	8		T15	2		T16	1
valid_sources[0x45]	28709	1			T3	9		T11	1		T14	1
valid_sources[0x46]	10649	1			T3	10		T15	7		T16	4
valid_sources[0x47]	10317	1			T3	13		T14	4		T6	1
valid_sources[0x48]	11219	1			T3	4		T14	10		T15	2
valid_sources[0x49]	9707	1			T3	9		T15	3		T16	4
valid_sources[0x4a]	52484	1			T3	4		T14	2		T15	6
valid_sources[0x4b]	10568	1			T3	7		T4	1		T14	2
valid_sources[0x4c]	10269	1			T3	5		T15	4		T16	2
valid_sources[0x4d]	10014	1			T3	8		T14	3		T15	3
valid_sources[0x4e]	11721	1			T3	7		T15	1		T16	6
valid_sources[0x4f]	11075	1			T3	7		T14	1		T15	4
valid_sources[0x50]	9880	1			T3	11		T14	1		T6	1
valid_sources[0x51]	44200	1			T3	7		T14	2		T15	6
valid_sources[0x52]	10191	1			T3	7		T14	4		T15	3
valid_sources[0x53]	10057	1			T3	14		T6	1		T15	5
valid_sources[0x54]	9985	1			T3	4		T16	2		T43	4
valid_sources[0x55]	10784	1			T2	116		T3	12		T14	4
valid_sources[0x56]	10257	1			T3	10		T6	2		T15	2
valid_sources[0x57]	38783	1			T3	9		T15	4		T16	6
valid_sources[0x58]	10369	1			T3	9		T4	1		T15	2
valid_sources[0x59]	9954	1			T3	9		T11	1		T14	3
valid_sources[0x5a]	11966	1			T3	4		T4	1		T15	6
valid_sources[0x5b]	16805	1			T3	3		T11	1		T14	2
valid_sources[0x5c]	10042	1			T3	4		T15	1		T16	1
valid_sources[0x5d]	10056	1			T3	7		T14	1		T15	4
valid_sources[0x5e]	10165	1			T3	9		T14	3		T15	3
valid_sources[0x5f]	10184	1			T3	4		T15	4		T16	4
valid_sources[0x60]	10447	1			T3	13		T4	1		T14	1
valid_sources[0x61]	10257	1			T3	3		T4	1		T14	2
valid_sources[0x62]	10288	1			T3	10		T14	1		T15	10
valid_sources[0x63]	10146	1			T3	5		T14	1		T15	5
valid_sources[0x64]	11518	1			T3	6		T6	3		T15	4
valid_sources[0x65]	23574	1			T3	4		T14	1		T16	2
valid_sources[0x66]	11261	1			T3	11		T15	5		T16	1
valid_sources[0x67]	10381	1			T3	7		T14	1		T16	5
valid_sources[0x68]	9921	1			T3	11		T6	1		T15	11
valid_sources[0x69]	10948	1			T3	6		T14	2		T15	6
valid_sources[0x6a]	18496	1			T3	12		T15	3		T16	1
valid_sources[0x6b]	10606	1			T3	6		T6	1		T15	2
valid_sources[0x6c]	9988	1			T3	12		T15	4		T16	5
valid_sources[0x6d]	11363	1			T3	5		T15	7		T16	3
valid_sources[0x6e]	12670	1			T3	9		T4	2		T14	1
valid_sources[0x6f]	102715	1			T3	8		T4	1		T15	9
valid_sources[0x70]	11895	1			T3	5		T12	1849		T4	1
valid_sources[0x71]	10303	1			T3	8		T11	2		T15	4
valid_sources[0x72]	10278	1			T3	4		T15	2		T16	3
valid_sources[0x73]	9849	1			T3	3		T16	2		T43	5
valid_sources[0x74]	12147	1			T3	8		T14	3		T15	1
valid_sources[0x75]	9843	1			T3	4		T4	1		T6	3
valid_sources[0x76]	172248	1			T3	7		T15	6		T16	4
valid_sources[0x77]	10423	1			T3	9		T15	5		T16	3
valid_sources[0x78]	10217	1			T3	6		T4	1		T6	1
valid_sources[0x79]	10273	1			T3	4		T11	1		T6	1
valid_sources[0x7a]	65957	1			T3	6		T15	3		T16	3
valid_sources[0x7b]	10560	1			T3	11		T15	3		T16	4
valid_sources[0x7c]	11110	1			T3	6		T14	1		T15	2
valid_sources[0x7d]	12124	1			T3	3		T15	6		T16	7
valid_sources[0x7e]	10183	1			T3	5		T15	2		T16	6
valid_sources[0x7f]	9946	1			T3	7		T14	4		T15	4
valid_sources[0x80]	11189	1			T3	2		T4	1		T14	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1842284

1

T1

494

T2

43

T3

656

values[0x0]

all_enables

biggest_size

151302

1

T1

226

T2

17

T3

267

values[0x1]

all_enables

biggest_size

150393

1

T1

250

T2

24

T3

241