Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	114123866	14168	0	0
claim_transition_if_regwen_rd_A	114123866	887	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114123866	14168	0	0
T7	28927	0	0	0
T21	396574	4	0	0
T22	268352	0	0	0
T30	36643	0	0	0
T39	1135	0	0	0
T40	41666	0	0	0
T44	5779	0	0	0
T47	0	16	0	0
T60	0	6	0	0
T61	0	12	0	0
T77	27214	0	0	0
T106	25229	0	0	0
T133	0	1	0	0
T134	0	7	0	0
T135	0	2	0	0
T136	0	3	0	0
T137	0	1	0	0
T138	0	17	0	0
T139	34963	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114123866	887	0	0
T60	0	9	0	0
T81	203994	2	0	0
T95	0	3	0	0
T97	0	30	0	0
T98	0	10	0	0
T104	0	24	0	0
T135	0	2	0	0
T137	0	5	0	0
T140	0	1	0	0
T141	0	9	0	0
T142	57165	0	0	0
T143	36774	0	0	0
T144	56421	0	0	0
T145	4946	0	0	0
T146	29141	0	0	0
T147	23711	0	0	0
T148	6337	0	0	0
T149	6835	0	0	0
T150	6535	0	0	0