Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1417318	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1641403

1

T1

11

T3

1

T4

925

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2712100	1			T4	749		T6	83107		T10	42
values[0x0]	173103	1			T1	13		T3	1		T4	327
values[0x1]	173518	1			T1	18		T3	4		T4	289

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1124557	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1934164

1

T1

14

T3

2

T4

1019

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10094	1			T4	12		T6	339		T11	65
valid_sources[0x01]	40741	1			T4	19		T6	309		T11	83
valid_sources[0x02]	9229	1			T4	8		T6	310		T11	70
valid_sources[0x03]	8970	1			T4	8		T6	316		T11	74
valid_sources[0x04]	103769	1			T4	2		T6	384		T11	62
valid_sources[0x05]	9373	1			T4	3		T6	324		T11	60
valid_sources[0x06]	10555	1			T6	328		T11	63		T13	3
valid_sources[0x07]	9962	1			T4	4		T6	318		T11	57
valid_sources[0x08]	8626	1			T4	8		T6	316		T11	73
valid_sources[0x09]	9016	1			T4	1		T6	345		T11	73
valid_sources[0x0a]	8692	1			T4	6		T6	352		T11	71
valid_sources[0x0b]	8763	1			T4	10		T6	363		T11	69
valid_sources[0x0c]	9964	1			T6	318		T11	91		T89	2
valid_sources[0x0d]	9630	1			T4	4		T6	331		T11	54
valid_sources[0x0e]	10979	1			T4	2		T6	339		T11	95
valid_sources[0x0f]	8463	1			T4	7		T6	336		T11	77
valid_sources[0x10]	8779	1			T4	1		T6	333		T11	67
valid_sources[0x11]	8760	1			T6	339		T11	70		T14	2
valid_sources[0x12]	8979	1			T4	14		T6	330		T11	72
valid_sources[0x13]	8331	1			T4	4		T6	333		T11	77
valid_sources[0x14]	8639	1			T4	5		T6	326		T11	85
valid_sources[0x15]	8689	1			T4	5		T6	336		T11	93
valid_sources[0x16]	10041	1			T4	3		T6	349		T11	65
valid_sources[0x17]	12899	1			T6	337		T11	81		T13	4
valid_sources[0x18]	54081	1			T4	4		T6	352		T11	64
valid_sources[0x19]	8776	1			T4	2		T6	354		T11	61
valid_sources[0x1a]	10969	1			T6	332		T11	67		T15	2
valid_sources[0x1b]	9242	1			T4	2		T6	345		T11	72
valid_sources[0x1c]	8709	1			T4	1		T6	314		T11	71
valid_sources[0x1d]	9342	1			T4	10		T6	337		T11	84
valid_sources[0x1e]	8988	1			T4	9		T6	311		T11	66
valid_sources[0x1f]	8950	1			T6	312		T11	54		T13	1
valid_sources[0x20]	8856	1			T4	24		T6	332		T11	75
valid_sources[0x21]	9424	1			T4	3		T6	325		T11	67
valid_sources[0x22]	8682	1			T4	2		T6	334		T11	81
valid_sources[0x23]	8602	1			T4	4		T6	311		T11	77
valid_sources[0x24]	9111	1			T4	6		T6	313		T11	73
valid_sources[0x25]	8271	1			T4	9		T6	341		T11	79
valid_sources[0x26]	8856	1			T4	9		T6	319		T11	78
valid_sources[0x27]	11213	1			T6	322		T11	79		T13	4
valid_sources[0x28]	8880	1			T4	3		T6	316		T11	64
valid_sources[0x29]	10318	1			T4	7		T6	341		T11	69
valid_sources[0x2a]	8706	1			T6	344		T11	62		T13	1
valid_sources[0x2b]	9004	1			T6	298		T11	84		T89	5
valid_sources[0x2c]	8494	1			T6	357		T11	67		T14	1
valid_sources[0x2d]	8779	1			T4	8		T6	321		T11	79
valid_sources[0x2e]	13032	1			T4	13		T6	343		T11	65
valid_sources[0x2f]	8631	1			T6	326		T11	64		T13	2
valid_sources[0x30]	8496	1			T4	15		T6	352		T11	75
valid_sources[0x31]	8474	1			T4	3		T6	315		T11	74
valid_sources[0x32]	8849	1			T4	5		T6	382		T11	83
valid_sources[0x33]	8547	1			T4	17		T6	356		T11	62
valid_sources[0x34]	11727	1			T4	2		T6	355		T11	76
valid_sources[0x35]	8275	1			T4	1		T6	351		T11	71
valid_sources[0x36]	8531	1			T4	8		T6	338		T11	74
valid_sources[0x37]	10209	1			T4	8		T6	355		T11	67
valid_sources[0x38]	8966	1			T4	9		T6	329		T11	53
valid_sources[0x39]	8696	1			T4	2		T6	358		T11	90
valid_sources[0x3a]	8783	1			T4	6		T6	346		T11	109
valid_sources[0x3b]	8735	1			T4	1		T6	307		T11	79
valid_sources[0x3c]	10179	1			T6	325		T11	74		T13	2
valid_sources[0x3d]	8735	1			T4	5		T6	340		T11	69
valid_sources[0x3e]	9225	1			T4	3		T6	352		T11	75
valid_sources[0x3f]	9051	1			T4	9		T6	345		T11	52
valid_sources[0x40]	8635	1			T4	3		T6	320		T11	82
valid_sources[0x41]	8727	1			T4	14		T6	335		T11	80
valid_sources[0x42]	8776	1			T4	12		T6	339		T11	78
valid_sources[0x43]	11277	1			T4	4		T6	314		T11	82
valid_sources[0x44]	31971	1			T4	1		T6	317		T11	62
valid_sources[0x45]	8815	1			T4	23		T6	350		T11	57
valid_sources[0x46]	9216	1			T4	5		T6	326		T11	75
valid_sources[0x47]	12217	1			T4	10		T6	356		T11	93
valid_sources[0x48]	8952	1			T4	3		T6	340		T11	68
valid_sources[0x49]	10094	1			T4	9		T6	324		T11	83
valid_sources[0x4a]	8772	1			T4	8		T6	346		T11	57
valid_sources[0x4b]	8894	1			T4	5		T6	318		T11	56
valid_sources[0x4c]	8430	1			T4	1		T6	302		T11	77
valid_sources[0x4d]	8864	1			T4	3		T6	332		T11	68
valid_sources[0x4e]	8425	1			T4	1		T6	331		T11	63
valid_sources[0x4f]	11156	1			T4	6		T6	322		T11	80
valid_sources[0x50]	8694	1			T4	2		T6	308		T11	74
valid_sources[0x51]	9008	1			T4	5		T6	344		T11	69
valid_sources[0x52]	8561	1			T4	6		T6	323		T11	48
valid_sources[0x53]	8618	1			T4	12		T6	337		T11	57
valid_sources[0x54]	9097	1			T4	2		T6	350		T11	67
valid_sources[0x55]	14959	1			T4	1		T6	320		T11	68
valid_sources[0x56]	8306	1			T4	18		T6	333		T11	57
valid_sources[0x57]	9319	1			T6	353		T11	65		T13	1
valid_sources[0x58]	9044	1			T4	8		T6	319		T11	71
valid_sources[0x59]	9831	1			T4	1		T6	353		T11	66
valid_sources[0x5a]	9074	1			T6	349		T11	81		T13	2
valid_sources[0x5b]	9764	1			T4	1		T6	324		T11	68
valid_sources[0x5c]	11307	1			T4	5		T6	304		T11	92
valid_sources[0x5d]	8524	1			T6	337		T11	82		T13	1
valid_sources[0x5e]	9158	1			T4	4		T6	343		T11	72
valid_sources[0x5f]	9431	1			T4	7		T6	292		T11	53
valid_sources[0x60]	8940	1			T4	9		T6	323		T11	82
valid_sources[0x61]	10435	1			T4	1		T6	344		T11	52
valid_sources[0x62]	11407	1			T4	2		T6	311		T11	74
valid_sources[0x63]	8931	1			T4	5		T6	358		T11	70
valid_sources[0x64]	8804	1			T4	6		T6	304		T11	73
valid_sources[0x65]	10356	1			T4	7		T6	353		T11	89
valid_sources[0x66]	8727	1			T4	3		T6	347		T11	85
valid_sources[0x67]	9295	1			T4	4		T6	332		T11	95
valid_sources[0x68]	8934	1			T4	10		T6	327		T11	62
valid_sources[0x69]	8750	1			T4	17		T6	322		T11	74
valid_sources[0x6a]	9639	1			T4	1		T6	331		T10	58
valid_sources[0x6b]	9143	1			T4	4		T6	318		T11	73
valid_sources[0x6c]	8734	1			T4	11		T6	337		T11	73
valid_sources[0x6d]	13177	1			T4	12		T6	339		T11	83
valid_sources[0x6e]	8153	1			T4	13		T6	342		T11	63
valid_sources[0x6f]	9198	1			T4	15		T6	342		T11	81
valid_sources[0x70]	8177	1			T6	340		T11	81		T13	3
valid_sources[0x71]	8176	1			T4	2		T6	319		T11	88
valid_sources[0x72]	8634	1			T6	331		T11	83		T14	1
valid_sources[0x73]	8636	1			T6	336		T11	63		T13	2
valid_sources[0x74]	8932	1			T4	2		T6	303		T11	53
valid_sources[0x75]	8716	1			T4	12		T6	317		T11	89
valid_sources[0x76]	8963	1			T4	15		T6	294		T11	69
valid_sources[0x77]	9335	1			T4	1		T6	355		T11	53
valid_sources[0x78]	8540	1			T4	2		T6	334		T11	75
valid_sources[0x79]	10088	1			T6	332		T11	59		T13	2
valid_sources[0x7a]	9499	1			T4	1		T6	334		T11	46
valid_sources[0x7b]	8722	1			T4	5		T6	337		T11	92
valid_sources[0x7c]	9016	1			T4	6		T6	349		T11	91
valid_sources[0x7d]	8405	1			T4	7		T6	336		T11	82
valid_sources[0x7e]	8318	1			T4	7		T6	334		T11	60
valid_sources[0x7f]	8969	1			T4	1		T6	341		T11	91
valid_sources[0x80]	13112	1			T4	10		T6	336		T11	94

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1342404

1

T4

382

T6

41504

T10

1

values[0x0]

all_enables

biggest_size

150157

1

T1

7

T4

290

T6

752

values[0x1]

all_enables

biggest_size

148842

1

T1

4

T3

1

T4

253