Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	106922487	14493	0	0
claim_transition_if_regwen_rd_A	106922487	1757	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106922487	14493	0	0
T8	19243	0	0	0
T9	6979	0	0	0
T28	429679	6	0	0
T29	1381	0	0	0
T30	181559	0	0	0
T31	13141	0	0	0
T32	26693	0	0	0
T33	1775	0	0	0
T34	36570	0	0	0
T35	22143	0	0	0
T46	0	4	0	0
T47	0	4	0	0
T61	0	2	0	0
T87	0	1	0	0
T93	0	1	0	0
T131	0	1	0	0
T132	0	15	0	0
T133	0	5	0	0
T134	0	1	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106922487	1757	0	0
T21	30296	0	0	0
T47	0	13	0	0
T51	71972	0	0	0
T87	236093	9	0	0
T102	0	55	0	0
T126	0	23	0	0
T127	0	415	0	0
T135	0	1	0	0
T136	0	6	0	0
T137	0	74	0	0
T138	0	16	0	0
T139	0	24	0	0
T140	27546	0	0	0
T141	7661	0	0	0
T142	26907	0	0	0
T143	5493	0	0	0
T144	1199	0	0	0
T145	118758	0	0	0
T146	48963	0	0	0