Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1720257	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1951730

1

T3

26

T4

6675

T9

282

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3310844	1			T3	25		T4	5323		T9	373
values[0x0]	180724	1			T3	13		T4	2574		T9	167
values[0x1]	180419	1			T3	8		T4	2516		T9	204

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1367184	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2304803

1

T3

30

T4

7548

T9

352

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11876	1			T4	61		T9	3		T10	16
valid_sources[0x01]	10997	1			T3	2		T4	32		T9	7
valid_sources[0x02]	10849	1			T4	43		T9	4		T10	9
valid_sources[0x03]	11357	1			T4	30		T9	4		T10	5
valid_sources[0x04]	11161	1			T4	28		T9	2		T10	11
valid_sources[0x05]	12513	1			T4	32		T10	5		T13	2
valid_sources[0x06]	12112	1			T4	67		T9	10		T10	2
valid_sources[0x07]	11454	1			T4	42		T9	4		T10	17
valid_sources[0x08]	10734	1			T4	73		T9	5		T10	5
valid_sources[0x09]	11057	1			T3	2		T4	38		T10	12
valid_sources[0x0a]	10784	1			T4	37		T9	6		T10	4
valid_sources[0x0b]	11408	1			T3	2		T4	31		T10	12
valid_sources[0x0c]	11037	1			T3	1		T4	41		T9	9
valid_sources[0x0d]	10630	1			T4	42		T10	9		T13	6
valid_sources[0x0e]	11600	1			T3	1		T4	47		T9	1
valid_sources[0x0f]	11996	1			T4	65		T9	2		T10	18
valid_sources[0x10]	10739	1			T4	46		T9	5		T10	12
valid_sources[0x11]	57221	1			T4	12		T9	6		T10	6
valid_sources[0x12]	10893	1			T4	44		T9	7		T10	5
valid_sources[0x13]	12449	1			T4	48		T9	5		T10	6
valid_sources[0x14]	13598	1			T4	62		T10	9		T13	3
valid_sources[0x15]	11410	1			T3	1		T4	90		T9	5
valid_sources[0x16]	15907	1			T3	1		T4	44		T9	3
valid_sources[0x17]	10561	1			T4	9		T9	4		T10	8
valid_sources[0x18]	11777	1			T4	57		T10	8		T13	4
valid_sources[0x19]	14223	1			T4	40		T10	11		T13	1
valid_sources[0x1a]	14018	1			T4	65		T9	10		T10	4
valid_sources[0x1b]	11006	1			T4	41		T9	8		T10	10
valid_sources[0x1c]	11955	1			T4	51		T9	2		T10	4
valid_sources[0x1d]	11757	1			T3	1		T4	67		T9	6
valid_sources[0x1e]	11158	1			T4	47		T9	6		T10	9
valid_sources[0x1f]	20120	1			T4	38		T10	8		T13	2
valid_sources[0x20]	95299	1			T4	51		T9	6		T10	7
valid_sources[0x21]	11862	1			T4	38		T9	1		T10	10
valid_sources[0x22]	12056	1			T4	39		T10	6		T13	2
valid_sources[0x23]	11619	1			T3	1		T4	37		T9	7
valid_sources[0x24]	10859	1			T4	26		T9	4		T10	5
valid_sources[0x25]	10860	1			T4	46		T9	2		T10	5
valid_sources[0x26]	11149	1			T4	37		T10	2		T13	1
valid_sources[0x27]	13416	1			T4	13		T9	6		T10	7
valid_sources[0x28]	10780	1			T4	45		T10	9		T13	2
valid_sources[0x29]	13016	1			T4	39		T9	1		T10	11
valid_sources[0x2a]	11542	1			T4	40		T9	2		T10	6
valid_sources[0x2b]	11644	1			T4	30		T10	7		T13	1
valid_sources[0x2c]	11787	1			T4	23		T9	1		T10	9
valid_sources[0x2d]	10853	1			T4	43		T9	4		T10	3
valid_sources[0x2e]	10751	1			T4	41		T10	7		T11	2
valid_sources[0x2f]	25795	1			T4	52		T9	3		T10	7
valid_sources[0x30]	10705	1			T4	40		T9	1		T10	11
valid_sources[0x31]	12789	1			T4	34		T9	1		T10	6
valid_sources[0x32]	83923	1			T4	44		T9	7		T10	10
valid_sources[0x33]	80841	1			T4	40		T9	2		T10	12
valid_sources[0x34]	11042	1			T4	36		T9	7		T10	9
valid_sources[0x35]	11076	1			T4	32		T9	10		T10	14
valid_sources[0x36]	11123	1			T4	58		T9	4		T10	2
valid_sources[0x37]	11576	1			T4	40		T9	2		T10	5
valid_sources[0x38]	11487	1			T4	76		T9	4		T10	10
valid_sources[0x39]	11603	1			T4	51		T9	10		T10	10
valid_sources[0x3a]	10909	1			T4	24		T9	1		T10	7
valid_sources[0x3b]	13103	1			T4	56		T10	5		T13	3
valid_sources[0x3c]	11458	1			T4	32		T10	10		T13	4
valid_sources[0x3d]	12457	1			T4	32		T9	2		T10	11
valid_sources[0x3e]	11371	1			T4	17		T9	8		T10	3
valid_sources[0x3f]	23110	1			T3	1		T4	23		T9	2
valid_sources[0x40]	25297	1			T3	1		T4	39		T9	3
valid_sources[0x41]	11086	1			T4	61		T9	4		T10	6
valid_sources[0x42]	17911	1			T3	1		T4	34		T10	4
valid_sources[0x43]	12369	1			T4	74		T9	1		T10	6
valid_sources[0x44]	14551	1			T4	59		T9	5		T10	7
valid_sources[0x45]	13737	1			T4	50		T10	10		T13	2
valid_sources[0x46]	10976	1			T3	2		T4	63		T9	5
valid_sources[0x47]	11243	1			T4	45		T9	6		T10	8
valid_sources[0x48]	11389	1			T4	32		T10	6		T13	4
valid_sources[0x49]	10953	1			T4	33		T9	5		T10	5
valid_sources[0x4a]	12103	1			T4	25		T9	8		T10	7
valid_sources[0x4b]	14933	1			T4	43		T9	3		T10	15
valid_sources[0x4c]	12162	1			T4	20		T9	1		T10	5
valid_sources[0x4d]	13814	1			T4	34		T9	1		T10	2
valid_sources[0x4e]	10328	1			T4	63		T9	1		T10	2
valid_sources[0x4f]	11372	1			T4	31		T10	3		T14	9
valid_sources[0x50]	10347	1			T4	20		T10	9		T13	2
valid_sources[0x51]	10869	1			T4	65		T9	4		T10	10
valid_sources[0x52]	10288	1			T4	11		T9	7		T10	10
valid_sources[0x53]	10447	1			T4	36		T10	14		T13	3
valid_sources[0x54]	10604	1			T4	19		T9	14		T10	13
valid_sources[0x55]	51267	1			T4	31		T10	2		T15	141
valid_sources[0x56]	10532	1			T3	2		T4	12		T10	12
valid_sources[0x57]	11554	1			T4	49		T9	3		T10	6
valid_sources[0x58]	11033	1			T4	75		T9	5		T10	5
valid_sources[0x59]	11749	1			T4	39		T10	6		T13	2
valid_sources[0x5a]	11431	1			T4	25		T10	8		T13	4
valid_sources[0x5b]	11040	1			T4	59		T10	12		T13	2
valid_sources[0x5c]	10474	1			T4	42		T9	5		T10	7
valid_sources[0x5d]	11347	1			T4	10		T9	2		T10	3
valid_sources[0x5e]	11676	1			T4	40		T9	1		T10	3
valid_sources[0x5f]	14079	1			T3	1		T4	60		T9	2
valid_sources[0x60]	10973	1			T4	30		T10	7		T13	1
valid_sources[0x61]	10673	1			T4	50		T10	8		T13	1
valid_sources[0x62]	11199	1			T3	1		T4	38		T9	4
valid_sources[0x63]	10553	1			T4	49		T10	8		T15	143
valid_sources[0x64]	12428	1			T4	59		T10	11		T13	5
valid_sources[0x65]	12837	1			T4	84		T9	1		T10	4
valid_sources[0x66]	10816	1			T3	1		T4	28		T9	2
valid_sources[0x67]	10784	1			T4	50		T9	1		T10	10
valid_sources[0x68]	11196	1			T4	57		T9	11		T10	12
valid_sources[0x69]	11021	1			T4	31		T10	9		T13	1
valid_sources[0x6a]	12275	1			T4	27		T9	2		T10	3
valid_sources[0x6b]	12178	1			T4	39		T9	4		T10	8
valid_sources[0x6c]	11274	1			T4	42		T9	8		T10	7
valid_sources[0x6d]	11343	1			T4	51		T9	2		T10	6
valid_sources[0x6e]	11863	1			T4	48		T9	3		T10	6
valid_sources[0x6f]	154165	1			T4	15		T9	4		T10	4
valid_sources[0x70]	12104	1			T3	1		T4	46		T10	5
valid_sources[0x71]	10817	1			T4	5		T10	9		T13	1
valid_sources[0x72]	10673	1			T3	1		T4	32		T9	9
valid_sources[0x73]	10640	1			T4	62		T9	3		T10	7
valid_sources[0x74]	15533	1			T3	1		T4	50		T9	1
valid_sources[0x75]	10620	1			T4	68		T9	2		T10	6
valid_sources[0x76]	10820	1			T4	42		T9	2		T10	8
valid_sources[0x77]	11358	1			T4	30		T10	6		T11	4
valid_sources[0x78]	10790	1			T4	30		T9	6		T10	3
valid_sources[0x79]	11152	1			T4	38		T9	5		T10	12
valid_sources[0x7a]	11503	1			T4	16		T9	2		T10	8
valid_sources[0x7b]	10681	1			T4	24		T10	10		T13	1
valid_sources[0x7c]	11177	1			T3	1		T4	45		T10	10
valid_sources[0x7d]	11274	1			T4	4		T9	5		T10	11
valid_sources[0x7e]	11193	1			T4	82		T9	1		T10	12
valid_sources[0x7f]	10579	1			T4	47		T10	6		T14	3
valid_sources[0x80]	14197	1			T4	27		T9	5		T10	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1640167

1

T3

10

T4

2252

T9

193

values[0x0]

all_enables

biggest_size

156795

1

T3

10

T4

2234

T9

58

values[0x1]

all_enables

biggest_size

154768

1

T3

6

T4

2189

T9

31