Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	119036355	15493	0	0
claim_transition_if_regwen_rd_A	119036355	1517	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119036355	15493	0	0
T4	111598	1	0	0
T9	208578	0	0	0
T10	29234	0	0	0
T11	4502	0	0	0
T12	29383	0	0	0
T13	6584	0	0	0
T14	4343	0	0	0
T15	103250	0	0	0
T16	24565	0	0	0
T36	1417	0	0	0
T45	0	2	0	0
T46	0	5	0	0
T47	0	6	0	0
T88	0	3	0	0
T97	0	1	0	0
T100	0	3	0	0
T136	0	2	0	0
T137	0	10	0	0
T138	0	13	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119036355	1517	0	0
T97	228483	3	0	0
T98	476777	0	0	0
T105	0	18	0	0
T122	0	2	0	0
T128	0	61	0	0
T136	125116	0	0	0
T139	0	10	0	0
T140	0	3	0	0
T141	0	11	0	0
T142	0	97	0	0
T143	0	25	0	0
T144	0	8	0	0
T145	112321	0	0	0
T146	24838	0	0	0
T147	73362	0	0	0
T148	25677	0	0	0
T149	4147	0	0	0
T150	3692	0	0	0
T151	2522	0	0	0