Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1343576	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1555022

1

T1

172

T2

862

T3

134

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2568504	1			T1	138		T2	908		T3	115
values[0x0]	164324	1			T1	72		T2	256		T3	59
values[0x1]	165770	1			T1	56		T2	240		T3	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1065291	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1833307

1

T1

186

T2

967

T3

154

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14033	1			T7	5		T13	1		T15	6
valid_sources[0x01]	8970	1			T1	1		T2	2		T4	3
valid_sources[0x02]	8659	1			T2	4		T4	1		T11	1
valid_sources[0x03]	8919	1			T11	2		T7	4		T15	8
valid_sources[0x04]	9475	1			T4	1		T5	3		T11	1
valid_sources[0x05]	8518	1			T2	3		T6	2		T7	1
valid_sources[0x06]	11926	1			T7	1		T13	3		T15	6
valid_sources[0x07]	8639	1			T10	22		T4	3		T7	1
valid_sources[0x08]	9235	1			T1	2		T2	4		T4	27
valid_sources[0x09]	8525	1			T1	7		T2	3		T10	13
valid_sources[0x0a]	8499	1			T5	23		T7	3		T15	8
valid_sources[0x0b]	19509	1			T2	11		T7	1		T13	3
valid_sources[0x0c]	8774	1			T2	3		T10	3		T4	5
valid_sources[0x0d]	8440	1			T1	2		T2	4		T11	1
valid_sources[0x0e]	10110	1			T1	1		T7	1		T15	14
valid_sources[0x0f]	9146	1			T1	2		T6	1		T7	2
valid_sources[0x10]	8509	1			T2	22		T10	13		T7	2
valid_sources[0x11]	8532	1			T1	1		T2	2		T11	1
valid_sources[0x12]	10587	1			T2	23		T10	3		T4	14
valid_sources[0x13]	10218	1			T1	2		T4	6		T13	18
valid_sources[0x14]	8687	1			T2	9		T10	24		T6	1
valid_sources[0x15]	29526	1			T1	3		T2	13		T11	1
valid_sources[0x16]	9428	1			T1	1		T2	13		T10	23
valid_sources[0x17]	10303	1			T2	6		T10	11		T5	4
valid_sources[0x18]	10368	1			T2	11		T5	9		T11	2
valid_sources[0x19]	8592	1			T2	9		T10	5		T4	11
valid_sources[0x1a]	10907	1			T7	1		T35	6		T15	8
valid_sources[0x1b]	8765	1			T1	1		T2	6		T4	13
valid_sources[0x1c]	8608	1			T2	5		T6	1		T11	2
valid_sources[0x1d]	8815	1			T2	5		T10	4		T4	7
valid_sources[0x1e]	9286	1			T1	2		T2	20		T10	1
valid_sources[0x1f]	8654	1			T1	1		T2	8		T10	13
valid_sources[0x20]	9760	1			T2	13		T11	1		T7	3
valid_sources[0x21]	8698	1			T2	1		T5	16		T11	1
valid_sources[0x22]	20825	1			T2	21		T10	1		T4	17
valid_sources[0x23]	9217	1			T1	1		T2	2		T10	36
valid_sources[0x24]	8856	1			T4	12		T6	1		T11	1
valid_sources[0x25]	58646	1			T2	12		T7	2		T13	2
valid_sources[0x26]	9829	1			T2	7		T10	17		T5	1
valid_sources[0x27]	10188	1			T2	14		T11	1		T7	2
valid_sources[0x28]	9655	1			T2	1		T7	1		T15	9
valid_sources[0x29]	8601	1			T2	3		T11	2		T7	1
valid_sources[0x2a]	9049	1			T1	1		T2	3		T4	4
valid_sources[0x2b]	9535	1			T2	4		T11	2		T7	2
valid_sources[0x2c]	8430	1			T2	11		T11	2		T13	5
valid_sources[0x2d]	9058	1			T1	7		T5	24		T6	2
valid_sources[0x2e]	8979	1			T2	9		T11	1		T13	3
valid_sources[0x2f]	8647	1			T2	14		T4	6		T5	1
valid_sources[0x30]	8510	1			T1	1		T2	5		T11	1
valid_sources[0x31]	8459	1			T1	4		T2	5		T5	1
valid_sources[0x32]	8761	1			T1	1		T2	12		T10	72
valid_sources[0x33]	11156	1			T1	7		T2	24		T7	1
valid_sources[0x34]	8523	1			T11	2		T7	4		T35	26
valid_sources[0x35]	8349	1			T1	3		T2	6		T5	10
valid_sources[0x36]	9240	1			T1	2		T2	6		T15	3
valid_sources[0x37]	8510	1			T1	1		T2	6		T13	1
valid_sources[0x38]	10992	1			T2	9		T11	1		T7	2
valid_sources[0x39]	8767	1			T2	5		T10	12		T13	1
valid_sources[0x3a]	9299	1			T11	1		T7	2		T15	15
valid_sources[0x3b]	12386	1			T1	5		T2	12		T11	1
valid_sources[0x3c]	9100	1			T7	2		T15	5		T33	5
valid_sources[0x3d]	8922	1			T2	5		T11	1		T7	3
valid_sources[0x3e]	9503	1			T1	3		T2	3		T11	1
valid_sources[0x3f]	9796	1			T2	7		T5	9		T11	3
valid_sources[0x40]	8538	1			T2	11		T4	8		T11	1
valid_sources[0x41]	8667	1			T2	8		T4	2		T7	1
valid_sources[0x42]	8737	1			T2	1		T10	8		T7	2
valid_sources[0x43]	8975	1			T1	2		T7	3		T13	5
valid_sources[0x44]	17178	1			T2	9		T10	17		T6	1
valid_sources[0x45]	8695	1			T1	3		T7	1		T13	4
valid_sources[0x46]	8767	1			T1	1		T2	2		T4	1
valid_sources[0x47]	8688	1			T4	11		T5	7		T11	3
valid_sources[0x48]	8403	1			T1	3		T2	6		T10	23
valid_sources[0x49]	76020	1			T2	6		T6	1		T11	1
valid_sources[0x4a]	8560	1			T1	1		T2	7		T10	8
valid_sources[0x4b]	10116	1			T10	9		T4	9		T11	1
valid_sources[0x4c]	8572	1			T2	9		T6	1		T11	1
valid_sources[0x4d]	10331	1			T2	4		T4	2		T5	28
valid_sources[0x4e]	73585	1			T5	12		T11	2		T7	2
valid_sources[0x4f]	10832	1			T2	4		T7	2		T13	8
valid_sources[0x50]	8343	1			T4	1		T7	1		T13	1
valid_sources[0x51]	8563	1			T2	12		T7	4		T13	1
valid_sources[0x52]	9112	1			T1	1		T2	8		T11	1
valid_sources[0x53]	11361	1			T2	3		T4	11		T5	4
valid_sources[0x54]	8461	1			T1	4		T4	1		T7	1
valid_sources[0x55]	8853	1			T2	3		T10	76		T11	1
valid_sources[0x56]	8513	1			T1	4		T2	13		T10	4
valid_sources[0x57]	8408	1			T10	28		T11	1		T13	1
valid_sources[0x58]	9765	1			T11	3		T7	1		T13	1
valid_sources[0x59]	10479	1			T1	1		T2	8		T10	5
valid_sources[0x5a]	8232	1			T1	4		T2	19		T6	1
valid_sources[0x5b]	10134	1			T4	22		T7	4		T33	7
valid_sources[0x5c]	10074	1			T2	12		T10	28		T6	1
valid_sources[0x5d]	8679	1			T2	12		T10	20		T7	1
valid_sources[0x5e]	8637	1			T1	4		T11	1		T13	3
valid_sources[0x5f]	8703	1			T1	4		T2	6		T6	1
valid_sources[0x60]	8555	1			T4	1		T7	2		T35	8
valid_sources[0x61]	9047	1			T11	1		T7	2		T13	5
valid_sources[0x62]	8384	1			T1	5		T2	2		T11	1
valid_sources[0x63]	8588	1			T1	2		T2	16		T11	1
valid_sources[0x64]	9222	1			T1	1		T2	3		T7	1
valid_sources[0x65]	9349	1			T1	7		T10	2		T4	10
valid_sources[0x66]	8956	1			T2	1		T6	2		T35	30
valid_sources[0x67]	8443	1			T2	7		T10	27		T11	2
valid_sources[0x68]	8734	1			T2	3		T6	1		T7	1
valid_sources[0x69]	13267	1			T2	6		T10	1		T4	2
valid_sources[0x6a]	8713	1			T1	3		T2	17		T10	21
valid_sources[0x6b]	9017	1			T1	5		T10	23		T4	27
valid_sources[0x6c]	9083	1			T1	1		T10	60		T4	1
valid_sources[0x6d]	8518	1			T1	5		T15	12		T33	10
valid_sources[0x6e]	8760	1			T2	1		T10	20		T5	22
valid_sources[0x6f]	8699	1			T2	2		T13	3		T15	10
valid_sources[0x70]	8634	1			T2	4		T3	219		T6	1
valid_sources[0x71]	8744	1			T2	1		T5	43		T6	1
valid_sources[0x72]	9135	1			T11	1		T7	1		T13	3
valid_sources[0x73]	8414	1			T1	2		T11	2		T7	3
valid_sources[0x74]	8417	1			T2	17		T4	18		T11	1
valid_sources[0x75]	9346	1			T1	2		T10	15		T11	1
valid_sources[0x76]	9703	1			T1	1		T2	2		T13	9
valid_sources[0x77]	9794	1			T5	22		T6	3		T11	1
valid_sources[0x78]	13628	1			T2	3		T10	7		T5	8
valid_sources[0x79]	8744	1			T1	4		T2	8		T7	1
valid_sources[0x7a]	10213	1			T10	22		T4	2		T11	1
valid_sources[0x7b]	8537	1			T2	16		T15	3		T33	5
valid_sources[0x7c]	8444	1			T1	3		T2	14		T6	1
valid_sources[0x7d]	8540	1			T1	11		T2	20		T4	8
valid_sources[0x7e]	51410	1			T7	1		T13	6		T15	9
valid_sources[0x7f]	8591	1			T7	2		T13	1		T15	9
valid_sources[0x80]	10653	1			T2	6		T10	16		T7	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1270196

1

T1

62

T2

421

T3

48

values[0x0]

all_enables

biggest_size

142649

1

T1

63

T2

224

T3

50

values[0x1]

all_enables

biggest_size

142177

1

T1

47

T2

217

T3

36