Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	100833776	13958	0	0
claim_transition_if_regwen_rd_A	100833776	1398	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100833776	13958	0	0
T16	196053	3	0	0
T31	184295	0	0	0
T33	49577	0	0	0
T34	37589	0	0	0
T37	0	2	0	0
T40	0	21	0	0
T52	0	4	0	0
T77	22394	0	0	0
T78	52551	0	0	0
T79	1370	0	0	0
T80	20993	0	0	0
T81	117248	0	0	0
T82	26801	0	0	0
T99	0	10	0	0
T139	0	2	0	0
T140	0	3	0	0
T141	0	3	0	0
T142	0	4	0	0
T143	0	3	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100833776	1398	0	0
T18	8043	0	0	0
T26	1566	0	0	0
T27	883	0	0	0
T37	170677	7	0	0
T59	15199	0	0	0
T103	0	12	0	0
T107	0	26	0	0
T122	0	64	0	0
T144	0	18	0	0
T145	0	16	0	0
T146	0	138	0	0
T147	0	82	0	0
T148	0	10	0	0
T149	0	426	0	0
T150	33203	0	0	0
T151	62161	0	0	0
T152	92536	0	0	0
T153	3365	0	0	0
T154	6370	0	0	0