Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.64 100.00 55.56 75.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic 75.00 75.00
tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic 75.00 75.00
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic 85.19 100.00 55.56 100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic 85.19 100.00 55.56 100.00


Module Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
75.00 75.00 gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
75.00 75.00 u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Toggle Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk0_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk1_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sel_i No No No INPUT
clk_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 71304769 71303137 0 0
selKnown1 98805021 98803389 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 71304769 71303137 0 0
T1 17 16 0 0
T2 63 62 0 0
T3 14 13 0 0
T4 76179 76177 0 0
T5 58558 58556 0 0
T6 347486 347484 0 0
T7 47186 47185 0 0
T8 61743 61741 0 0
T9 176018 176016 0 0
T10 71 70 0 0
T11 14 12 0 0
T12 149723 149731 0 0
T13 1 58 0 0
T14 0 113941 0 0
T15 0 297331 0 0
T16 0 126007 0 0
T17 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 98805021 98803389 0 0
T1 8202 8201 0 0
T2 31216 31215 0 0
T3 7365 7364 0 0
T4 61117 61115 0 0
T5 68051 68049 0 0
T6 197467 197465 0 0
T7 4 3 0 0
T8 41240 41238 0 0
T9 156154 156152 0 0
T10 35905 35904 0 0
T11 7012 7010 0 0
T12 1 0 0 0
T13 1 0 0 0
T17 1 0 0 0
T18 0 1 0 0
T19 0 3 0 0
T20 0 1 0 0
T21 0 2 0 0
T22 0 1 0 0
T23 0 6 0 0
T24 0 4 0 0

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk0_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk1_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
sel_i No No No INPUT
clk_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 8 6 75.00
Total Bits 0->1 4 3 75.00
Total Bits 1->0 4 3 75.00

Ports 4 3 75.00
Port Bits 8 6 75.00
Port Bits 0->1 4 3 75.00
Port Bits 1->0 4 3 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk0_i Yes Yes T6,T8,T9 Yes T4,T5,T6 INPUT
clk1_i Yes Yes T4,T5,T7 Yes T4,T5,T7 INPUT
sel_i No No No INPUT
clk_o Yes Yes T6,T8,T9 Yes T4,T5,T6 OUTPUT

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 71252087 71251271 0 0
selKnown1 98804091 98803275 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 71252087 71251271 0 0
T4 76178 76177 0 0
T5 58557 58556 0 0
T6 347467 347466 0 0
T7 47186 47185 0 0
T8 61727 61726 0 0
T9 175956 175955 0 0
T11 1 0 0 0
T12 149723 149722 0 0
T13 1 0 0 0
T14 0 113941 0 0
T15 0 297331 0 0
T16 0 126007 0 0
T17 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 98804091 98803275 0 0
T1 8202 8201 0 0
T2 31216 31215 0 0
T3 7365 7364 0 0
T4 61110 61109 0 0
T5 68047 68046 0 0
T6 197466 197465 0 0
T8 41239 41238 0 0
T9 156153 156152 0 0
T10 35905 35904 0 0
T11 7011 7010 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 52682 51866 0 0
selKnown1 930 114 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 52682 51866 0 0
T1 17 16 0 0
T2 63 62 0 0
T3 14 13 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 19 18 0 0
T8 16 15 0 0
T9 62 61 0 0
T10 71 70 0 0
T11 13 12 0 0
T12 0 9 0 0
T13 0 58 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 930 114 0 0
T4 7 6 0 0
T5 4 3 0 0
T6 1 0 0 0
T7 4 3 0 0
T8 1 0 0 0
T9 1 0 0 0
T11 1 0 0 0
T12 1 0 0 0
T13 1 0 0 0
T17 1 0 0 0
T18 0 1 0 0
T19 0 3 0 0
T20 0 1 0 0
T21 0 2 0 0
T22 0 1 0 0
T23 0 6 0 0
T24 0 4 0 0

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