Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	879548	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1067992

1

T1

594

T3

235

T4

25303

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1656892	1			T1	491		T3	213		T4	48226
values[0x0]	144878	1			T1	195		T3	99		T4	638
values[0x1]	145770	1			T1	229		T3	86		T4	630

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	696246	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1251294

1

T1

667

T3

276

T4

30184

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4814	1			T1	8		T3	1		T4	193
valid_sources[0x01]	4592	1			T1	5		T3	3		T4	219
valid_sources[0x02]	75016	1			T3	1		T4	218		T6	5
valid_sources[0x03]	6332	1			T1	7		T3	3		T4	193
valid_sources[0x04]	4760	1			T1	2		T3	3		T4	191
valid_sources[0x05]	4909	1			T1	1		T3	2		T4	185
valid_sources[0x06]	4709	1			T1	2		T4	188		T6	3
valid_sources[0x07]	7366	1			T1	2		T3	2		T4	223
valid_sources[0x08]	4960	1			T1	2		T4	183		T6	1
valid_sources[0x09]	4928	1			T1	3		T3	4		T4	223
valid_sources[0x0a]	7458	1			T1	5		T4	198		T6	1
valid_sources[0x0b]	11172	1			T1	1		T3	4		T4	177
valid_sources[0x0c]	6362	1			T1	4		T3	1		T4	204
valid_sources[0x0d]	4401	1			T1	2		T4	170		T6	3
valid_sources[0x0e]	4753	1			T1	3		T3	2		T4	224
valid_sources[0x0f]	4896	1			T1	5		T3	1		T4	196
valid_sources[0x10]	97108	1			T1	5		T3	3		T4	197
valid_sources[0x11]	6239	1			T1	1		T4	148		T6	1
valid_sources[0x12]	4987	1			T1	2		T3	1		T4	197
valid_sources[0x13]	4667	1			T1	1		T3	1		T4	163
valid_sources[0x14]	4958	1			T1	7		T4	188		T6	4
valid_sources[0x15]	4990	1			T1	3		T3	6		T4	205
valid_sources[0x16]	4889	1			T1	2		T3	3		T4	168
valid_sources[0x17]	4694	1			T1	8		T4	203		T6	1
valid_sources[0x18]	5712	1			T1	1		T3	2		T4	171
valid_sources[0x19]	4871	1			T1	1		T3	2		T4	196
valid_sources[0x1a]	4744	1			T1	2		T3	1		T4	160
valid_sources[0x1b]	4909	1			T1	2		T3	4		T4	179
valid_sources[0x1c]	5065	1			T1	2		T4	164		T6	3
valid_sources[0x1d]	4797	1			T1	5		T4	205		T7	2
valid_sources[0x1e]	4828	1			T1	1		T4	191		T6	3
valid_sources[0x1f]	4825	1			T1	4		T3	3		T4	206
valid_sources[0x20]	4730	1			T1	10		T3	1		T4	200
valid_sources[0x21]	4870	1			T1	2		T3	1		T4	183
valid_sources[0x22]	54692	1			T1	2		T3	1		T4	195
valid_sources[0x23]	4840	1			T1	3		T3	1		T4	189
valid_sources[0x24]	4769	1			T1	3		T4	194		T6	4
valid_sources[0x25]	4754	1			T1	3		T3	1		T4	192
valid_sources[0x26]	4726	1			T1	4		T3	2		T4	219
valid_sources[0x27]	4677	1			T1	5		T4	206		T6	3
valid_sources[0x28]	6318	1			T1	2		T3	2		T4	221
valid_sources[0x29]	5196	1			T1	2		T3	1		T4	158
valid_sources[0x2a]	4617	1			T1	4		T3	3		T4	180
valid_sources[0x2b]	5827	1			T1	7		T4	207		T6	2
valid_sources[0x2c]	39512	1			T1	2		T3	3		T4	147
valid_sources[0x2d]	4985	1			T1	10		T3	6		T4	187
valid_sources[0x2e]	24369	1			T4	201		T6	1		T7	2
valid_sources[0x2f]	4719	1			T1	4		T3	4		T4	193
valid_sources[0x30]	4769	1			T1	3		T4	182		T6	2
valid_sources[0x31]	24908	1			T1	7		T4	205		T6	2
valid_sources[0x32]	5035	1			T1	4		T3	1		T4	211
valid_sources[0x33]	5465	1			T1	3		T3	1		T4	211
valid_sources[0x34]	4772	1			T1	10		T3	2		T4	207
valid_sources[0x35]	5545	1			T1	1		T3	2		T4	189
valid_sources[0x36]	4640	1			T1	4		T3	1		T4	197
valid_sources[0x37]	6352	1			T1	7		T3	1		T4	180
valid_sources[0x38]	7000	1			T1	3		T3	2		T4	208
valid_sources[0x39]	5004	1			T1	1		T4	176		T7	1
valid_sources[0x3a]	6346	1			T1	2		T4	179		T6	2
valid_sources[0x3b]	5973	1			T1	2		T3	7		T4	173
valid_sources[0x3c]	4622	1			T1	4		T4	174		T7	5
valid_sources[0x3d]	6739	1			T1	2		T3	1		T4	189
valid_sources[0x3e]	8239	1			T1	7		T3	2		T4	207
valid_sources[0x3f]	4863	1			T1	4		T3	1		T4	150
valid_sources[0x40]	21809	1			T1	3		T4	181		T6	1
valid_sources[0x41]	4714	1			T1	5		T3	2		T4	213
valid_sources[0x42]	4869	1			T1	3		T4	147		T5	2
valid_sources[0x43]	7886	1			T1	5		T3	3		T4	208
valid_sources[0x44]	6881	1			T1	2		T3	2		T4	222
valid_sources[0x45]	6986	1			T1	15		T3	2		T4	179
valid_sources[0x46]	5281	1			T1	4		T3	3		T4	202
valid_sources[0x47]	4757	1			T1	2		T3	2		T4	173
valid_sources[0x48]	4563	1			T1	2		T3	4		T4	176
valid_sources[0x49]	4980	1			T1	1		T3	1		T4	220
valid_sources[0x4a]	6203	1			T1	5		T3	1		T4	189
valid_sources[0x4b]	4827	1			T1	4		T3	2		T4	219
valid_sources[0x4c]	11009	1			T1	3		T4	216		T7	2
valid_sources[0x4d]	4858	1			T1	5		T4	209		T6	1
valid_sources[0x4e]	4680	1			T1	6		T4	203		T7	4
valid_sources[0x4f]	4985	1			T1	5		T4	195		T5	6
valid_sources[0x50]	5179	1			T1	3		T3	1		T4	199
valid_sources[0x51]	6590	1			T1	6		T3	2		T4	228
valid_sources[0x52]	6485	1			T1	4		T3	1		T4	213
valid_sources[0x53]	8723	1			T1	4		T3	1		T4	183
valid_sources[0x54]	4464	1			T1	2		T4	210		T7	6
valid_sources[0x55]	5007	1			T1	7		T3	1		T4	206
valid_sources[0x56]	5772	1			T1	1		T3	1		T4	202
valid_sources[0x57]	19693	1			T1	3		T4	203		T7	4
valid_sources[0x58]	4535	1			T1	1		T4	150		T6	3
valid_sources[0x59]	4747	1			T1	7		T3	3		T4	226
valid_sources[0x5a]	6690	1			T1	4		T4	169		T6	2
valid_sources[0x5b]	4950	1			T1	5		T4	232		T7	10
valid_sources[0x5c]	10173	1			T1	3		T4	172		T6	3
valid_sources[0x5d]	4608	1			T1	5		T3	3		T4	193
valid_sources[0x5e]	4840	1			T1	1		T4	215		T6	4
valid_sources[0x5f]	6714	1			T1	1		T3	3		T4	237
valid_sources[0x60]	66458	1			T1	5		T3	3		T4	214
valid_sources[0x61]	4831	1			T1	4		T3	2		T4	192
valid_sources[0x62]	5543	1			T1	2		T3	3		T4	185
valid_sources[0x63]	15118	1			T1	2		T3	2		T4	192
valid_sources[0x64]	9592	1			T3	2		T4	216		T6	1
valid_sources[0x65]	5873	1			T1	2		T3	1		T4	178
valid_sources[0x66]	5009	1			T1	4		T3	2		T4	230
valid_sources[0x67]	4898	1			T1	6		T4	213		T6	2
valid_sources[0x68]	4690	1			T1	4		T3	1		T4	166
valid_sources[0x69]	4965	1			T3	5		T4	221		T6	5
valid_sources[0x6a]	5089	1			T1	3		T3	3		T4	176
valid_sources[0x6b]	4538	1			T1	3		T4	166		T6	2
valid_sources[0x6c]	5101	1			T1	3		T3	2		T4	208
valid_sources[0x6d]	6146	1			T1	6		T3	3		T4	191
valid_sources[0x6e]	6202	1			T1	8		T3	4		T4	204
valid_sources[0x6f]	5380	1			T1	8		T3	3		T4	163
valid_sources[0x70]	4994	1			T1	2		T4	186		T6	1
valid_sources[0x71]	16728	1			T1	6		T3	2		T4	203
valid_sources[0x72]	5509	1			T4	193		T6	2		T7	2
valid_sources[0x73]	4836	1			T1	14		T4	158		T6	2
valid_sources[0x74]	4911	1			T1	5		T4	225		T7	4
valid_sources[0x75]	5086	1			T1	3		T4	216		T6	2
valid_sources[0x76]	4876	1			T1	2		T3	3		T4	168
valid_sources[0x77]	5090	1			T1	1		T3	2		T4	182
valid_sources[0x78]	4848	1			T1	5		T4	181		T6	2
valid_sources[0x79]	4909	1			T1	3		T3	4		T4	231
valid_sources[0x7a]	5049	1			T1	3		T3	3		T4	214
valid_sources[0x7b]	4741	1			T1	2		T3	4		T4	189
valid_sources[0x7c]	6217	1			T1	1		T4	192		T6	3
valid_sources[0x7d]	4691	1			T1	7		T4	157		T6	1
valid_sources[0x7e]	8761	1			T1	2		T4	210		T6	1
valid_sources[0x7f]	4853	1			T1	2		T3	3		T4	201
valid_sources[0x80]	4814	1			T1	6		T3	2		T4	180

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

818100

1

T1

225

T3

106

T4

24202

values[0x0]

all_enables

biggest_size

125512

1

T1

169

T3

77

T4

547

values[0x1]

all_enables

biggest_size

124380

1

T1

200

T3

52

T4

554