Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	60739648	14900	0	0
claim_transition_if_regwen_rd_A	60739648	787	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60739648	14900	0	0
T25	28626	0	0	0
T41	25817	0	0	0
T55	188841	1	0	0
T67	4665	0	0	0
T84	0	15	0	0
T85	0	5	0	0
T109	0	3	0	0
T148	0	1	0	0
T149	0	4	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	27524	0	0	0
T155	1140	0	0	0
T156	1113	0	0	0
T157	6713	0	0	0
T158	27793	0	0	0
T159	23974	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60739648	787	0	0
T71	267495	0	0	0
T72	6373	0	0	0
T85	151839	8	0	0
T110	0	10	0	0
T113	0	8	0	0
T160	0	4	0	0
T161	0	10	0	0
T162	0	130	0	0
T163	0	11	0	0
T164	0	7	0	0
T165	0	4	0	0
T166	0	22	0	0
T167	1167	0	0	0
T168	45091	0	0	0
T169	29379	0	0	0
T170	28489	0	0	0
T171	29362	0	0	0
T172	23802	0	0	0
T173	26071	0	0	0