Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	823655	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1012416

1

T1

21171

T2

1716

T3

1244

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1541225	1			T1	37833		T2	2362		T3	1269
values[0x0]	147357	1			T1	1395		T2	331		T3	372
values[0x1]	147489	1			T1	1393		T2	341		T3	364

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	651958	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1184113

1

T1

25215

T2

1980

T3

1418

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6480	1			T1	145		T2	6		T3	5
valid_sources[0x01]	5958	1			T1	149		T2	13		T3	9
valid_sources[0x02]	5874	1			T1	167		T2	12		T3	6
valid_sources[0x03]	5876	1			T1	118		T2	13		T3	6
valid_sources[0x04]	6242	1			T1	115		T2	12		T3	7
valid_sources[0x05]	6474	1			T1	122		T2	17		T3	8
valid_sources[0x06]	50449	1			T1	134		T2	10		T3	8
valid_sources[0x07]	6496	1			T1	168		T2	11		T3	2
valid_sources[0x08]	7189	1			T1	209		T2	8		T3	4
valid_sources[0x09]	6488	1			T1	155		T2	15		T3	7
valid_sources[0x0a]	6279	1			T1	217		T2	14		T3	9
valid_sources[0x0b]	6530	1			T1	186		T2	19		T3	5
valid_sources[0x0c]	7566	1			T1	101		T2	11		T3	10
valid_sources[0x0d]	6024	1			T1	242		T2	7		T3	10
valid_sources[0x0e]	7123	1			T1	126		T2	2		T3	8
valid_sources[0x0f]	7184	1			T1	157		T2	11		T3	7
valid_sources[0x10]	6130	1			T1	166		T2	14		T3	9
valid_sources[0x11]	6373	1			T1	178		T2	12		T3	10
valid_sources[0x12]	5995	1			T1	140		T2	11		T3	6
valid_sources[0x13]	6316	1			T1	148		T2	12		T3	6
valid_sources[0x14]	5935	1			T1	158		T2	15		T3	6
valid_sources[0x15]	6260	1			T1	136		T2	11		T3	12
valid_sources[0x16]	6240	1			T1	170		T2	17		T3	7
valid_sources[0x17]	6252	1			T1	140		T2	14		T3	3
valid_sources[0x18]	9876	1			T1	192		T2	12		T3	6
valid_sources[0x19]	6243	1			T1	149		T2	18		T3	7
valid_sources[0x1a]	6446	1			T1	194		T2	14		T3	9
valid_sources[0x1b]	6386	1			T1	108		T2	20		T3	7
valid_sources[0x1c]	9039	1			T1	144		T2	10		T3	5
valid_sources[0x1d]	9089	1			T1	172		T2	8		T3	3
valid_sources[0x1e]	6456	1			T1	208		T2	8		T3	6
valid_sources[0x1f]	6191	1			T1	160		T2	17		T3	9
valid_sources[0x20]	6426	1			T1	200		T2	13		T3	4
valid_sources[0x21]	6322	1			T1	144		T2	18		T3	3
valid_sources[0x22]	6136	1			T1	98		T2	4		T3	11
valid_sources[0x23]	14640	1			T1	248		T2	14		T3	4
valid_sources[0x24]	5902	1			T1	114		T2	12		T3	5
valid_sources[0x25]	5974	1			T1	137		T2	12		T3	5
valid_sources[0x26]	6160	1			T1	193		T2	10		T3	8
valid_sources[0x27]	6817	1			T1	139		T2	9		T3	4
valid_sources[0x28]	9771	1			T1	143		T2	7		T3	5
valid_sources[0x29]	7065	1			T1	175		T2	8		T3	7
valid_sources[0x2a]	5999	1			T1	126		T2	13		T3	3
valid_sources[0x2b]	7591	1			T1	162		T2	8		T3	14
valid_sources[0x2c]	6201	1			T1	138		T2	13		T3	10
valid_sources[0x2d]	6067	1			T1	169		T2	11		T3	7
valid_sources[0x2e]	6001	1			T1	168		T2	11		T3	9
valid_sources[0x2f]	6641	1			T1	228		T2	17		T3	14
valid_sources[0x30]	5955	1			T1	233		T2	10		T3	2
valid_sources[0x31]	6126	1			T1	153		T2	15		T3	5
valid_sources[0x32]	6213	1			T1	163		T2	11		T3	3
valid_sources[0x33]	6288	1			T1	210		T2	10		T3	2
valid_sources[0x34]	6002	1			T1	133		T2	14		T3	5
valid_sources[0x35]	6152	1			T1	155		T2	9		T3	13
valid_sources[0x36]	6435	1			T1	208		T2	18		T3	5
valid_sources[0x37]	6058	1			T1	178		T2	12		T3	7
valid_sources[0x38]	6041	1			T1	151		T2	12		T3	5
valid_sources[0x39]	6104	1			T1	140		T2	19		T3	3
valid_sources[0x3a]	6216	1			T1	178		T2	17		T3	8
valid_sources[0x3b]	6023	1			T1	96		T2	15		T3	7
valid_sources[0x3c]	6207	1			T1	95		T2	14		T3	4
valid_sources[0x3d]	6974	1			T1	208		T2	10		T3	5
valid_sources[0x3e]	6701	1			T1	201		T2	7		T3	14
valid_sources[0x3f]	6516	1			T1	210		T2	14		T3	6
valid_sources[0x40]	6193	1			T1	146		T2	17		T3	5
valid_sources[0x41]	6090	1			T1	134		T2	15		T3	8
valid_sources[0x42]	5811	1			T1	131		T2	11		T3	8
valid_sources[0x43]	6130	1			T1	108		T2	7		T3	23
valid_sources[0x44]	6010	1			T1	115		T2	10		T3	10
valid_sources[0x45]	6212	1			T1	166		T2	12		T3	8
valid_sources[0x46]	10238	1			T1	135		T2	13		T3	14
valid_sources[0x47]	7949	1			T1	94		T2	7		T3	3
valid_sources[0x48]	7772	1			T1	123		T2	15		T3	18
valid_sources[0x49]	6067	1			T1	160		T2	19		T3	10
valid_sources[0x4a]	6237	1			T1	161		T2	4		T3	5
valid_sources[0x4b]	6162	1			T1	185		T2	13		T3	10
valid_sources[0x4c]	6023	1			T1	167		T2	16		T3	12
valid_sources[0x4d]	7004	1			T1	143		T2	10		T3	5
valid_sources[0x4e]	6068	1			T1	186		T2	14		T3	10
valid_sources[0x4f]	6021	1			T1	203		T2	11		T3	2
valid_sources[0x50]	6035	1			T1	128		T2	11		T3	6
valid_sources[0x51]	6103	1			T1	145		T2	12		T3	4
valid_sources[0x52]	9311	1			T1	192		T2	17		T3	12
valid_sources[0x53]	6144	1			T1	178		T2	12		T3	14
valid_sources[0x54]	6149	1			T1	170		T2	12		T3	12
valid_sources[0x55]	6007	1			T1	179		T2	13		T3	6
valid_sources[0x56]	13651	1			T1	145		T2	13		T3	6
valid_sources[0x57]	6153	1			T1	140		T2	8		T3	17
valid_sources[0x58]	7922	1			T1	205		T2	13		T3	4
valid_sources[0x59]	7267	1			T1	165		T2	8		T3	5
valid_sources[0x5a]	6368	1			T1	154		T2	9		T3	4
valid_sources[0x5b]	6440	1			T1	136		T2	15		T3	10
valid_sources[0x5c]	6630	1			T1	178		T2	10		T3	8
valid_sources[0x5d]	6264	1			T1	243		T2	16		T3	6
valid_sources[0x5e]	5884	1			T1	185		T2	15		T3	7
valid_sources[0x5f]	6230	1			T1	173		T2	14		T3	6
valid_sources[0x60]	6244	1			T1	169		T2	13		T3	1
valid_sources[0x61]	10942	1			T1	171		T2	12		T3	7
valid_sources[0x62]	6495	1			T1	124		T2	14		T3	5
valid_sources[0x63]	7587	1			T1	114		T2	12		T3	6
valid_sources[0x64]	6048	1			T1	153		T2	16		T3	5
valid_sources[0x65]	6323	1			T1	199		T2	13		T3	13
valid_sources[0x66]	6059	1			T1	202		T2	15		T3	6
valid_sources[0x67]	6067	1			T1	143		T2	15		T3	5
valid_sources[0x68]	5972	1			T1	114		T2	15		T3	9
valid_sources[0x69]	5920	1			T1	193		T2	13		T3	3
valid_sources[0x6a]	6112	1			T1	137		T2	8		T3	5
valid_sources[0x6b]	6727	1			T1	140		T2	13		T3	10
valid_sources[0x6c]	10703	1			T1	172		T2	12		T3	13
valid_sources[0x6d]	7277	1			T1	164		T2	13		T3	16
valid_sources[0x6e]	6031	1			T1	206		T2	13		T3	5
valid_sources[0x6f]	6570	1			T1	255		T2	7		T3	3
valid_sources[0x70]	6224	1			T1	106		T2	17		T3	8
valid_sources[0x71]	6178	1			T1	141		T2	18		T3	10
valid_sources[0x72]	5767	1			T1	140		T2	14		T3	5
valid_sources[0x73]	6401	1			T1	126		T2	9		T3	4
valid_sources[0x74]	5972	1			T1	140		T2	12		T3	10
valid_sources[0x75]	6016	1			T1	171		T2	13		T3	9
valid_sources[0x76]	6416	1			T1	201		T2	8		T3	6
valid_sources[0x77]	6265	1			T1	185		T2	11		T3	9
valid_sources[0x78]	10433	1			T1	142		T2	16		T3	11
valid_sources[0x79]	5821	1			T1	175		T2	5		T3	10
valid_sources[0x7a]	7264	1			T1	115		T2	16		T3	7
valid_sources[0x7b]	13093	1			T1	157		T2	17		T3	6
valid_sources[0x7c]	6013	1			T1	187		T2	10		T3	3
valid_sources[0x7d]	6409	1			T1	184		T2	7		T3	4
valid_sources[0x7e]	6116	1			T1	172		T2	11		T3	12
valid_sources[0x7f]	6098	1			T1	146		T2	5		T3	9
valid_sources[0x80]	6048	1			T1	171		T2	9		T3	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

758827

1

T1

18714

T2

1134

T3

616

values[0x0]

all_enables

biggest_size

127638

1

T1

1216

T2

292

T3

322

values[0x1]

all_enables

biggest_size

125951

1

T1

1241

T2

290

T3

306