Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	61679014	14860	0	0
claim_transition_if_regwen_rd_A	61679014	2091	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61679014	14860	0	0
T45	0	7	0	0
T49	128053	2	0	0
T96	0	8	0	0
T97	0	12	0	0
T100	293882	0	0	0
T113	0	10	0	0
T149	0	8	0	0
T150	0	13	0	0
T151	0	18	0	0
T152	0	5	0	0
T153	0	3	0	0
T154	13705	0	0	0
T155	18992	0	0	0
T156	500052	0	0	0
T157	811	0	0	0
T158	24289	0	0	0
T159	643794	0	0	0
T160	530243	0	0	0
T161	2385	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61679014	2091	0	0
T73	2575	0	0	0
T112	0	2	0	0
T114	0	20	0	0
T115	0	73	0	0
T140	0	29	0	0
T141	0	253	0	0
T142	0	16	0	0
T162	443892	11	0	0
T163	0	7	0	0
T164	0	1	0	0
T165	0	6	0	0
T166	2663	0	0	0
T167	1098	0	0	0
T168	65482	0	0	0
T169	8383	0	0	0
T170	9025	0	0	0
T171	6475	0	0	0
T172	1700	0	0	0
T173	6957	0	0	0