Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	869732	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1060139

1

T1

14

T2

1386

T3

98

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1631032	1			T2	1915		T3	123		T4	555
values[0x0]	149565	1			T1	23		T2	257		T3	61
values[0x1]	149274	1			T1	28		T2	255		T3	60

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	687952	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1241919

1

T1

16

T2

1587

T3

116

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6024	1			T2	12		T11	1		T12	4
valid_sources[0x01]	8845	1			T2	8		T3	1		T14	32
valid_sources[0x02]	7897	1			T2	8		T12	6		T14	45
valid_sources[0x03]	6375	1			T2	11		T14	38		T15	23
valid_sources[0x04]	6006	1			T2	12		T11	1		T12	2
valid_sources[0x05]	6842	1			T2	14		T4	7		T14	27
valid_sources[0x06]	5847	1			T2	5		T3	11		T4	1
valid_sources[0x07]	6050	1			T2	10		T4	3		T11	1
valid_sources[0x08]	7532	1			T2	6		T4	5		T12	24
valid_sources[0x09]	10949	1			T2	5		T4	8		T14	32
valid_sources[0x0a]	5841	1			T2	9		T12	1		T14	31
valid_sources[0x0b]	5939	1			T2	13		T4	1		T12	22
valid_sources[0x0c]	6072	1			T2	11		T4	1		T12	4
valid_sources[0x0d]	5955	1			T2	9		T11	1		T14	33
valid_sources[0x0e]	6046	1			T2	4		T4	5		T14	32
valid_sources[0x0f]	6781	1			T2	10		T4	1		T14	23
valid_sources[0x10]	7208	1			T2	10		T4	4		T14	34
valid_sources[0x11]	6156	1			T2	10		T3	9		T4	2
valid_sources[0x12]	6066	1			T2	10		T4	4		T14	40
valid_sources[0x13]	7595	1			T2	9		T5	5		T14	40
valid_sources[0x14]	6282	1			T2	11		T4	2		T14	39
valid_sources[0x15]	6189	1			T2	13		T4	17		T11	1
valid_sources[0x16]	6288	1			T2	10		T4	5		T14	29
valid_sources[0x17]	5927	1			T2	9		T3	4		T4	6
valid_sources[0x18]	6106	1			T2	9		T4	1		T14	37
valid_sources[0x19]	6776	1			T2	9		T12	17		T14	42
valid_sources[0x1a]	6293	1			T2	12		T11	1		T14	39
valid_sources[0x1b]	6010	1			T2	14		T12	12		T14	42
valid_sources[0x1c]	5768	1			T2	8		T4	3		T14	25
valid_sources[0x1d]	6996	1			T2	6		T4	9		T14	33
valid_sources[0x1e]	6096	1			T2	17		T4	1		T11	1
valid_sources[0x1f]	9375	1			T2	9		T4	4		T5	1
valid_sources[0x20]	6243	1			T2	11		T14	39		T15	18
valid_sources[0x21]	6062	1			T2	3		T4	7		T14	41
valid_sources[0x22]	5773	1			T2	7		T4	5		T14	36
valid_sources[0x23]	7920	1			T2	11		T4	6		T14	34
valid_sources[0x24]	5945	1			T2	4		T4	9		T14	43
valid_sources[0x25]	16245	1			T2	6		T4	2		T11	2
valid_sources[0x26]	8130	1			T2	5		T4	7		T14	36
valid_sources[0x27]	7204	1			T2	9		T4	1		T12	1
valid_sources[0x28]	6938	1			T2	6		T4	4		T14	40
valid_sources[0x29]	6313	1			T2	11		T4	1		T12	7
valid_sources[0x2a]	6547	1			T2	5		T4	6		T12	4
valid_sources[0x2b]	6061	1			T2	11		T4	2		T14	38
valid_sources[0x2c]	6221	1			T2	10		T4	1		T14	36
valid_sources[0x2d]	6279	1			T2	10		T4	3		T11	2
valid_sources[0x2e]	6358	1			T2	10		T4	5		T14	31
valid_sources[0x2f]	6090	1			T2	12		T4	6		T12	37
valid_sources[0x30]	7312	1			T2	7		T14	28		T15	1
valid_sources[0x31]	6511	1			T2	7		T3	3		T4	3
valid_sources[0x32]	7130	1			T2	13		T4	3		T14	30
valid_sources[0x33]	6474	1			T2	6		T4	2		T12	65
valid_sources[0x34]	6307	1			T2	8		T4	2		T11	1
valid_sources[0x35]	5881	1			T2	10		T3	5		T11	2
valid_sources[0x36]	6075	1			T2	12		T4	5		T14	45
valid_sources[0x37]	6464	1			T2	5		T4	1		T14	41
valid_sources[0x38]	6033	1			T2	7		T4	4		T14	34
valid_sources[0x39]	6935	1			T2	8		T4	6		T14	40
valid_sources[0x3a]	6246	1			T2	8		T4	4		T5	4
valid_sources[0x3b]	5829	1			T2	7		T4	2		T11	2
valid_sources[0x3c]	6040	1			T2	17		T4	1		T11	1
valid_sources[0x3d]	6617	1			T2	9		T12	59		T14	37
valid_sources[0x3e]	6195	1			T2	7		T14	35		T15	18
valid_sources[0x3f]	6095	1			T2	10		T4	9		T5	3
valid_sources[0x40]	7590	1			T2	5		T4	5		T14	33
valid_sources[0x41]	5793	1			T2	9		T4	3		T14	27
valid_sources[0x42]	7374	1			T2	12		T12	6		T14	41
valid_sources[0x43]	7539	1			T2	9		T4	2		T14	37
valid_sources[0x44]	5701	1			T2	5		T14	41		T15	8
valid_sources[0x45]	6163	1			T2	4		T4	4		T11	1
valid_sources[0x46]	7400	1			T2	6		T4	3		T5	11
valid_sources[0x47]	7681	1			T2	8		T4	6		T11	2
valid_sources[0x48]	6241	1			T2	9		T4	2		T14	32
valid_sources[0x49]	6175	1			T2	6		T11	2		T14	39
valid_sources[0x4a]	6528	1			T2	10		T14	33		T15	6
valid_sources[0x4b]	8950	1			T2	9		T5	9		T14	33
valid_sources[0x4c]	6621	1			T2	12		T4	6		T12	4
valid_sources[0x4d]	5702	1			T2	10		T14	35		T15	11
valid_sources[0x4e]	6281	1			T2	11		T3	4		T12	14
valid_sources[0x4f]	7650	1			T2	6		T3	4		T4	2
valid_sources[0x50]	66976	1			T2	12		T4	3		T11	1
valid_sources[0x51]	6952	1			T2	13		T4	2		T11	1
valid_sources[0x52]	5876	1			T2	4		T4	1		T14	43
valid_sources[0x53]	8205	1			T2	7		T4	8		T14	34
valid_sources[0x54]	6271	1			T2	12		T4	2		T14	26
valid_sources[0x55]	6112	1			T2	15		T14	36		T15	11
valid_sources[0x56]	10676	1			T2	11		T4	2		T12	8
valid_sources[0x57]	6221	1			T2	7		T4	1		T11	2
valid_sources[0x58]	10844	1			T2	5		T4	9		T11	2
valid_sources[0x59]	10093	1			T2	14		T4	5		T12	6
valid_sources[0x5a]	7335	1			T2	9		T14	32		T15	12
valid_sources[0x5b]	8473	1			T2	6		T4	2		T12	21
valid_sources[0x5c]	7223	1			T2	19		T4	5		T11	1
valid_sources[0x5d]	6139	1			T2	9		T4	5		T12	29
valid_sources[0x5e]	6209	1			T2	5		T12	14		T14	31
valid_sources[0x5f]	6300	1			T2	12		T4	3		T14	35
valid_sources[0x60]	6871	1			T2	12		T14	29		T15	16
valid_sources[0x61]	6103	1			T2	10		T3	22		T4	1
valid_sources[0x62]	6387	1			T2	5		T4	2		T12	4
valid_sources[0x63]	5626	1			T2	9		T4	2		T14	37
valid_sources[0x64]	7588	1			T2	6		T4	8		T12	23
valid_sources[0x65]	6147	1			T2	9		T14	27		T15	8
valid_sources[0x66]	6069	1			T2	5		T4	9		T14	49
valid_sources[0x67]	5909	1			T2	12		T4	4		T12	1
valid_sources[0x68]	6378	1			T2	9		T4	6		T12	13
valid_sources[0x69]	6121	1			T2	10		T11	1		T14	38
valid_sources[0x6a]	5947	1			T2	10		T4	1		T14	36
valid_sources[0x6b]	6172	1			T2	13		T4	4		T14	36
valid_sources[0x6c]	7143	1			T2	11		T4	3		T14	35
valid_sources[0x6d]	10643	1			T2	10		T3	15		T4	3
valid_sources[0x6e]	6105	1			T2	13		T3	10		T4	6
valid_sources[0x6f]	5738	1			T2	14		T4	1		T12	4
valid_sources[0x70]	7269	1			T2	9		T12	35		T14	35
valid_sources[0x71]	6247	1			T2	10		T14	26		T15	26
valid_sources[0x72]	101281	1			T2	9		T4	3		T14	34
valid_sources[0x73]	6880	1			T2	5		T4	9		T14	36
valid_sources[0x74]	6462	1			T2	7		T4	2		T14	37
valid_sources[0x75]	5868	1			T2	7		T4	3		T11	1
valid_sources[0x76]	6989	1			T2	20		T4	3		T14	22
valid_sources[0x77]	7312	1			T2	5		T3	4		T4	2
valid_sources[0x78]	5849	1			T2	13		T4	7		T14	30
valid_sources[0x79]	8552	1			T2	4		T4	3		T14	39
valid_sources[0x7a]	6051	1			T2	11		T4	14		T14	36
valid_sources[0x7b]	7033	1			T2	7		T4	4		T14	34
valid_sources[0x7c]	10737	1			T2	7		T3	12		T4	1
valid_sources[0x7d]	8232	1			T2	12		T4	2		T14	38
valid_sources[0x7e]	7784	1			T2	17		T4	1		T5	5
valid_sources[0x7f]	5903	1			T2	5		T4	5		T11	2
valid_sources[0x80]	7288	1			T2	7		T3	28		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

803080

1

T2

937

T3

67

T4

274

values[0x0]

all_enables

biggest_size

129709

1

T1

9

T2

230

T3

21

values[0x1]

all_enables

biggest_size

127350

1

T1

5

T2

219

T3

10