Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	60943391	13263	0	0
claim_transition_if_regwen_rd_A	60943391	1675	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60943391	13263	0	0
T33	735	0	0	0
T53	0	13	0	0
T87	458518	22	0	0
T88	277465	8	0	0
T89	0	2	0	0
T91	0	8	0	0
T143	0	3	0	0
T144	0	11	0	0
T145	0	6	0	0
T146	0	12	0	0
T147	0	14	0	0
T148	2339	0	0	0
T149	28422	0	0	0
T150	319602	0	0	0
T151	24635	0	0	0
T152	9735	0	0	0
T153	25053	0	0	0
T154	21048	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60943391	1675	0	0
T89	250882	4	0	0
T111	0	8	0	0
T143	118659	0	0	0
T144	337298	0	0	0
T145	163812	0	0	0
T155	0	17	0	0
T156	0	2	0	0
T157	0	46	0	0
T158	0	15	0	0
T159	0	92	0	0
T160	0	424	0	0
T161	0	29	0	0
T162	0	6	0	0
T163	952	0	0	0
T164	5728	0	0	0
T165	341336	0	0	0
T166	17818	0	0	0
T167	10015	0	0	0
T168	403269	0	0	0