Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	769101	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

960194

1

T1

1097

T2

240

T3

4955

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1431590	1			T1	1078		T2	166		T3	9231
values[0x0]	148625	1			T1	358		T2	91		T3	239
values[0x1]	149080	1			T1	322		T2	85		T3	245

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	608228	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1121067

1

T1

1242

T2

260

T3

5875

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5771	1			T1	9		T3	22		T10	5
valid_sources[0x01]	5079	1			T1	5		T3	28		T10	4
valid_sources[0x02]	28096	1			T1	12		T3	69		T10	8
valid_sources[0x03]	5633	1			T1	6		T3	28		T13	10
valid_sources[0x04]	4947	1			T1	4		T3	26		T10	6
valid_sources[0x05]	5324	1			T1	10		T3	39		T10	4
valid_sources[0x06]	5638	1			T1	11		T3	42		T10	1
valid_sources[0x07]	22614	1			T1	3		T3	20		T10	6
valid_sources[0x08]	5330	1			T1	8		T3	31		T10	8
valid_sources[0x09]	5821	1			T1	4		T3	36		T10	5
valid_sources[0x0a]	8922	1			T1	7		T3	40		T10	2
valid_sources[0x0b]	5337	1			T1	9		T3	41		T10	3
valid_sources[0x0c]	9184	1			T1	14		T3	18		T10	6
valid_sources[0x0d]	7250	1			T1	2		T3	30		T10	10
valid_sources[0x0e]	7313	1			T1	3		T3	47		T10	5
valid_sources[0x0f]	6804	1			T1	3		T3	48		T10	10
valid_sources[0x10]	5655	1			T1	9		T3	30		T10	3
valid_sources[0x11]	5074	1			T1	9		T3	34		T10	6
valid_sources[0x12]	5529	1			T1	6		T3	58		T10	3
valid_sources[0x13]	5550	1			T1	11		T3	21		T10	6
valid_sources[0x14]	5625	1			T1	6		T3	26		T13	15
valid_sources[0x15]	5173	1			T1	6		T3	41		T10	5
valid_sources[0x16]	8318	1			T1	3		T3	44		T10	4
valid_sources[0x17]	7852	1			T1	6		T3	51		T10	5
valid_sources[0x18]	5455	1			T1	6		T3	39		T10	7
valid_sources[0x19]	5401	1			T1	7		T3	41		T13	11
valid_sources[0x1a]	5287	1			T1	10		T3	63		T10	7
valid_sources[0x1b]	5175	1			T1	11		T3	30		T10	2
valid_sources[0x1c]	5187	1			T1	3		T3	48		T10	5
valid_sources[0x1d]	5544	1			T1	6		T3	32		T10	2
valid_sources[0x1e]	5512	1			T1	8		T3	45		T10	6
valid_sources[0x1f]	6250	1			T1	9		T3	24		T10	5
valid_sources[0x20]	7602	1			T1	11		T3	40		T10	3
valid_sources[0x21]	6755	1			T1	5		T3	46		T10	6
valid_sources[0x22]	5249	1			T1	2		T3	40		T10	11
valid_sources[0x23]	5293	1			T1	8		T3	28		T10	7
valid_sources[0x24]	6777	1			T1	9		T3	44		T10	5
valid_sources[0x25]	6601	1			T1	2		T3	36		T10	3
valid_sources[0x26]	5424	1			T1	6		T3	23		T10	9
valid_sources[0x27]	5856	1			T1	8		T3	32		T10	10
valid_sources[0x28]	5337	1			T1	9		T3	19		T10	7
valid_sources[0x29]	5326	1			T1	1		T3	42		T10	8
valid_sources[0x2a]	7817	1			T1	11		T3	53		T10	12
valid_sources[0x2b]	6572	1			T1	6		T3	46		T10	2
valid_sources[0x2c]	5523	1			T1	1		T3	42		T10	7
valid_sources[0x2d]	6766	1			T1	6		T3	39		T10	2
valid_sources[0x2e]	5504	1			T1	6		T3	19		T10	2
valid_sources[0x2f]	5380	1			T1	10		T3	30		T10	5
valid_sources[0x30]	5308	1			T1	12		T3	38		T10	4
valid_sources[0x31]	5294	1			T1	12		T3	20		T10	8
valid_sources[0x32]	8248	1			T1	1		T3	33		T10	4
valid_sources[0x33]	6360	1			T1	6		T3	39		T13	11
valid_sources[0x34]	22775	1			T1	9		T3	36		T10	6
valid_sources[0x35]	5790	1			T1	2		T3	33		T13	6
valid_sources[0x36]	5537	1			T1	8		T3	41		T10	3
valid_sources[0x37]	5692	1			T1	6		T3	44		T10	5
valid_sources[0x38]	5342	1			T1	7		T3	19		T10	5
valid_sources[0x39]	9182	1			T1	14		T3	39		T10	7
valid_sources[0x3a]	5537	1			T1	5		T3	29		T10	2
valid_sources[0x3b]	5045	1			T1	13		T3	49		T10	1
valid_sources[0x3c]	5393	1			T1	6		T3	32		T10	4
valid_sources[0x3d]	5738	1			T1	10		T3	54		T10	2
valid_sources[0x3e]	6834	1			T1	3		T3	38		T10	10
valid_sources[0x3f]	5283	1			T1	5		T3	19		T10	5
valid_sources[0x40]	5521	1			T1	9		T3	33		T10	6
valid_sources[0x41]	6716	1			T1	9		T3	51		T10	8
valid_sources[0x42]	5075	1			T1	2		T3	50		T10	5
valid_sources[0x43]	5068	1			T1	3		T3	24		T10	4
valid_sources[0x44]	5473	1			T1	7		T3	39		T10	4
valid_sources[0x45]	5131	1			T1	8		T3	25		T10	6
valid_sources[0x46]	6353	1			T1	2		T3	34		T10	2
valid_sources[0x47]	5969	1			T1	8		T3	55		T10	5
valid_sources[0x48]	5556	1			T1	10		T3	34		T13	8
valid_sources[0x49]	5321	1			T1	8		T3	61		T10	3
valid_sources[0x4a]	5309	1			T1	3		T3	30		T10	1
valid_sources[0x4b]	5621	1			T1	6		T3	26		T10	4
valid_sources[0x4c]	7660	1			T1	3		T3	27		T10	17
valid_sources[0x4d]	5771	1			T1	5		T3	49		T10	3
valid_sources[0x4e]	6541	1			T1	7		T3	24		T10	5
valid_sources[0x4f]	7388	1			T1	8		T3	47		T10	8
valid_sources[0x50]	5433	1			T1	4		T3	16		T10	7
valid_sources[0x51]	5452	1			T1	6		T3	37		T10	1
valid_sources[0x52]	5558	1			T1	7		T3	41		T10	2
valid_sources[0x53]	5864	1			T1	8		T3	47		T10	9
valid_sources[0x54]	5466	1			T1	7		T3	56		T10	8
valid_sources[0x55]	5552	1			T1	12		T3	55		T10	1
valid_sources[0x56]	7129	1			T1	11		T3	34		T10	4
valid_sources[0x57]	7958	1			T1	16		T3	26		T10	8
valid_sources[0x58]	4945	1			T1	2		T3	24		T10	4
valid_sources[0x59]	7466	1			T1	12		T3	78		T10	1
valid_sources[0x5a]	41011	1			T1	5		T3	22		T10	5
valid_sources[0x5b]	6430	1			T1	4		T3	19		T10	6
valid_sources[0x5c]	5428	1			T1	4		T3	36		T10	3
valid_sources[0x5d]	6226	1			T1	5		T3	42		T10	5
valid_sources[0x5e]	5307	1			T1	4		T3	48		T10	7
valid_sources[0x5f]	10406	1			T1	3		T3	32		T10	7
valid_sources[0x60]	6284	1			T1	8		T3	57		T10	4
valid_sources[0x61]	5693	1			T1	8		T3	28		T10	4
valid_sources[0x62]	10687	1			T1	8		T3	55		T10	1
valid_sources[0x63]	5630	1			T1	10		T3	37		T10	4
valid_sources[0x64]	5392	1			T1	8		T3	30		T10	10
valid_sources[0x65]	7204	1			T1	6		T3	30		T13	10
valid_sources[0x66]	5477	1			T1	5		T3	24		T10	7
valid_sources[0x67]	5389	1			T1	16		T3	37		T10	4
valid_sources[0x68]	7947	1			T1	7		T3	54		T10	3
valid_sources[0x69]	5436	1			T1	3		T3	41		T10	1
valid_sources[0x6a]	5484	1			T1	9		T3	28		T13	9
valid_sources[0x6b]	51058	1			T1	6		T3	51		T10	2
valid_sources[0x6c]	5892	1			T1	2		T3	51		T10	1
valid_sources[0x6d]	5380	1			T1	8		T3	26		T10	2
valid_sources[0x6e]	5500	1			T1	7		T3	19		T10	6
valid_sources[0x6f]	5838	1			T1	5		T3	41		T10	8
valid_sources[0x70]	9398	1			T1	5		T3	36		T10	8
valid_sources[0x71]	5674	1			T1	5		T3	37		T10	5
valid_sources[0x72]	7109	1			T1	1		T3	18		T10	7
valid_sources[0x73]	5591	1			T1	3		T3	30		T13	10
valid_sources[0x74]	5237	1			T1	11		T3	58		T10	7
valid_sources[0x75]	5715	1			T1	7		T3	32		T10	7
valid_sources[0x76]	6795	1			T1	3		T3	47		T10	4
valid_sources[0x77]	5684	1			T1	8		T3	31		T10	2
valid_sources[0x78]	6630	1			T1	12		T3	22		T10	3
valid_sources[0x79]	5289	1			T1	8		T3	40		T10	3
valid_sources[0x7a]	6844	1			T1	5		T3	50		T10	4
valid_sources[0x7b]	5389	1			T1	11		T3	20		T10	10
valid_sources[0x7c]	7511	1			T1	5		T3	46		T10	7
valid_sources[0x7d]	7317	1			T1	5		T3	44		T10	20
valid_sources[0x7e]	5388	1			T1	12		T3	57		T10	5
valid_sources[0x7f]	27631	1			T1	7		T3	27		T10	3
valid_sources[0x80]	5591	1			T1	9		T3	28		T10	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

704184

1

T1

500

T2

87

T3

4532

values[0x0]

all_enables

biggest_size

128625

1

T1

309

T2

78

T3

207

values[0x1]

all_enables

biggest_size

127385

1

T1

288

T2

75

T3

216