Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	59728200	14538	0	0
claim_transition_if_regwen_rd_A	59728200	1049	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59728200	14538	0	0
T3	230031	1	0	0
T4	369447	0	0	0
T5	10505	0	0	0
T10	35131	0	0	0
T11	1098	0	0	0
T12	1036	0	0	0
T13	42605	0	0	0
T14	1625	0	0	0
T15	3622	0	0	0
T16	462481	1	0	0
T21	0	3	0	0
T103	0	4	0	0
T135	0	4	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	8	0	0
T140	0	3	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59728200	1049	0	0
T7	83788	0	0	0
T8	3859	0	0	0
T9	20815	0	0	0
T21	214737	2	0	0
T33	26548	0	0	0
T34	3405	0	0	0
T35	1512	0	0	0
T63	40766	0	0	0
T64	251322	0	0	0
T107	0	29	0	0
T137	0	8	0	0
T141	0	2	0	0
T142	0	3	0	0
T143	0	7	0	0
T144	0	8	0	0
T145	0	7	0	0
T146	0	8	0	0
T147	0	2	0	0
T148	29635	0	0	0